1 * ARM Generic Interrupt Controller
3 ARM SMP cores are often associated with a GIC, providing per processor
4 interrupts (PPI), shared processor interrupts (SPI) and software
5 generated interrupts (SGI).
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8 Secondary GICs are cascaded into the upward interrupt controller and do not
11 Main node required properties:
13 - compatible : should be one of:
20 - interrupt-controller : Identifies the node as an interrupt controller
21 - #interrupt-cells : Specifies the number of cells needed to encode an
22 interrupt source. The type shall be a <u32> and the value shall be 3.
24 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
27 The 2nd cell contains the interrupt number for the interrupt type.
28 SPI interrupts are in the range [0-987]. PPI interrupts are in the
31 The 3rd cell is the flags, encoded as follows:
32 bits[3:0] trigger type and level flags.
33 1 = low-to-high edge triggered
34 2 = high-to-low edge triggered
35 4 = active high level-sensitive
36 8 = active low level-sensitive
37 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
38 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
39 the interrupt is wired to that CPU. Only valid for PPI interrupts.
41 - reg : Specifies base physical address(s) and size of the GIC registers. The
42 first region is the GIC distributor register base and size. The 2nd region is
43 the GIC cpu interface register base and size.
46 - interrupts : Interrupt source of the parent interrupt controller on
47 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
50 - cpu-offset : per-cpu offset within the distributor and cpu interface
51 regions, used when the GIC doesn't have banked registers. The offset is
54 - arm,routable-irqs : Total number of gic irq inputs which are not directly
55 connected from the peripherals, but are routed dynamically
56 by a crossbar/multiplexer preceding the GIC. The GIC irq
57 input line is assigned dynamically when the corresponding
58 peripheral's crossbar line is mapped.
61 intc: interrupt-controller@fff11000 {
62 compatible = "arm,cortex-a9-gic";
63 #interrupt-cells = <3>;
66 arm,routable-irqs = <160>;
67 reg = <0xfff11000 0x1000>,
72 * GIC virtualization extensions (VGIC)
74 For ARM cores that support the virtualization extensions, additional
75 properties must be described (they only exist if the GIC is the
76 primary interrupt controller).
80 - reg : Additional regions specifying the base physical address and
81 size of the VGIC registers. The first additional region is the GIC
82 virtual interface control register base and size. The 2nd additional
83 region is the GIC virtual cpu interface register base and size.
85 - interrupts : VGIC maintenance interrupt.
89 interrupt-controller@2c001000 {
90 compatible = "arm,cortex-a15-gic";
91 #interrupt-cells = <3>;
93 reg = <0x2c001000 0x1000>,
97 interrupts = <1 9 0xf04>;