1 Device Tree Clock bindings for arch-at91
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91sam9x5-sckc":
10 at91 SCKC (Slow Clock Controller)
11 This node contains the slow clock definitions.
13 "atmel,at91sam9x5-clk-slow-osc":
16 "atmel,at91sam9x5-clk-slow-rc-osc":
17 at91 internal slow RC oscillator
19 "atmel,at91rm9200-pmc" or
20 "atmel,at91sam9g45-pmc" or
21 "atmel,at91sam9n12-pmc" or
22 "atmel,at91sam9x5-pmc" or
24 at91 PMC (Power Management Controller)
25 All at91 specific clocks (clocks defined below) must be child
28 "atmel,at91sam9x5-clk-slow" (under sckc node)
30 "atmel,at91sam9260-clk-slow" (under pmc node):
33 "atmel,at91rm9200-clk-main-osc"
34 "atmel,at91sam9x5-clk-main-rc-osc"
37 "atmel,at91sam9x5-clk-main"
38 "atmel,at91rm9200-clk-main":
41 "atmel,at91rm9200-clk-master" or
42 "atmel,at91sam9x5-clk-master":
45 "atmel,at91sam9x5-clk-peripheral" or
46 "atmel,at91rm9200-clk-peripheral":
47 at91 peripheral clocks
49 "atmel,at91rm9200-clk-pll" or
50 "atmel,at91sam9g45-clk-pll" or
51 "atmel,at91sam9g20-clk-pllb" or
52 "atmel,sama5d3-clk-pll":
55 "atmel,at91sam9x5-clk-plldiv":
58 "atmel,at91rm9200-clk-programmable" or
59 "atmel,at91sam9g45-clk-programmable" or
60 "atmel,at91sam9x5-clk-programmable":
61 at91 programmable clocks
63 "atmel,at91sam9x5-clk-smd":
64 at91 SMD (Soft Modem) clock
66 "atmel,at91rm9200-clk-system":
69 "atmel,at91rm9200-clk-usb" or
70 "atmel,at91sam9x5-clk-usb" or
71 "atmel,at91sam9n12-clk-usb":
74 "atmel,at91sam9x5-clk-utmi":
77 "atmel,sama5d4-clk-h32mx":
80 "atmel,sama5d2-clk-generated":
83 Required properties for SCKC node:
84 - reg : defines the IO memory reserved for the SCKC.
85 - #size-cells : shall be 0 (reg is used to encode clk id).
86 - #address-cells : shall be 1 (reg is used to encode clk id).
91 compatible = "atmel,sama5d3-pmc";
92 reg = <0xfffffe50 0x4>
96 /* put at91 slow clocks here */
100 Required properties for internal slow RC oscillator:
101 - #clock-cells : from common clock binding; shall be set to 0.
102 - clock-frequency : define the internal RC oscillator frequency.
105 - clock-accuracy : define the internal RC oscillator accuracy.
108 slow_rc_osc: slow_rc_osc {
109 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
110 clock-frequency = <32768>;
111 clock-accuracy = <50000000>;
114 Required properties for slow oscillator:
115 - #clock-cells : from common clock binding; shall be set to 0.
116 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
119 - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
124 compatible = "atmel,at91rm9200-clk-slow-osc";
126 clocks = <&slow_xtal>;
129 Required properties for slow clock:
130 - #clock-cells : from common clock binding; shall be set to 0.
131 - clocks : shall encode the slow clk sources (see atmel datasheet).
135 compatible = "atmel,at91sam9x5-clk-slow";
137 clocks = <&slow_rc_osc &slow_osc>;
140 Required properties for PMC node:
141 - reg : defines the IO memory reserved for the PMC.
142 - #size-cells : shall be 0 (reg is used to encode clk id).
143 - #address-cells : shall be 1 (reg is used to encode clk id).
144 - interrupts : shall be set to PMC interrupt line.
145 - interrupt-controller : tell that the PMC is an interrupt controller.
146 - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
147 and reflect the bit position in the PMC_ER/DR/SR registers.
148 You can use the dt macros defined in dt-bindings/clock/at91.h.
149 0 (AT91_PMC_MOSCS) -> main oscillator ready
150 1 (AT91_PMC_LOCKA) -> PLL A ready
151 2 (AT91_PMC_LOCKB) -> PLL B ready
152 3 (AT91_PMC_MCKRDY) -> master clock ready
153 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
154 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
155 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
156 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
157 18 (AT91_PMC_CFDEV) -> clock failure detected
161 compatible = "atmel,sama5d3-pmc";
162 interrupts = <1 4 7>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
166 #address-cells = <1>;
168 /* put at91 clocks here */
171 Required properties for main clock internal RC oscillator:
172 - interrupt-parent : must reference the PMC node.
173 - interrupts : shall be set to "<0>".
174 - clock-frequency : define the internal RC oscillator frequency.
177 - clock-accuracy : define the internal RC oscillator accuracy.
180 main_rc_osc: main_rc_osc {
181 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
182 interrupt-parent = <&pmc>;
184 clock-frequency = <12000000>;
185 clock-accuracy = <50000000>;
188 Required properties for main clock oscillator:
189 - interrupt-parent : must reference the PMC node.
190 - interrupts : shall be set to "<0>".
191 - #clock-cells : from common clock binding; shall be set to 0.
192 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
195 - atmel,osc-bypass : boolean property. Specified if a clock signal is provided
198 clock signal is directly provided on XIN pin.
202 compatible = "atmel,at91rm9200-clk-main-osc";
203 interrupt-parent = <&pmc>;
206 clocks = <&main_xtal>;
209 Required properties for main clock:
210 - interrupt-parent : must reference the PMC node.
211 - interrupts : shall be set to "<0>".
212 - #clock-cells : from common clock binding; shall be set to 0.
213 - clocks : shall encode the main clk sources (see atmel datasheet).
217 compatible = "atmel,at91sam9x5-clk-main";
218 interrupt-parent = <&pmc>;
221 clocks = <&main_rc_osc &main_osc>;
224 Required properties for master clock:
225 - interrupt-parent : must reference the PMC node.
226 - interrupts : shall be set to "<3>".
227 - #clock-cells : from common clock binding; shall be set to 0.
228 - clocks : shall be the master clock sources (see atmel datasheet) phandles.
229 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
230 - atmel,clk-output-range : minimum and maximum clock frequency (two u32
232 e.g. output = <0 133000000>; <=> 0 to 133MHz.
233 - atmel,clk-divisors : master clock divisors table (four u32 fields).
234 0 <=> reserved value.
235 e.g. divisors = <1 2 4 6>;
236 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
237 PRES field as CLOCK_DIV3 (e.g sam9x5).
241 compatible = "atmel,at91rm9200-clk-master";
242 interrupt-parent = <&pmc>;
245 atmel,clk-output-range = <0 133000000>;
246 atmel,clk-divisors = <1 2 4 0>;
249 Required properties for peripheral clocks:
250 - #size-cells : shall be 0 (reg is used to encode clk id).
251 - #address-cells : shall be 1 (reg is used to encode clk id).
252 - clocks : shall be the master clock phandle.
253 e.g. clocks = <&mck>;
254 - name: device tree node describing a specific peripheral clock.
255 * #clock-cells : from common clock binding; shall be set to 0.
256 * reg: peripheral id. See Atmel's datasheets to get a full
257 list of peripheral ids.
258 * atmel,clk-output-range : minimum and maximum clock frequency
259 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
264 compatible = "atmel,at91sam9x5-clk-peripheral";
266 #address-cells = <1>;
272 atmel,clk-output-range = <0 133000000>;
278 atmel,clk-output-range = <0 66000000>;
283 Required properties for pll clocks:
284 - interrupt-parent : must reference the PMC node.
285 - interrupts : shall be set to "<1>".
286 - #clock-cells : from common clock binding; shall be set to 0.
287 - clocks : shall be the main clock phandle.
291 - atmel,clk-input-range : minimum and maximum source clock frequency (two u32
293 e.g. input = <1 32000000>; <=> 1 to 32MHz.
294 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
295 range description. Sould be set to 2, 3
297 * 1st and 2nd cells represent the frequency range (min-max).
298 * 3rd cell is optional and represents the OUT field value for the given
300 * 4th cell is optional and represents the ICPLL field (PLLICPR
302 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
303 depending on #atmel,pll-output-range-cells
308 compatible = "atmel,at91sam9g45-clk-pll";
309 interrupt-parent = <&pmc>;
314 atmel,clk-input-range = <2000000 32000000>;
315 #atmel,pll-clk-output-range-cells = <4>;
316 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
317 69500000 750000000 1 0
318 64500000 700000000 2 0
319 59500000 650000000 3 0
320 54500000 600000000 0 1
321 49500000 550000000 1 1
322 44500000 500000000 2 1
323 40000000 450000000 3 1>;
326 Required properties for plldiv clocks (plldiv = pll / 2):
327 - #clock-cells : from common clock binding; shall be set to 0.
328 - clocks : shall be the plla clock phandle.
330 The pll divisor is equal to 2 and cannot be changed.
334 compatible = "atmel,at91sam9x5-clk-plldiv";
339 Required properties for programmable clocks:
340 - interrupt-parent : must reference the PMC node.
341 - #size-cells : shall be 0 (reg is used to encode clk id).
342 - #address-cells : shall be 1 (reg is used to encode clk id).
343 - clocks : shall be the programmable clock source phandles.
344 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
345 - name: device tree node describing a specific prog clock.
346 * #clock-cells : from common clock binding; shall be set to 0.
347 * reg : programmable clock id (register offset from PCKx
349 * interrupts : shall be set to "<(8 + id)>".
353 compatible = "atmel,at91sam9g45-clk-programmable";
355 #address-cells = <1>;
356 interrupt-parent = <&pmc>;
357 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
373 Required properties for smd clock:
374 - #clock-cells : from common clock binding; shall be set to 0.
375 - clocks : shall be the smd clock source phandles.
376 e.g. clocks = <&plladiv>, <&utmi>;
380 compatible = "atmel,at91sam9x5-clk-smd";
382 clocks = <&plladiv>, <&utmi>;
385 Required properties for system clocks:
386 - #size-cells : shall be 0 (reg is used to encode clk id).
387 - #address-cells : shall be 1 (reg is used to encode clk id).
388 - name: device tree node describing a specific system clock.
389 * #clock-cells : from common clock binding; shall be set to 0.
390 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
391 See Atmel's datasheet to get a full list of system clock ids.
395 compatible = "atmel,at91rm9200-clk-system";
396 #address-cells = <1>;
419 Required properties for usb clock:
420 - #clock-cells : from common clock binding; shall be set to 0.
421 - clocks : shall be the smd clock source phandles.
422 e.g. clocks = <&pllb>;
423 - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
424 usb clock divisor table.
425 e.g. divisors = <1 2 4 0>;
429 compatible = "atmel,at91sam9x5-clk-usb";
431 clocks = <&plladiv>, <&utmi>;
435 compatible = "atmel,at91rm9200-clk-usb";
438 atmel,clk-divisors = <1 2 4 0>;
442 Required properties for utmi clock:
443 - interrupt-parent : must reference the PMC node.
444 - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
445 - #clock-cells : from common clock binding; shall be set to 0.
446 - clocks : shall be the main clock source phandle.
450 compatible = "atmel,at91sam9x5-clk-utmi";
451 interrupt-parent = <&pmc>;
452 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
457 Required properties for 32 bits bus Matrix clock (h32mx clock):
458 - #clock-cells : from common clock binding; shall be set to 0.
459 - clocks : shall be the master clock source phandle.
464 compatible = "atmel,sama5d4-clk-h32mx";
468 Required properties for generated clocks:
469 - #size-cells : shall be 0 (reg is used to encode clk id).
470 - #address-cells : shall be 1 (reg is used to encode clk id).
471 - clocks : shall be the generated clock source phandles.
472 e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
473 - name: device tree node describing a specific generated clock.
474 * #clock-cells : from common clock binding; shall be set to 0.
475 * reg: peripheral id. See Atmel's datasheets to get a full
476 list of peripheral ids.
477 * atmel,clk-output-range : minimum and maximum clock frequency
482 compatible = "atmel,sama5d2-clk-generated";
483 #address-cells = <1>;
485 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
487 tcb0_gclk: tcb0_gclk {
490 atmel,clk-output-range = <0 83000000>;
496 atmel,clk-output-range = <0 83000000>;