1 Device Tree Clock bindings for arch-at91
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91sam9x5-sckc":
10 at91 SCKC (Slow Clock Controller)
11 This node contains the slow clock definitions.
13 "atmel,at91sam9x5-clk-slow-osc":
16 "atmel,at91sam9x5-clk-slow-rc-osc":
17 at91 internal slow RC oscillator
19 "atmel,at91rm9200-pmc" or
20 "atmel,at91sam9g45-pmc" or
21 "atmel,at91sam9n12-pmc" or
22 "atmel,at91sam9x5-pmc" or
24 at91 PMC (Power Management Controller)
25 All at91 specific clocks (clocks defined below) must be child
28 "atmel,at91sam9x5-clk-slow" (under sckc node)
30 "atmel,at91sam9260-clk-slow" (under pmc node):
33 "atmel,at91rm9200-clk-main-osc"
34 "atmel,at91sam9x5-clk-main-rc-osc"
37 "atmel,at91sam9x5-clk-main"
38 "atmel,at91rm9200-clk-main":
41 "atmel,at91rm9200-clk-master" or
42 "atmel,at91sam9x5-clk-master":
45 "atmel,at91sam9x5-clk-peripheral" or
46 "atmel,at91rm9200-clk-peripheral":
47 at91 peripheral clocks
49 "atmel,at91rm9200-clk-pll" or
50 "atmel,at91sam9g45-clk-pll" or
51 "atmel,at91sam9g20-clk-pllb" or
52 "atmel,sama5d3-clk-pll":
55 "atmel,at91sam9x5-clk-plldiv":
58 "atmel,at91rm9200-clk-programmable" or
59 "atmel,at91sam9g45-clk-programmable" or
60 "atmel,at91sam9x5-clk-programmable":
61 at91 programmable clocks
63 "atmel,at91sam9x5-clk-smd":
64 at91 SMD (Soft Modem) clock
66 "atmel,at91rm9200-clk-system":
69 "atmel,at91rm9200-clk-usb" or
70 "atmel,at91sam9x5-clk-usb" or
71 "atmel,at91sam9n12-clk-usb":
74 "atmel,at91sam9x5-clk-utmi":
77 Required properties for SCKC node:
78 - reg : defines the IO memory reserved for the SCKC.
79 - #size-cells : shall be 0 (reg is used to encode clk id).
80 - #address-cells : shall be 1 (reg is used to encode clk id).
85 compatible = "atmel,sama5d3-pmc";
86 reg = <0xfffffe50 0x4>
90 /* put at91 slow clocks here */
94 Required properties for internal slow RC oscillator:
95 - #clock-cells : from common clock binding; shall be set to 0.
96 - clock-frequency : define the internal RC oscillator frequency.
99 - clock-accuracy : define the internal RC oscillator accuracy.
102 slow_rc_osc: slow_rc_osc {
103 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
104 clock-frequency = <32768>;
105 clock-accuracy = <50000000>;
108 Required properties for slow oscillator:
109 - #clock-cells : from common clock binding; shall be set to 0.
110 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
113 - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
118 compatible = "atmel,at91rm9200-clk-slow-osc";
120 clocks = <&slow_xtal>;
123 Required properties for slow clock:
124 - #clock-cells : from common clock binding; shall be set to 0.
125 - clocks : shall encode the slow clk sources (see atmel datasheet).
129 compatible = "atmel,at91sam9x5-clk-slow";
131 clocks = <&slow_rc_osc &slow_osc>;
134 Required properties for PMC node:
135 - reg : defines the IO memory reserved for the PMC.
136 - #size-cells : shall be 0 (reg is used to encode clk id).
137 - #address-cells : shall be 1 (reg is used to encode clk id).
138 - interrupts : shall be set to PMC interrupt line.
139 - interrupt-controller : tell that the PMC is an interrupt controller.
140 - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
141 and reflect the bit position in the PMC_ER/DR/SR registers.
142 You can use the dt macros defined in dt-bindings/clock/at91.h.
143 0 (AT91_PMC_MOSCS) -> main oscillator ready
144 1 (AT91_PMC_LOCKA) -> PLL A ready
145 2 (AT91_PMC_LOCKB) -> PLL B ready
146 3 (AT91_PMC_MCKRDY) -> master clock ready
147 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
148 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
149 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
150 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
151 18 (AT91_PMC_CFDEV) -> clock failure detected
155 compatible = "atmel,sama5d3-pmc";
156 interrupts = <1 4 7>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
160 #address-cells = <1>;
162 /* put at91 clocks here */
165 Required properties for main clock internal RC oscillator:
166 - interrupt-parent : must reference the PMC node.
167 - interrupts : shall be set to "<0>".
168 - clock-frequency : define the internal RC oscillator frequency.
171 - clock-accuracy : define the internal RC oscillator accuracy.
174 main_rc_osc: main_rc_osc {
175 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
176 interrupt-parent = <&pmc>;
178 clock-frequency = <12000000>;
179 clock-accuracy = <50000000>;
182 Required properties for main clock oscillator:
183 - interrupt-parent : must reference the PMC node.
184 - interrupts : shall be set to "<0>".
185 - #clock-cells : from common clock binding; shall be set to 0.
186 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
189 - atmel,osc-bypass : boolean property. Specified if a clock signal is provided
192 clock signal is directly provided on XIN pin.
196 compatible = "atmel,at91rm9200-clk-main-osc";
197 interrupt-parent = <&pmc>;
200 clocks = <&main_xtal>;
203 Required properties for main clock:
204 - interrupt-parent : must reference the PMC node.
205 - interrupts : shall be set to "<0>".
206 - #clock-cells : from common clock binding; shall be set to 0.
207 - clocks : shall encode the main clk sources (see atmel datasheet).
211 compatible = "atmel,at91sam9x5-clk-main";
212 interrupt-parent = <&pmc>;
215 clocks = <&main_rc_osc &main_osc>;
218 Required properties for master clock:
219 - interrupt-parent : must reference the PMC node.
220 - interrupts : shall be set to "<3>".
221 - #clock-cells : from common clock binding; shall be set to 0.
222 - clocks : shall be the master clock sources (see atmel datasheet) phandles.
223 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
224 - atmel,clk-output-range : minimum and maximum clock frequency (two u32
226 e.g. output = <0 133000000>; <=> 0 to 133MHz.
227 - atmel,clk-divisors : master clock divisors table (four u32 fields).
228 0 <=> reserved value.
229 e.g. divisors = <1 2 4 6>;
230 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
231 PRES field as CLOCK_DIV3 (e.g sam9x5).
235 compatible = "atmel,at91rm9200-clk-master";
236 interrupt-parent = <&pmc>;
239 atmel,clk-output-range = <0 133000000>;
240 atmel,clk-divisors = <1 2 4 0>;
243 Required properties for peripheral clocks:
244 - #size-cells : shall be 0 (reg is used to encode clk id).
245 - #address-cells : shall be 1 (reg is used to encode clk id).
246 - clocks : shall be the master clock phandle.
247 e.g. clocks = <&mck>;
248 - name: device tree node describing a specific system clock.
249 * #clock-cells : from common clock binding; shall be set to 0.
250 * reg: peripheral id. See Atmel's datasheets to get a full
251 list of peripheral ids.
252 * atmel,clk-output-range : minimum and maximum clock frequency
253 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
258 compatible = "atmel,at91sam9x5-clk-peripheral";
260 #address-cells = <1>;
266 atmel,clk-output-range = <0 133000000>;
272 atmel,clk-output-range = <0 66000000>;
277 Required properties for pll clocks:
278 - interrupt-parent : must reference the PMC node.
279 - interrupts : shall be set to "<1>".
280 - #clock-cells : from common clock binding; shall be set to 0.
281 - clocks : shall be the main clock phandle.
285 - atmel,clk-input-range : minimum and maximum source clock frequency (two u32
287 e.g. input = <1 32000000>; <=> 1 to 32MHz.
288 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
289 range description. Sould be set to 2, 3
291 * 1st and 2nd cells represent the frequency range (min-max).
292 * 3rd cell is optional and represents the OUT field value for the given
294 * 4th cell is optional and represents the ICPLL field (PLLICPR
296 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
297 depending on #atmel,pll-output-range-cells
302 compatible = "atmel,at91sam9g45-clk-pll";
303 interrupt-parent = <&pmc>;
308 atmel,clk-input-range = <2000000 32000000>;
309 #atmel,pll-clk-output-range-cells = <4>;
310 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
311 69500000 750000000 1 0
312 64500000 700000000 2 0
313 59500000 650000000 3 0
314 54500000 600000000 0 1
315 49500000 550000000 1 1
316 44500000 500000000 2 1
317 40000000 450000000 3 1>;
320 Required properties for plldiv clocks (plldiv = pll / 2):
321 - #clock-cells : from common clock binding; shall be set to 0.
322 - clocks : shall be the plla clock phandle.
324 The pll divisor is equal to 2 and cannot be changed.
328 compatible = "atmel,at91sam9x5-clk-plldiv";
333 Required properties for programmable clocks:
334 - interrupt-parent : must reference the PMC node.
335 - #size-cells : shall be 0 (reg is used to encode clk id).
336 - #address-cells : shall be 1 (reg is used to encode clk id).
337 - clocks : shall be the programmable clock source phandles.
338 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
339 - name: device tree node describing a specific prog clock.
340 * #clock-cells : from common clock binding; shall be set to 0.
341 * reg : programmable clock id (register offset from PCKx
343 * interrupts : shall be set to "<(8 + id)>".
347 compatible = "atmel,at91sam9g45-clk-programmable";
349 #address-cells = <1>;
350 interrupt-parent = <&pmc>;
351 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
367 Required properties for smd clock:
368 - #clock-cells : from common clock binding; shall be set to 0.
369 - clocks : shall be the smd clock source phandles.
370 e.g. clocks = <&plladiv>, <&utmi>;
374 compatible = "atmel,at91sam9x5-clk-smd";
376 clocks = <&plladiv>, <&utmi>;
379 Required properties for system clocks:
380 - #size-cells : shall be 0 (reg is used to encode clk id).
381 - #address-cells : shall be 1 (reg is used to encode clk id).
382 - name: device tree node describing a specific system clock.
383 * #clock-cells : from common clock binding; shall be set to 0.
384 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
385 See Atmel's datasheet to get a full list of system clock ids.
389 compatible = "atmel,at91rm9200-clk-system";
390 #address-cells = <1>;
413 Required properties for usb clock:
414 - #clock-cells : from common clock binding; shall be set to 0.
415 - clocks : shall be the smd clock source phandles.
416 e.g. clocks = <&pllb>;
417 - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
418 usb clock divisor table.
419 e.g. divisors = <1 2 4 0>;
423 compatible = "atmel,at91sam9x5-clk-usb";
425 clocks = <&plladiv>, <&utmi>;
429 compatible = "atmel,at91rm9200-clk-usb";
432 atmel,clk-divisors = <1 2 4 0>;
436 Required properties for utmi clock:
437 - interrupt-parent : must reference the PMC node.
438 - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
439 - #clock-cells : from common clock binding; shall be set to 0.
440 - clocks : shall be the main clock source phandle.
444 compatible = "atmel,at91sam9x5-clk-utmi";
445 interrupt-parent = <&pmc>;
446 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;