1 * Clock Block on Freescale CoreNet Platforms
3 Freescale CoreNet chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
6 which can then be passed to a variety of internal logic, including
7 cores and peripheral IP blocks.
8 Please refer to the Reference Manual for details.
10 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11 which the chip complies.
13 Chassis Version Example Chips
14 --------------- -------------
15 1.0 p4080, p5020, p5040
16 2.0 t4240, b4860, t1040
18 1. Clock Block Binding
21 - compatible: Should contain a specific clock block compatible string
22 and a single chassis clock compatible string.
23 Clock block strings include, but not limited to, one of the:
24 * "fsl,p2041-clockgen"
25 * "fsl,p3041-clockgen"
26 * "fsl,p4080-clockgen"
27 * "fsl,p5020-clockgen"
28 * "fsl,p5040-clockgen"
29 * "fsl,t4240-clockgen"
30 * "fsl,b4420-clockgen"
31 * "fsl,b4860-clockgen"
32 Chassis clock strings include:
33 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
34 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
35 - reg: Describes the address of the device's resources within the
36 address space defined by its parent bus, and resource zero
37 represents the clock register set
38 - clock-frequency: Input system clock frequency
40 Recommended properties:
41 - ranges: Allows valid translation between child's address space and
42 parent's. Must be present if the device has sub-nodes.
43 - #address-cells: Specifies the number of cells used to represent
44 physical base addresses. Must be present if the device has
45 sub-nodes and set to 1 if present
46 - #size-cells: Specifies the number of cells used to represent
47 the size of an address. Must be present if the device has
48 sub-nodes and set to 1 if present
50 2. Clock Provider/Consumer Binding
52 Most of the bindings are from the common clock binding[1].
53 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
56 - compatible : Should include one of the following:
57 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
58 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
59 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
60 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
61 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
62 It takes parent's clock-frequency as its clock.
63 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
64 It takes parent's clock-frequency as its clock.
65 - #clock-cells: From common clock binding. The number of cells in a
66 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
67 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
68 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
69 clock-specifier cell may take the following values:
70 * 0 - equal to the PLL frequency
71 * 1 - equal to the PLL frequency divided by 2
72 * 2 - equal to the PLL frequency divided by 4
74 Recommended properties:
75 - clocks: Should be the phandle of input parent clock
76 - clock-names: From common clock binding, indicates the clock name
77 - clock-output-names: From common clock binding, indicates the names of
79 - reg: Should be the offset and length of clock block base address.
80 The length should be 4.
82 Example for clock block and clock provider:
84 clockgen: global-utilities@e1000 {
85 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
86 ranges = <0x0 0xe1000 0x1000>;
87 clock-frequency = <133333333>;
88 reg = <0xe1000 0x1000>;
94 compatible = "fsl,qoriq-sysclk-1.0";
95 clock-output-names = "sysclk";
101 compatible = "fsl,qoriq-core-pll-1.0";
103 clock-output-names = "pll0", "pll0-div2";
109 compatible = "fsl,qoriq-core-pll-1.0";
111 clock-output-names = "pll1", "pll1-div2";
117 compatible = "fsl,qoriq-core-mux-1.0";
118 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
119 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
120 clock-output-names = "cmux0";
126 compatible = "fsl,qoriq-core-mux-1.0";
127 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
128 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
129 clock-output-names = "cmux1";
134 Example for clock consumer:
137 cpu0: PowerPC,e5500@0 {