1 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
4 - compatible : Should be one of
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
11 The -to variants should be preferred since they allow to determine the
12 correct ROM script addresses needed for the driver to work without additional
14 - reg : Should contain SDMA registers location and length
15 - interrupts : Should contain SDMA interrupt
16 - #dma-cells : Must be <3>.
17 The first cell specifies the DMA request/event ID. See details below
18 about the second and third cell.
19 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
22 The second cell of dma phandle specifies the peripheral type of DMA transfer.
23 The full ID of peripheral types can be found below.
39 12 External peripheral
40 13 Memory Stick Host Controller
41 14 Shared Memory Stick Host Controller
49 22 SSI Dual FIFO (needs firmware ver >= 2)
53 The third cell specifies the transfer priority as below.
56 -------------------------
63 - gpr : The phandle to the General Purpose Register (GPR) node.
64 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
66 reg is the GPR register offset.
67 shift is the bit position inside the GPR register.
68 val is the value of the bit (0 or 1).
73 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
74 reg = <0x83fb0000 0x4000>;
77 fsl,sdma-ram-script-name = "sdma-imx51.bin";
80 DMA clients connected to the i.MX SDMA controller must use the format
81 described in the dma.txt file.
86 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
87 reg = <0x70014000 0x4000>;
90 dmas = <&sdma 24 1 0>,
92 dma-names = "rx", "tx";
93 fsl,fifo-depth = <15>;
96 Using the fsl,sdma-event-remap property:
98 If we want to use SDMA on the SAI1 port on a MX6SX:
102 /* SDMA events remap for SAI1_RX and SAI1_TX */
103 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
106 The fsl,sdma-event-remap property in this case has two values:
107 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
108 SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
109 Setting bit 15 to 1 selects SAI1_RX.
110 - <0 16 1> means that the offset is 0, so GPR0 is the register of the
111 SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
112 Setting bit 16 to 1 selects SAI1_TX.