1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
5 platforms. It can be found on BCM7xxx products starting with BCM7120.
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
14 controller, in particular for UARTs
16 - not all 32-bits within the interrupt controller actually map to an interrupt
18 The typical hardware layout for this controller is represented below:
20 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
22 0 -----[ MUX ] ------------|==========> GIC interrupt 75
25 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
28 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
31 3 ---------------------|
32 4 ---------------------|
33 5 ---------------------|
34 7 ---------------------|---|===========> GIC interrupt 66
35 9 ---------------------|
36 10 --------------------|
37 11 --------------------/
39 6 ------------------------\
40 |===========> GIC interrupt 64
41 8 ------------------------/
43 12 ........................ X
44 13 ........................ X (not connected)
46 31 ........................ X
50 - compatible: should be "brcm,bcm7120-l2-intc"
51 - reg: specifies the base physical address and size of the registers
52 - interrupt-controller: identifies the node as an interrupt controller
53 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
55 - interrupt-parent: specifies the phandle to the parent interrupt controller
56 this one is cascaded from
57 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
58 node, valid values depend on the type of parent interrupt controller
59 - brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
60 are wired to this 2nd level interrupt controller, and how they match their
61 respective interrupt parents. Should match exactly the number of interrupts
62 specified in the 'interrupts' property.
66 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
67 wakeup source for system suspend/resume.
69 - brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
70 interrupts which have a mux gate, typically UARTs. Setting these bits will
71 make their respective interrupts outputs bypass this 2nd level interrupt
72 controller completely, it completely transparent for the interrupt controller
77 irq0_intc: interrupt-controller@f0406800 {
78 compatible = "brcm,bcm7120-l2-intc";
79 interrupt-parent = <&intc>;
80 #interrupt-cells = <1>;
81 reg = <0xf0406800 0x8>;
83 interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
84 brcm,int-map-mask = <0xeb8>, <0x140>;
85 brcm,int-fwd-mask = <0x7>;