3 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4 running counter, and 5 watchdog modules. The first two channels may also
5 trigger a legacy watchdog reset.
9 - compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
10 - reg : Specifies base physical address and size of the registers.
11 - interrupts : A list of 6 interrupts; one per each of timer channels 1
12 through 5, and one for the shared interrupt for the remaining channels.
13 - clocks : Must contain one entry, for the module clock.
14 See ../clocks/clock-bindings.txt for details.
17 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
18 reg = <0x60005000 0x400>;
19 interrupts = <0 0 0x04
25 clocks = <&tegra_car 214>;