4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
14 #include <linux/sched.h>
15 #include <linux/cache.h>
16 #include <linux/mmu_context.h>
17 #include <linux/syscalls.h>
18 #include <linux/uaccess.h>
19 #include <linux/pagemap.h>
20 #include <asm/cacheflush.h>
21 #include <asm/cachectl.h>
22 #include <asm/setup.h>
24 static int l2_line_sz;
25 static int ioc_exists;
26 int slc_enable = 1, ioc_enable = 1;
27 unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
28 unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
30 void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
31 unsigned long sz, const int cacheop);
33 void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
34 void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
35 void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz);
37 char *arc_cache_mumbojumbo(int c, char *buf, int len)
40 struct cpuinfo_arc_cache *p;
42 #define PR_CACHE(p, cfg, str) \
44 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
46 n += scnprintf(buf + n, len - n, \
47 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \
48 (p)->sz_k, (p)->assoc, (p)->line_len, \
49 (p)->vipt ? "VIPT" : "PIPT", \
50 (p)->alias ? " aliasing" : "", \
53 PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");
54 PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
59 p = &cpuinfo_arc700[c].slc;
61 n += scnprintf(buf + n, len - n,
62 "SLC\t\t: %uK, %uB Line%s\n",
63 p->sz_k, p->line_len, IS_USED_RUN(slc_enable));
66 n += scnprintf(buf + n, len - n, "IOC\t\t:%s\n",
67 IS_DISABLED_RUN(ioc_enable));
73 * Read the Cache Build Confuration Registers, Decode them and save into
74 * the cpuinfo structure for later use.
75 * No Validation done here, simply read/convert the BCRs
77 static void read_decode_cache_bcr_arcv2(int cpu)
79 struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
80 struct bcr_generic sbcr;
83 #ifdef CONFIG_CPU_BIG_ENDIAN
84 unsigned int pad:24, way:2, lsz:2, sz:4;
86 unsigned int sz:4, lsz:2, way:2, pad:24;
90 struct bcr_clust_cfg {
91 #ifdef CONFIG_CPU_BIG_ENDIAN
92 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
94 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
99 #ifdef CONFIG_CPU_BIG_ENDIAN
100 unsigned int start:4, limit:4, pad:22, order:1, disable:1;
102 unsigned int disable:1, order:1, pad:22, limit:4, start:4;
107 READ_BCR(ARC_REG_SLC_BCR, sbcr);
109 READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
110 p_slc->ver = sbcr.ver;
111 p_slc->sz_k = 128 << slc_cfg.sz;
112 l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;
115 READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);
121 /* HS 2.0 didn't have AUX_VOL */
122 if (cpuinfo_arc700[cpu].core.family > 0x51) {
123 READ_BCR(AUX_VOL, vol);
124 perip_base = vol.start << 28;
125 /* HS 3.0 has limit and strict-ordering fields */
126 if (cpuinfo_arc700[cpu].core.family > 0x52)
127 perip_end = (vol.limit << 28) - 1;
131 void read_decode_cache_bcr(void)
133 struct cpuinfo_arc_cache *p_ic, *p_dc;
134 unsigned int cpu = smp_processor_id();
136 #ifdef CONFIG_CPU_BIG_ENDIAN
137 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
139 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
143 p_ic = &cpuinfo_arc700[cpu].icache;
144 READ_BCR(ARC_REG_IC_BCR, ibcr);
150 BUG_ON(ibcr.config != 3);
151 p_ic->assoc = 2; /* Fixed to 2w set assoc */
152 } else if (ibcr.ver >= 4) {
153 p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */
156 p_ic->line_len = 8 << ibcr.line_len;
157 p_ic->sz_k = 1 << (ibcr.sz - 1);
158 p_ic->ver = ibcr.ver;
160 p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;
163 p_dc = &cpuinfo_arc700[cpu].dcache;
164 READ_BCR(ARC_REG_DC_BCR, dbcr);
170 BUG_ON(dbcr.config != 2);
171 p_dc->assoc = 4; /* Fixed to 4w set assoc */
173 p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1;
174 } else if (dbcr.ver >= 4) {
175 p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */
177 p_dc->alias = 0; /* PIPT so can't VIPT alias */
180 p_dc->line_len = 16 << dbcr.line_len;
181 p_dc->sz_k = 1 << (dbcr.sz - 1);
182 p_dc->ver = dbcr.ver;
186 read_decode_cache_bcr_arcv2(cpu);
190 * Line Operation on {I,D}-Cache
195 #define OP_FLUSH_N_INV 0x3
196 #define OP_INV_IC 0x4
199 * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
201 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
202 * The orig Cache Management Module "CDU" only required paddr to invalidate a
203 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
204 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
205 * the exact same line.
207 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
208 * paddr alone could not be used to correctly index the cache.
211 * MMU v1/v2 (Fixed Page Size 8k)
213 * The solution was to provide CDU with these additonal vaddr bits. These
214 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
215 * standard page size of 8k.
216 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
217 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
218 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
219 * represent the offset within cache-line. The adv of using this "clumsy"
220 * interface for additional info was no new reg was needed in CDU programming
223 * 17:13 represented the max num of bits passable, actual bits needed were
224 * fewer, based on the num-of-aliases possible.
225 * -for 2 alias possibility, only bit 13 needed (32K cache)
226 * -for 4 alias possibility, bits 14:13 needed (64K cache)
231 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
232 * only support 8k (default), 16k and 4k.
233 * However from hardware perspective, smaller page sizes aggravate aliasing
234 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
235 * the existing scheme of piggybacking won't work for certain configurations.
236 * Two new registers IC_PTAG and DC_PTAG inttoduced.
237 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
241 void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
242 unsigned long sz, const int op)
244 unsigned int aux_cmd;
246 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
248 if (op == OP_INV_IC) {
249 aux_cmd = ARC_REG_IC_IVIL;
251 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
252 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
255 /* Ensure we properly floor/ceil the non-line aligned/sized requests
256 * and have @paddr - aligned to cache line and integral @num_lines.
257 * This however can be avoided for page sized since:
258 * -@paddr will be cache-line aligned already (being page aligned)
259 * -@sz will be integral multiple of line size (being page sized).
262 sz += paddr & ~CACHE_LINE_MASK;
263 paddr &= CACHE_LINE_MASK;
264 vaddr &= CACHE_LINE_MASK;
267 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
269 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
270 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
272 while (num_lines-- > 0) {
273 write_aux_reg(aux_cmd, paddr);
274 paddr += L1_CACHE_BYTES;
279 * For ARC700 MMUv3 I-cache and D-cache flushes
280 * Also reused for HS38 aliasing I-cache configuration
283 void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
284 unsigned long sz, const int op)
286 unsigned int aux_cmd, aux_tag;
288 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
290 if (op == OP_INV_IC) {
291 aux_cmd = ARC_REG_IC_IVIL;
292 aux_tag = ARC_REG_IC_PTAG;
294 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
295 aux_tag = ARC_REG_DC_PTAG;
298 /* Ensure we properly floor/ceil the non-line aligned/sized requests
299 * and have @paddr - aligned to cache line and integral @num_lines.
300 * This however can be avoided for page sized since:
301 * -@paddr will be cache-line aligned already (being page aligned)
302 * -@sz will be integral multiple of line size (being page sized).
305 sz += paddr & ~CACHE_LINE_MASK;
306 paddr &= CACHE_LINE_MASK;
307 vaddr &= CACHE_LINE_MASK;
309 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
312 * MMUv3, cache ops require paddr in PTAG reg
313 * if V-P const for loop, PTAG can be written once outside loop
316 write_aux_reg(aux_tag, paddr);
319 * This is technically for MMU v4, using the MMU v3 programming model
320 * Special work for HS38 aliasing I-cache configuration with PAE40
321 * - upper 8 bits of paddr need to be written into PTAG_HI
322 * - (and needs to be written before the lower 32 bits)
323 * Note that PTAG_HI is hoisted outside the line loop
325 if (is_pae40_enabled() && op == OP_INV_IC)
326 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
328 while (num_lines-- > 0) {
330 write_aux_reg(aux_tag, paddr);
331 paddr += L1_CACHE_BYTES;
334 write_aux_reg(aux_cmd, vaddr);
335 vaddr += L1_CACHE_BYTES;
340 * In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
341 * Here's how cache ops are implemented
343 * - D-cache: only paddr needed (in DC_IVDL/DC_FLDL)
344 * - I-cache Non Aliasing: Despite VIPT, only paddr needed (in IC_IVIL)
345 * - I-cache Aliasing: Both vaddr and paddr needed (in IC_IVIL, IC_PTAG
346 * respectively, similar to MMU v3 programming model, hence
347 * __cache_line_loop_v3() is used)
349 * If PAE40 is enabled, independent of aliasing considerations, the higher bits
350 * needs to be written into PTAG_HI
353 void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
354 unsigned long sz, const int cacheop)
356 unsigned int aux_cmd;
358 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
360 if (cacheop == OP_INV_IC) {
361 aux_cmd = ARC_REG_IC_IVIL;
363 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
364 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
367 /* Ensure we properly floor/ceil the non-line aligned/sized requests
368 * and have @paddr - aligned to cache line and integral @num_lines.
369 * This however can be avoided for page sized since:
370 * -@paddr will be cache-line aligned already (being page aligned)
371 * -@sz will be integral multiple of line size (being page sized).
374 sz += paddr & ~CACHE_LINE_MASK;
375 paddr &= CACHE_LINE_MASK;
378 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
381 * For HS38 PAE40 configuration
382 * - upper 8 bits of paddr need to be written into PTAG_HI
383 * - (and needs to be written before the lower 32 bits)
385 if (is_pae40_enabled()) {
386 if (cacheop == OP_INV_IC)
388 * Non aliasing I-cache in HS38,
389 * aliasing I-cache handled in __cache_line_loop_v3()
391 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
393 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
396 while (num_lines-- > 0) {
397 write_aux_reg(aux_cmd, paddr);
398 paddr += L1_CACHE_BYTES;
402 #if (CONFIG_ARC_MMU_VER < 3)
403 #define __cache_line_loop __cache_line_loop_v2
404 #elif (CONFIG_ARC_MMU_VER == 3)
405 #define __cache_line_loop __cache_line_loop_v3
406 #elif (CONFIG_ARC_MMU_VER > 3)
407 #define __cache_line_loop __cache_line_loop_v4
410 #ifdef CONFIG_ARC_HAS_DCACHE
412 /***************************************************************
413 * Machine specific helpers for Entire D-Cache or Per Line ops
416 static inline void __before_dc_op(const int op)
418 if (op == OP_FLUSH_N_INV) {
419 /* Dcache provides 2 cmd: FLUSH or INV
420 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
421 * flush-n-inv is achieved by INV cmd but with IM=1
422 * So toggle INV sub-mode depending on op request and default
424 const unsigned int ctl = ARC_REG_DC_CTRL;
425 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
429 static inline void __after_dc_op(const int op)
432 const unsigned int ctl = ARC_REG_DC_CTRL;
435 /* flush / flush-n-inv both wait */
436 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)
439 /* Switch back to default Invalidate mode */
440 if (op == OP_FLUSH_N_INV)
441 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
446 * Operation on Entire D-Cache
447 * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
448 * Note that constant propagation ensures all the checks are gone
451 static inline void __dc_entire_op(const int op)
457 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
458 aux = ARC_REG_DC_IVDC;
460 aux = ARC_REG_DC_FLSH;
462 write_aux_reg(aux, 0x1);
467 /* For kernel mappings cache operation: index is same as paddr */
468 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
471 * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback)
473 static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
474 unsigned long sz, const int op)
478 local_irq_save(flags);
482 __cache_line_loop(paddr, vaddr, sz, op);
486 local_irq_restore(flags);
491 #define __dc_entire_op(op)
492 #define __dc_line_op(paddr, vaddr, sz, op)
493 #define __dc_line_op_k(paddr, sz, op)
495 #endif /* CONFIG_ARC_HAS_DCACHE */
497 #ifdef CONFIG_ARC_HAS_ICACHE
499 static inline void __ic_entire_inv(void)
501 write_aux_reg(ARC_REG_IC_IVIC, 1);
502 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
506 __ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr,
511 local_irq_save(flags);
512 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
513 local_irq_restore(flags);
518 #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s)
523 phys_addr_t paddr, vaddr;
527 static void __ic_line_inv_vaddr_helper(void *info)
529 struct ic_inv_args *ic_inv = info;
531 __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz);
534 static void __ic_line_inv_vaddr(phys_addr_t paddr, unsigned long vaddr,
537 struct ic_inv_args ic_inv = {
543 on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1);
546 #endif /* CONFIG_SMP */
548 #else /* !CONFIG_ARC_HAS_ICACHE */
550 #define __ic_entire_inv()
551 #define __ic_line_inv_vaddr(pstart, vstart, sz)
553 #endif /* CONFIG_ARC_HAS_ICACHE */
555 noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
557 #ifdef CONFIG_ISA_ARCV2
559 * SLC is shared between all cores and concurrent aux operations from
560 * multiple cores need to be serialized using a spinlock
561 * A concurrent operation can be silently ignored and/or the old/new
562 * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop
565 static DEFINE_SPINLOCK(lock);
569 spin_lock_irqsave(&lock, flags);
572 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
573 * - b'000 (default) is Flush,
574 * - b'001 is Invalidate if CTRL.IM == 0
575 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
577 ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
579 /* Don't rely on default value of IM bit */
580 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
581 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
586 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
588 ctrl &= ~SLC_CTRL_RGN_OP_INV;
590 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
593 * Lower bits are ignored, no need to clip
594 * END needs to be setup before START (latter triggers the operation)
595 * END can't be same as START, so add (l2_line_sz - 1) to sz
597 write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
598 write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
600 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
602 spin_unlock_irqrestore(&lock, flags);
606 /***********************************************************
611 * Handle cache congruency of kernel and userspace mappings of page when kernel
612 * writes-to/reads-from
614 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
615 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
616 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
617 * -In SMP, if hardware caches are coherent
619 * There's a corollary case, where kernel READs from a userspace mapped page.
620 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
622 void flush_dcache_page(struct page *page)
624 struct address_space *mapping;
626 if (!cache_is_vipt_aliasing()) {
627 clear_bit(PG_dc_clean, &page->flags);
631 /* don't handle anon pages here */
632 mapping = page_mapping(page);
637 * pagecache page, file not yet mapped to userspace
638 * Make a note that K-mapping is dirty
640 if (!mapping_mapped(mapping)) {
641 clear_bit(PG_dc_clean, &page->flags);
642 } else if (page_mapcount(page)) {
644 /* kernel reading from page with U-mapping */
645 phys_addr_t paddr = (unsigned long)page_address(page);
646 unsigned long vaddr = page->index << PAGE_SHIFT;
648 if (addr_not_cache_congruent(paddr, vaddr))
649 __flush_dcache_page(paddr, vaddr);
652 EXPORT_SYMBOL(flush_dcache_page);
655 * DMA ops for systems with L1 cache only
656 * Make memory coherent with L1 cache by flushing/invalidating L1 lines
658 static void __dma_cache_wback_inv_l1(phys_addr_t start, unsigned long sz)
660 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
663 static void __dma_cache_inv_l1(phys_addr_t start, unsigned long sz)
665 __dc_line_op_k(start, sz, OP_INV);
668 static void __dma_cache_wback_l1(phys_addr_t start, unsigned long sz)
670 __dc_line_op_k(start, sz, OP_FLUSH);
674 * DMA ops for systems with both L1 and L2 caches, but without IOC
675 * Both L1 and L2 lines need to be explicitly flushed/invalidated
677 static void __dma_cache_wback_inv_slc(phys_addr_t start, unsigned long sz)
679 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
680 slc_op(start, sz, OP_FLUSH_N_INV);
683 static void __dma_cache_inv_slc(phys_addr_t start, unsigned long sz)
685 __dc_line_op_k(start, sz, OP_INV);
686 slc_op(start, sz, OP_INV);
689 static void __dma_cache_wback_slc(phys_addr_t start, unsigned long sz)
691 __dc_line_op_k(start, sz, OP_FLUSH);
692 slc_op(start, sz, OP_FLUSH);
696 * DMA ops for systems with IOC
697 * IOC hardware snoops all DMA traffic keeping the caches consistent with
698 * memory - eliding need for any explicit cache maintenance of DMA buffers
700 static void __dma_cache_wback_inv_ioc(phys_addr_t start, unsigned long sz) {}
701 static void __dma_cache_inv_ioc(phys_addr_t start, unsigned long sz) {}
702 static void __dma_cache_wback_ioc(phys_addr_t start, unsigned long sz) {}
707 void dma_cache_wback_inv(phys_addr_t start, unsigned long sz)
709 __dma_cache_wback_inv(start, sz);
711 EXPORT_SYMBOL(dma_cache_wback_inv);
713 void dma_cache_inv(phys_addr_t start, unsigned long sz)
715 __dma_cache_inv(start, sz);
717 EXPORT_SYMBOL(dma_cache_inv);
719 void dma_cache_wback(phys_addr_t start, unsigned long sz)
721 __dma_cache_wback(start, sz);
723 EXPORT_SYMBOL(dma_cache_wback);
726 * This is API for making I/D Caches consistent when modifying
727 * kernel code (loadable modules, kprobes, kgdb...)
728 * This is called on insmod, with kernel virtual address for CODE of
729 * the module. ARC cache maintenance ops require PHY address thus we
730 * need to convert vmalloc addr to PHY addr
732 void flush_icache_range(unsigned long kstart, unsigned long kend)
736 WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__);
738 /* Shortcut for bigger flush ranges.
739 * Here we don't care if this was kernel virtual or phy addr
741 tot_sz = kend - kstart;
742 if (tot_sz > PAGE_SIZE) {
747 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
748 if (likely(kstart > PAGE_OFFSET)) {
750 * The 2nd arg despite being paddr will be used to index icache
751 * This is OK since no alternate virtual mappings will exist
752 * given the callers for this case: kprobe/kgdb in built-in
755 __sync_icache_dcache(kstart, kstart, kend - kstart);
760 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
761 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
762 * handling of kernel vaddr.
764 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
765 * it still needs to handle a 2 page scenario, where the range
766 * straddles across 2 virtual pages and hence need for loop
769 unsigned int off, sz;
770 unsigned long phy, pfn;
772 off = kstart % PAGE_SIZE;
773 pfn = vmalloc_to_pfn((void *)kstart);
774 phy = (pfn << PAGE_SHIFT) + off;
775 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
776 __sync_icache_dcache(phy, kstart, sz);
781 EXPORT_SYMBOL(flush_icache_range);
784 * General purpose helper to make I and D cache lines consistent.
785 * @paddr is phy addr of region
786 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
787 * However in one instance, when called by kprobe (for a breakpt in
788 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
789 * use a paddr to index the cache (despite VIPT). This is fine since since a
790 * builtin kernel page will not have any virtual mappings.
791 * kprobe on loadable module will be kernel vaddr.
793 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
795 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
796 __ic_line_inv_vaddr(paddr, vaddr, len);
799 /* wrapper to compile time eliminate alignment checks in flush loop */
800 void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
802 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
806 * wrapper to clearout kernel or userspace mappings of a page
807 * For kernel mappings @vaddr == @paddr
809 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr)
811 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
814 noinline void flush_cache_all(void)
818 local_irq_save(flags);
821 __dc_entire_op(OP_FLUSH_N_INV);
823 local_irq_restore(flags);
827 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
829 void flush_cache_mm(struct mm_struct *mm)
834 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
837 unsigned int paddr = pfn << PAGE_SHIFT;
839 u_vaddr &= PAGE_MASK;
841 __flush_dcache_page(paddr, u_vaddr);
843 if (vma->vm_flags & VM_EXEC)
844 __inv_icache_page(paddr, u_vaddr);
847 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
853 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
854 unsigned long u_vaddr)
856 /* TBD: do we really need to clear the kernel mapping */
857 __flush_dcache_page(page_address(page), u_vaddr);
858 __flush_dcache_page(page_address(page), page_address(page));
864 void copy_user_highpage(struct page *to, struct page *from,
865 unsigned long u_vaddr, struct vm_area_struct *vma)
867 void *kfrom = kmap_atomic(from);
868 void *kto = kmap_atomic(to);
869 int clean_src_k_mappings = 0;
872 * If SRC page was already mapped in userspace AND it's U-mapping is
873 * not congruent with K-mapping, sync former to physical page so that
874 * K-mapping in memcpy below, sees the right data
876 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
877 * equally valid for SRC page as well
879 * For !VIPT cache, all of this gets compiled out as
880 * addr_not_cache_congruent() is 0
882 if (page_mapcount(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
883 __flush_dcache_page((unsigned long)kfrom, u_vaddr);
884 clean_src_k_mappings = 1;
887 copy_page(kto, kfrom);
890 * Mark DST page K-mapping as dirty for a later finalization by
891 * update_mmu_cache(). Although the finalization could have been done
892 * here as well (given that both vaddr/paddr are available).
893 * But update_mmu_cache() already has code to do that for other
894 * non copied user pages (e.g. read faults which wire in pagecache page
897 clear_bit(PG_dc_clean, &to->flags);
900 * if SRC was already usermapped and non-congruent to kernel mapping
901 * sync the kernel mapping back to physical page
903 if (clean_src_k_mappings) {
904 __flush_dcache_page((unsigned long)kfrom, (unsigned long)kfrom);
905 set_bit(PG_dc_clean, &from->flags);
907 clear_bit(PG_dc_clean, &from->flags);
911 kunmap_atomic(kfrom);
914 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
917 clear_bit(PG_dc_clean, &page->flags);
921 /**********************************************************************
922 * Explicit Cache flush request from user space via syscall
923 * Needed for JITs which generate code on the fly
925 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
927 /* TBD: optimize this */
932 void arc_cache_init(void)
934 unsigned int __maybe_unused cpu = smp_processor_id();
937 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
940 * Only master CPU needs to execute rest of function:
941 * - Assume SMP so all cores will have same cache config so
942 * any geomtry checks will be same for all
943 * - IOC setup / dma callbacks only need to be setup once
948 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
949 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
952 panic("cache support enabled but non-existent cache\n");
954 if (ic->line_len != L1_CACHE_BYTES)
955 panic("ICache line [%d] != kernel Config [%d]",
956 ic->line_len, L1_CACHE_BYTES);
958 if (ic->ver != CONFIG_ARC_MMU_VER)
959 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
960 ic->ver, CONFIG_ARC_MMU_VER);
963 * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG
964 * pair to provide vaddr/paddr respectively, just as in MMU v3
966 if (is_isa_arcv2() && ic->alias)
967 _cache_line_loop_ic_fn = __cache_line_loop_v3;
969 _cache_line_loop_ic_fn = __cache_line_loop;
972 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
973 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
976 panic("cache support enabled but non-existent cache\n");
978 if (dc->line_len != L1_CACHE_BYTES)
979 panic("DCache line [%d] != kernel Config [%d]",
980 dc->line_len, L1_CACHE_BYTES);
982 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
983 if (is_isa_arcompact()) {
984 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
986 if (dc->alias && !handled)
987 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
988 else if (!dc->alias && handled)
989 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
993 if (is_isa_arcv2() && l2_line_sz && !slc_enable) {
995 /* IM set : flush before invalidate */
996 write_aux_reg(ARC_REG_SLC_CTRL,
997 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM);
999 write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
1001 /* Important to wait for flush to complete */
1002 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
1003 write_aux_reg(ARC_REG_SLC_CTRL,
1004 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
1007 if (is_isa_arcv2() && ioc_enable) {
1008 /* IO coherency base - 0x8z */
1009 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
1010 /* IO coherency aperture size - 512Mb: 0x8z-0xAz */
1011 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
1012 /* Enable partial writes */
1013 write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
1014 /* Enable IO coherency */
1015 write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
1017 __dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
1018 __dma_cache_inv = __dma_cache_inv_ioc;
1019 __dma_cache_wback = __dma_cache_wback_ioc;
1020 } else if (is_isa_arcv2() && l2_line_sz && slc_enable) {
1021 __dma_cache_wback_inv = __dma_cache_wback_inv_slc;
1022 __dma_cache_inv = __dma_cache_inv_slc;
1023 __dma_cache_wback = __dma_cache_wback_slc;
1025 __dma_cache_wback_inv = __dma_cache_wback_inv_l1;
1026 __dma_cache_inv = __dma_cache_inv_l1;
1027 __dma_cache_wback = __dma_cache_wback_l1;