4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
69 select MODULES_USE_ELF_REL
72 select OLD_SIGSUSPEND3
73 select PERF_USE_VMALLOC
75 select SYS_SUPPORTS_APM_EMULATION
76 # Above selects are sorted alphabetically; please add new ones
77 # according to that. Thanks.
79 The ARM series is a line of low-power-consumption RISC chip designs
80 licensed by ARM Ltd and targeted at embedded applications and
81 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
82 manufactured, but legacy ARM-based PC hardware remains popular in
83 Europe. There is an ARM Linux project with a web page at
84 <http://www.arm.linux.org.uk/>.
86 config ARM_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_BANDGAP
182 config GENERIC_HWEIGHT
186 config GENERIC_CALIBRATE_DELAY
190 config ARCH_MAY_HAVE_PC_FDC
196 config NEED_DMA_MAP_STATE
199 config ARCH_SUPPORTS_UPROBES
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select ARM_HAS_SG_CHAIN
296 select ARM_PATCH_PHYS_VIRT
300 select GENERIC_CLOCKEVENTS
301 select MIGHT_HAVE_PCI
302 select MULTI_IRQ_HANDLER
306 config ARCH_INTEGRATOR
307 bool "ARM Ltd. Integrator family"
309 select ARM_PATCH_PHYS_VIRT
312 select COMMON_CLK_VERSATILE
313 select GENERIC_CLOCKEVENTS
316 select MULTI_IRQ_HANDLER
317 select NEED_MACH_MEMORY_H
318 select PLAT_VERSATILE
321 select VERSATILE_FPGA_IRQ
323 Support for ARM's Integrator platform.
326 bool "ARM Ltd. RealView family"
327 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_TIMER_SP804
331 select COMMON_CLK_VERSATILE
332 select GENERIC_CLOCKEVENTS
333 select GPIO_PL061 if GPIOLIB
335 select NEED_MACH_MEMORY_H
336 select PLAT_VERSATILE
337 select PLAT_VERSATILE_CLCD
339 This enables support for ARM Ltd RealView boards.
341 config ARCH_VERSATILE
342 bool "ARM Ltd. Versatile family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
348 select GENERIC_CLOCKEVENTS
349 select HAVE_MACH_CLKDEV
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
353 select PLAT_VERSATILE_CLOCK
354 select VERSATILE_FPGA_IRQ
356 This enables support for ARM Ltd Versatile board.
360 select ARCH_REQUIRE_GPIOLIB
363 select NEED_MACH_IO_H if PCCARD
365 select PINCTRL_AT91 if USE_OF
367 This enables support for systems based on Atmel
368 AT91RM9200 and AT91SAM9* processors.
371 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
372 select ARCH_REQUIRE_GPIOLIB
377 select GENERIC_CLOCKEVENTS
380 Support for Cirrus Logic 711x/721x/731x based boards.
383 bool "Cortina Systems Gemini"
384 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
389 Support for the Cortina Systems Gemini family SoCs
393 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_IO_H
397 select NEED_MACH_MEMORY_H
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
406 bool "Energy Micro efm32"
408 select ARCH_REQUIRE_GPIOLIB
414 select GENERIC_CLOCKEVENTS
420 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
425 select ARCH_HAS_HOLES_MEMORYMODEL
426 select ARCH_REQUIRE_GPIOLIB
427 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_MEMORY_H
434 This enables support for the Cirrus EP93xx series of CPUs.
436 config ARCH_FOOTBRIDGE
440 select GENERIC_CLOCKEVENTS
442 select NEED_MACH_IO_H if !MMU
443 select NEED_MACH_MEMORY_H
445 Support for systems based on the DC21285 companion chip
446 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
449 bool "Hilscher NetX based"
453 select GENERIC_CLOCKEVENTS
455 This enables support for systems based on the Hilscher NetX Soc
461 select NEED_MACH_MEMORY_H
462 select NEED_RET_TO_USER
468 Support for Intel's IOP13XX (XScale) family of processors.
473 select ARCH_REQUIRE_GPIOLIB
476 select NEED_RET_TO_USER
480 Support for Intel's 80219 and IOP32X (XScale) family of
486 select ARCH_REQUIRE_GPIOLIB
489 select NEED_RET_TO_USER
493 Support for Intel's IOP33X (XScale) family of processors.
498 select ARCH_HAS_DMA_SET_COHERENT_MASK
499 select ARCH_REQUIRE_GPIOLIB
500 select ARCH_SUPPORTS_BIG_ENDIAN
503 select DMABOUNCE if PCI
504 select GENERIC_CLOCKEVENTS
505 select MIGHT_HAVE_PCI
506 select NEED_MACH_IO_H
507 select USB_EHCI_BIG_ENDIAN_DESC
508 select USB_EHCI_BIG_ENDIAN_MMIO
510 Support for Intel's IXP4XX (XScale) family of processors.
514 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
517 select MIGHT_HAVE_PCI
521 select PLAT_ORION_LEGACY
523 Support for the Marvell Dove SoC 88AP510
526 bool "Marvell MV78xx0"
527 select ARCH_REQUIRE_GPIOLIB
529 select GENERIC_CLOCKEVENTS
532 select PLAT_ORION_LEGACY
534 Support for the following Marvell MV78xx0 series SoCs:
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
545 select PLAT_ORION_LEGACY
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_ALLOCATOR
557 select GENERIC_CLOCKEVENTS
560 select MULTI_IRQ_HANDLER
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
605 Support for the NXP LPC32XX family of processors
608 bool "PXA2xx/PXA3xx-based"
611 select ARCH_REQUIRE_GPIOLIB
612 select ARM_CPU_SUSPEND if PM
616 select GENERIC_CLOCKEVENTS
619 select MULTI_IRQ_HANDLER
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
626 bool "Qualcomm MSM (non-multiplatform)"
627 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
637 config ARCH_SHMOBILE_LEGACY
638 bool "Renesas ARM SoCs (non-multiplatform)"
640 select ARM_PATCH_PHYS_VIRT
642 select GENERIC_CLOCKEVENTS
643 select HAVE_ARM_SCU if SMP
644 select HAVE_ARM_TWD if SMP
645 select HAVE_MACH_CLKDEV
647 select MIGHT_HAVE_CACHE_L2X0
648 select MULTI_IRQ_HANDLER
651 select PM_GENERIC_DOMAINS if PM
654 Support for Renesas ARM SoC platforms using a non-multiplatform
655 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
661 select ARCH_MAY_HAVE_PC_FDC
662 select ARCH_SPARSEMEM_ENABLE
663 select ARCH_USES_GETTIMEOFFSET
667 select HAVE_PATA_PLATFORM
669 select NEED_MACH_IO_H
670 select NEED_MACH_MEMORY_H
674 On the Acorn Risc-PC, Linux can support the internal IDE disk and
675 CD-ROM interface, serial and parallel port, and the floppy drive.
680 select ARCH_REQUIRE_GPIOLIB
681 select ARCH_SPARSEMEM_ENABLE
686 select GENERIC_CLOCKEVENTS
689 select NEED_MACH_MEMORY_H
692 Support for StrongARM 11x0 based boards.
695 bool "Samsung S3C24XX SoCs"
696 select ARCH_REQUIRE_GPIOLIB
699 select CLKSRC_SAMSUNG_PWM
700 select GENERIC_CLOCKEVENTS
702 select HAVE_S3C2410_I2C if I2C
703 select HAVE_S3C2410_WATCHDOG if WATCHDOG
704 select HAVE_S3C_RTC if RTC_CLASS
705 select MULTI_IRQ_HANDLER
706 select NEED_MACH_IO_H
709 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
710 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
711 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
712 Samsung SMDK2410 development board (and derivatives).
715 bool "Samsung S3C64XX"
716 select ARCH_REQUIRE_GPIOLIB
721 select CLKSRC_SAMSUNG_PWM
722 select COMMON_CLK_SAMSUNG
724 select GENERIC_CLOCKEVENTS
726 select HAVE_S3C2410_I2C if I2C
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
731 select PM_GENERIC_DOMAINS if PM
733 select S3C_GPIO_TRACK
735 select SAMSUNG_WAKEMASK
736 select SAMSUNG_WDT_RESET
738 Samsung S3C64XX series based systems
742 select ARCH_HAS_HOLES_MEMORYMODEL
743 select ARCH_REQUIRE_GPIOLIB
745 select GENERIC_ALLOCATOR
746 select GENERIC_CLOCKEVENTS
747 select GENERIC_IRQ_CHIP
753 Support for TI's DaVinci platform.
758 select ARCH_HAS_HOLES_MEMORYMODEL
760 select ARCH_REQUIRE_GPIOLIB
763 select GENERIC_CLOCKEVENTS
764 select GENERIC_IRQ_CHIP
767 select NEED_MACH_IO_H if PCCARD
768 select NEED_MACH_MEMORY_H
770 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
774 menu "Multiple platform selection"
775 depends on ARCH_MULTIPLATFORM
777 comment "CPU Core family selection"
780 bool "ARMv4 based platforms (FA526)"
781 depends on !ARCH_MULTI_V6_V7
782 select ARCH_MULTI_V4_V5
785 config ARCH_MULTI_V4T
786 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
787 depends on !ARCH_MULTI_V6_V7
788 select ARCH_MULTI_V4_V5
789 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
790 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
791 CPU_ARM925T || CPU_ARM940T)
794 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
795 depends on !ARCH_MULTI_V6_V7
796 select ARCH_MULTI_V4_V5
797 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
798 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
799 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
801 config ARCH_MULTI_V4_V5
805 bool "ARMv6 based platforms (ARM11)"
806 select ARCH_MULTI_V6_V7
810 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
812 select ARCH_MULTI_V6_V7
816 config ARCH_MULTI_V6_V7
818 select MIGHT_HAVE_CACHE_L2X0
820 config ARCH_MULTI_CPU_AUTO
821 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
827 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
831 select HAVE_ARM_ARCH_TIMER
834 # This is sorted alphabetically by mach-* pathname. However, plat-*
835 # Kconfigs may be included either alphabetically (according to the
836 # plat- suffix) or along side the corresponding mach-* source.
838 source "arch/arm/mach-mvebu/Kconfig"
840 source "arch/arm/mach-at91/Kconfig"
842 source "arch/arm/mach-axxia/Kconfig"
844 source "arch/arm/mach-bcm/Kconfig"
846 source "arch/arm/mach-berlin/Kconfig"
848 source "arch/arm/mach-clps711x/Kconfig"
850 source "arch/arm/mach-cns3xxx/Kconfig"
852 source "arch/arm/mach-davinci/Kconfig"
854 source "arch/arm/mach-dove/Kconfig"
856 source "arch/arm/mach-ep93xx/Kconfig"
858 source "arch/arm/mach-footbridge/Kconfig"
860 source "arch/arm/mach-gemini/Kconfig"
862 source "arch/arm/mach-highbank/Kconfig"
864 source "arch/arm/mach-hisi/Kconfig"
866 source "arch/arm/mach-integrator/Kconfig"
868 source "arch/arm/mach-iop32x/Kconfig"
870 source "arch/arm/mach-iop33x/Kconfig"
872 source "arch/arm/mach-iop13xx/Kconfig"
874 source "arch/arm/mach-ixp4xx/Kconfig"
876 source "arch/arm/mach-keystone/Kconfig"
878 source "arch/arm/mach-ks8695/Kconfig"
880 source "arch/arm/mach-msm/Kconfig"
882 source "arch/arm/mach-moxart/Kconfig"
884 source "arch/arm/mach-mv78xx0/Kconfig"
886 source "arch/arm/mach-imx/Kconfig"
888 source "arch/arm/mach-mediatek/Kconfig"
890 source "arch/arm/mach-mxs/Kconfig"
892 source "arch/arm/mach-netx/Kconfig"
894 source "arch/arm/mach-nomadik/Kconfig"
896 source "arch/arm/mach-nspire/Kconfig"
898 source "arch/arm/plat-omap/Kconfig"
900 source "arch/arm/mach-omap1/Kconfig"
902 source "arch/arm/mach-omap2/Kconfig"
904 source "arch/arm/mach-orion5x/Kconfig"
906 source "arch/arm/mach-picoxcell/Kconfig"
908 source "arch/arm/mach-pxa/Kconfig"
909 source "arch/arm/plat-pxa/Kconfig"
911 source "arch/arm/mach-mmp/Kconfig"
913 source "arch/arm/mach-qcom/Kconfig"
915 source "arch/arm/mach-realview/Kconfig"
917 source "arch/arm/mach-rockchip/Kconfig"
919 source "arch/arm/mach-sa1100/Kconfig"
921 source "arch/arm/mach-socfpga/Kconfig"
923 source "arch/arm/mach-spear/Kconfig"
925 source "arch/arm/mach-sti/Kconfig"
927 source "arch/arm/mach-s3c24xx/Kconfig"
929 source "arch/arm/mach-s3c64xx/Kconfig"
931 source "arch/arm/mach-s5pv210/Kconfig"
933 source "arch/arm/mach-exynos/Kconfig"
934 source "arch/arm/plat-samsung/Kconfig"
936 source "arch/arm/mach-shmobile/Kconfig"
938 source "arch/arm/mach-sunxi/Kconfig"
940 source "arch/arm/mach-prima2/Kconfig"
942 source "arch/arm/mach-tegra/Kconfig"
944 source "arch/arm/mach-u300/Kconfig"
946 source "arch/arm/mach-ux500/Kconfig"
948 source "arch/arm/mach-versatile/Kconfig"
950 source "arch/arm/mach-vexpress/Kconfig"
951 source "arch/arm/plat-versatile/Kconfig"
953 source "arch/arm/mach-vt8500/Kconfig"
955 source "arch/arm/mach-w90x900/Kconfig"
957 source "arch/arm/mach-zynq/Kconfig"
959 # Definitions to make life easier
965 select GENERIC_CLOCKEVENTS
971 select GENERIC_IRQ_CHIP
974 config PLAT_ORION_LEGACY
981 config PLAT_VERSATILE
984 config ARM_TIMER_SP804
987 select CLKSRC_OF if OF
989 source "arch/arm/firmware/Kconfig"
991 source arch/arm/mm/Kconfig
994 bool "Enable iWMMXt support"
995 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
996 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
998 Enable support for iWMMXt context switching at run time if
999 running on a CPU that supports it.
1001 config MULTI_IRQ_HANDLER
1004 Allow each machine to specify it's own IRQ handler at run time.
1007 source "arch/arm/Kconfig-nommu"
1010 config PJ4B_ERRATA_4742
1011 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1012 depends on CPU_PJ4B && MACH_ARMADA_370
1015 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1016 Event (WFE) IDLE states, a specific timing sensitivity exists between
1017 the retiring WFI/WFE instructions and the newly issued subsequent
1018 instructions. This sensitivity can result in a CPU hang scenario.
1020 The software must insert either a Data Synchronization Barrier (DSB)
1021 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1024 config ARM_ERRATA_326103
1025 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1028 Executing a SWP instruction to read-only memory does not set bit 11
1029 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1030 treat the access as a read, preventing a COW from occurring and
1031 causing the faulting task to livelock.
1033 config ARM_ERRATA_411920
1034 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1035 depends on CPU_V6 || CPU_V6K
1037 Invalidation of the Instruction Cache operation can
1038 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1039 It does not affect the MPCore. This option enables the ARM Ltd.
1040 recommended workaround.
1042 config ARM_ERRATA_430973
1043 bool "ARM errata: Stale prediction on replaced interworking branch"
1046 This option enables the workaround for the 430973 Cortex-A8
1047 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1048 interworking branch is replaced with another code sequence at the
1049 same virtual address, whether due to self-modifying code or virtual
1050 to physical address re-mapping, Cortex-A8 does not recover from the
1051 stale interworking branch prediction. This results in Cortex-A8
1052 executing the new code sequence in the incorrect ARM or Thumb state.
1053 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1054 and also flushes the branch target cache at every context switch.
1055 Note that setting specific bits in the ACTLR register may not be
1056 available in non-secure mode.
1058 config ARM_ERRATA_458693
1059 bool "ARM errata: Processor deadlock when a false hazard is created"
1061 depends on !ARCH_MULTIPLATFORM
1063 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1064 erratum. For very specific sequences of memory operations, it is
1065 possible for a hazard condition intended for a cache line to instead
1066 be incorrectly associated with a different cache line. This false
1067 hazard might then cause a processor deadlock. The workaround enables
1068 the L1 caching of the NEON accesses and disables the PLD instruction
1069 in the ACTLR register. Note that setting specific bits in the ACTLR
1070 register may not be available in non-secure mode.
1072 config ARM_ERRATA_460075
1073 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1075 depends on !ARCH_MULTIPLATFORM
1077 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1078 erratum. Any asynchronous access to the L2 cache may encounter a
1079 situation in which recent store transactions to the L2 cache are lost
1080 and overwritten with stale memory contents from external memory. The
1081 workaround disables the write-allocate mode for the L2 cache via the
1082 ACTLR register. Note that setting specific bits in the ACTLR register
1083 may not be available in non-secure mode.
1085 config ARM_ERRATA_742230
1086 bool "ARM errata: DMB operation may be faulty"
1087 depends on CPU_V7 && SMP
1088 depends on !ARCH_MULTIPLATFORM
1090 This option enables the workaround for the 742230 Cortex-A9
1091 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1092 between two write operations may not ensure the correct visibility
1093 ordering of the two writes. This workaround sets a specific bit in
1094 the diagnostic register of the Cortex-A9 which causes the DMB
1095 instruction to behave as a DSB, ensuring the correct behaviour of
1098 config ARM_ERRATA_742231
1099 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1100 depends on CPU_V7 && SMP
1101 depends on !ARCH_MULTIPLATFORM
1103 This option enables the workaround for the 742231 Cortex-A9
1104 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1105 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1106 accessing some data located in the same cache line, may get corrupted
1107 data due to bad handling of the address hazard when the line gets
1108 replaced from one of the CPUs at the same time as another CPU is
1109 accessing it. This workaround sets specific bits in the diagnostic
1110 register of the Cortex-A9 which reduces the linefill issuing
1111 capabilities of the processor.
1113 config ARM_ERRATA_643719
1114 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1115 depends on CPU_V7 && SMP
1117 This option enables the workaround for the 643719 Cortex-A9 (prior to
1118 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1119 register returns zero when it should return one. The workaround
1120 corrects this value, ensuring cache maintenance operations which use
1121 it behave as intended and avoiding data corruption.
1123 config ARM_ERRATA_720789
1124 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1127 This option enables the workaround for the 720789 Cortex-A9 (prior to
1128 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1129 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1130 As a consequence of this erratum, some TLB entries which should be
1131 invalidated are not, resulting in an incoherency in the system page
1132 tables. The workaround changes the TLB flushing routines to invalidate
1133 entries regardless of the ASID.
1135 config ARM_ERRATA_743622
1136 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1138 depends on !ARCH_MULTIPLATFORM
1140 This option enables the workaround for the 743622 Cortex-A9
1141 (r2p*) erratum. Under very rare conditions, a faulty
1142 optimisation in the Cortex-A9 Store Buffer may lead to data
1143 corruption. This workaround sets a specific bit in the diagnostic
1144 register of the Cortex-A9 which disables the Store Buffer
1145 optimisation, preventing the defect from occurring. This has no
1146 visible impact on the overall performance or power consumption of the
1149 config ARM_ERRATA_751472
1150 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1152 depends on !ARCH_MULTIPLATFORM
1154 This option enables the workaround for the 751472 Cortex-A9 (prior
1155 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1156 completion of a following broadcasted operation if the second
1157 operation is received by a CPU before the ICIALLUIS has completed,
1158 potentially leading to corrupted entries in the cache or TLB.
1160 config ARM_ERRATA_754322
1161 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1164 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1165 r3p*) erratum. A speculative memory access may cause a page table walk
1166 which starts prior to an ASID switch but completes afterwards. This
1167 can populate the micro-TLB with a stale entry which may be hit with
1168 the new ASID. This workaround places two dsb instructions in the mm
1169 switching code so that no page table walks can cross the ASID switch.
1171 config ARM_ERRATA_754327
1172 bool "ARM errata: no automatic Store Buffer drain"
1173 depends on CPU_V7 && SMP
1175 This option enables the workaround for the 754327 Cortex-A9 (prior to
1176 r2p0) erratum. The Store Buffer does not have any automatic draining
1177 mechanism and therefore a livelock may occur if an external agent
1178 continuously polls a memory location waiting to observe an update.
1179 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1180 written polling loops from denying visibility of updates to memory.
1182 config ARM_ERRATA_364296
1183 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1186 This options enables the workaround for the 364296 ARM1136
1187 r0p2 erratum (possible cache data corruption with
1188 hit-under-miss enabled). It sets the undocumented bit 31 in
1189 the auxiliary control register and the FI bit in the control
1190 register, thus disabling hit-under-miss without putting the
1191 processor into full low interrupt latency mode. ARM11MPCore
1194 config ARM_ERRATA_764369
1195 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1196 depends on CPU_V7 && SMP
1198 This option enables the workaround for erratum 764369
1199 affecting Cortex-A9 MPCore with two or more processors (all
1200 current revisions). Under certain timing circumstances, a data
1201 cache line maintenance operation by MVA targeting an Inner
1202 Shareable memory region may fail to proceed up to either the
1203 Point of Coherency or to the Point of Unification of the
1204 system. This workaround adds a DSB instruction before the
1205 relevant cache maintenance functions and sets a specific bit
1206 in the diagnostic control register of the SCU.
1208 config ARM_ERRATA_775420
1209 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1212 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1213 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1214 operation aborts with MMU exception, it might cause the processor
1215 to deadlock. This workaround puts DSB before executing ISB if
1216 an abort may occur on cache maintenance.
1218 config ARM_ERRATA_798181
1219 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1220 depends on CPU_V7 && SMP
1222 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1223 adequately shooting down all use of the old entries. This
1224 option enables the Linux kernel workaround for this erratum
1225 which sends an IPI to the CPUs that are running the same ASID
1226 as the one being invalidated.
1228 config ARM_ERRATA_773022
1229 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1232 This option enables the workaround for the 773022 Cortex-A15
1233 (up to r0p4) erratum. In certain rare sequences of code, the
1234 loop buffer may deliver incorrect instructions. This
1235 workaround disables the loop buffer to avoid the erratum.
1239 source "arch/arm/common/Kconfig"
1249 Find out whether you have ISA slots on your motherboard. ISA is the
1250 name of a bus system, i.e. the way the CPU talks to the other stuff
1251 inside your box. Other bus systems are PCI, EISA, MicroChannel
1252 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1253 newer boards don't support it. If you have ISA, say Y, otherwise N.
1255 # Select ISA DMA controller support
1260 # Select ISA DMA interface
1265 bool "PCI support" if MIGHT_HAVE_PCI
1267 Find out whether you have a PCI motherboard. PCI is the name of a
1268 bus system, i.e. the way the CPU talks to the other stuff inside
1269 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1270 VESA. If you have PCI, say Y, otherwise N.
1276 config PCI_NANOENGINE
1277 bool "BSE nanoEngine PCI support"
1278 depends on SA1100_NANOENGINE
1280 Enable PCI on the BSE nanoEngine board.
1285 config PCI_HOST_ITE8152
1287 depends on PCI && MACH_ARMCORE
1291 source "drivers/pci/Kconfig"
1292 source "drivers/pci/pcie/Kconfig"
1294 source "drivers/pcmcia/Kconfig"
1298 menu "Kernel Features"
1303 This option should be selected by machines which have an SMP-
1306 The only effect of this option is to make the SMP-related
1307 options available to the user for configuration.
1310 bool "Symmetric Multi-Processing"
1311 depends on CPU_V6K || CPU_V7
1312 depends on GENERIC_CLOCKEVENTS
1314 depends on MMU || ARM_MPU
1316 This enables support for systems with more than one CPU. If you have
1317 a system with only one CPU, say N. If you have a system with more
1318 than one CPU, say Y.
1320 If you say N here, the kernel will run on uni- and multiprocessor
1321 machines, but will use only one CPU of a multiprocessor machine. If
1322 you say Y here, the kernel will run on many, but not all,
1323 uniprocessor machines. On a uniprocessor machine, the kernel
1324 will run faster if you say N here.
1326 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1327 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1328 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1330 If you don't know what to do here, say N.
1333 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1334 depends on SMP && !XIP_KERNEL && MMU
1337 SMP kernels contain instructions which fail on non-SMP processors.
1338 Enabling this option allows the kernel to modify itself to make
1339 these instructions safe. Disabling it allows about 1K of space
1342 If you don't know what to do here, say Y.
1344 config ARM_CPU_TOPOLOGY
1345 bool "Support cpu topology definition"
1346 depends on SMP && CPU_V7
1349 Support ARM cpu topology definition. The MPIDR register defines
1350 affinity between processors which is then used to describe the cpu
1351 topology of an ARM System.
1354 bool "Multi-core scheduler support"
1355 depends on ARM_CPU_TOPOLOGY
1357 Multi-core scheduler support improves the CPU scheduler's decision
1358 making when dealing with multi-core CPU chips at a cost of slightly
1359 increased overhead in some places. If unsure say N here.
1362 bool "SMT scheduler support"
1363 depends on ARM_CPU_TOPOLOGY
1365 Improves the CPU scheduler's decision making when dealing with
1366 MultiThreading at a cost of slightly increased overhead in some
1367 places. If unsure say N here.
1372 This option enables support for the ARM system coherency unit
1374 config HAVE_ARM_ARCH_TIMER
1375 bool "Architected timer support"
1377 select ARM_ARCH_TIMER
1378 select GENERIC_CLOCKEVENTS
1380 This option enables support for the ARM architected timer
1385 select CLKSRC_OF if OF
1387 This options enables support for the ARM timer and watchdog unit
1390 bool "Multi-Cluster Power Management"
1391 depends on CPU_V7 && SMP
1393 This option provides the common power management infrastructure
1394 for (multi-)cluster based systems, such as big.LITTLE based
1398 bool "big.LITTLE support (Experimental)"
1399 depends on CPU_V7 && SMP
1402 This option enables support selections for the big.LITTLE
1403 system architecture.
1406 bool "big.LITTLE switcher support"
1407 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1408 select ARM_CPU_SUSPEND
1411 The big.LITTLE "switcher" provides the core functionality to
1412 transparently handle transition between a cluster of A15's
1413 and a cluster of A7's in a big.LITTLE system.
1415 config BL_SWITCHER_DUMMY_IF
1416 tristate "Simple big.LITTLE switcher user interface"
1417 depends on BL_SWITCHER && DEBUG_KERNEL
1419 This is a simple and dummy char dev interface to control
1420 the big.LITTLE switcher core code. It is meant for
1421 debugging purposes only.
1424 prompt "Memory split"
1428 Select the desired split between kernel and user memory.
1430 If you are not absolutely sure what you are doing, leave this
1434 bool "3G/1G user/kernel split"
1436 bool "2G/2G user/kernel split"
1438 bool "1G/3G user/kernel split"
1443 default PHYS_OFFSET if !MMU
1444 default 0x40000000 if VMSPLIT_1G
1445 default 0x80000000 if VMSPLIT_2G
1449 int "Maximum number of CPUs (2-32)"
1455 bool "Support for hot-pluggable CPUs"
1458 Say Y here to experiment with turning CPUs off and on. CPUs
1459 can be controlled through /sys/devices/system/cpu.
1462 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1465 Say Y here if you want Linux to communicate with system firmware
1466 implementing the PSCI specification for CPU-centric power
1467 management operations described in ARM document number ARM DEN
1468 0022A ("Power State Coordination Interface System Software on
1471 # The GPIO number here must be sorted by descending number. In case of
1472 # a multiplatform kernel, we just want the highest value required by the
1473 # selected platforms.
1476 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1477 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1478 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1479 default 416 if ARCH_SUNXI
1480 default 392 if ARCH_U8500
1481 default 352 if ARCH_VT8500
1482 default 264 if MACH_H4700
1485 Maximum number of GPIOs in the system.
1487 If unsure, leave the default value.
1489 source kernel/Kconfig.preempt
1493 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1494 ARCH_S5PV210 || ARCH_EXYNOS4
1495 default AT91_TIMER_HZ if ARCH_AT91
1496 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1500 depends on HZ_FIXED = 0
1501 prompt "Timer frequency"
1525 default HZ_FIXED if HZ_FIXED != 0
1526 default 100 if HZ_100
1527 default 200 if HZ_200
1528 default 250 if HZ_250
1529 default 300 if HZ_300
1530 default 500 if HZ_500
1534 def_bool HIGH_RES_TIMERS
1536 config THUMB2_KERNEL
1537 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1538 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1539 default y if CPU_THUMBONLY
1541 select ARM_ASM_UNIFIED
1544 By enabling this option, the kernel will be compiled in
1545 Thumb-2 mode. A compiler/assembler that understand the unified
1546 ARM-Thumb syntax is needed.
1550 config THUMB2_AVOID_R_ARM_THM_JUMP11
1551 bool "Work around buggy Thumb-2 short branch relocations in gas"
1552 depends on THUMB2_KERNEL && MODULES
1555 Various binutils versions can resolve Thumb-2 branches to
1556 locally-defined, preemptible global symbols as short-range "b.n"
1557 branch instructions.
1559 This is a problem, because there's no guarantee the final
1560 destination of the symbol, or any candidate locations for a
1561 trampoline, are within range of the branch. For this reason, the
1562 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1563 relocation in modules at all, and it makes little sense to add
1566 The symptom is that the kernel fails with an "unsupported
1567 relocation" error when loading some modules.
1569 Until fixed tools are available, passing
1570 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1571 code which hits this problem, at the cost of a bit of extra runtime
1572 stack usage in some cases.
1574 The problem is described in more detail at:
1575 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1577 Only Thumb-2 kernels are affected.
1579 Unless you are sure your tools don't have this problem, say Y.
1581 config ARM_ASM_UNIFIED
1585 bool "Use the ARM EABI to compile the kernel"
1587 This option allows for the kernel to be compiled using the latest
1588 ARM ABI (aka EABI). This is only useful if you are using a user
1589 space environment that is also compiled with EABI.
1591 Since there are major incompatibilities between the legacy ABI and
1592 EABI, especially with regard to structure member alignment, this
1593 option also changes the kernel syscall calling convention to
1594 disambiguate both ABIs and allow for backward compatibility support
1595 (selected with CONFIG_OABI_COMPAT).
1597 To use this you need GCC version 4.0.0 or later.
1600 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1601 depends on AEABI && !THUMB2_KERNEL
1603 This option preserves the old syscall interface along with the
1604 new (ARM EABI) one. It also provides a compatibility layer to
1605 intercept syscalls that have structure arguments which layout
1606 in memory differs between the legacy ABI and the new ARM EABI
1607 (only for non "thumb" binaries). This option adds a tiny
1608 overhead to all syscalls and produces a slightly larger kernel.
1610 The seccomp filter system will not be available when this is
1611 selected, since there is no way yet to sensibly distinguish
1612 between calling conventions during filtering.
1614 If you know you'll be using only pure EABI user space then you
1615 can say N here. If this option is not selected and you attempt
1616 to execute a legacy ABI binary then the result will be
1617 UNPREDICTABLE (in fact it can be predicted that it won't work
1618 at all). If in doubt say N.
1620 config ARCH_HAS_HOLES_MEMORYMODEL
1623 config ARCH_SPARSEMEM_ENABLE
1626 config ARCH_SPARSEMEM_DEFAULT
1627 def_bool ARCH_SPARSEMEM_ENABLE
1629 config ARCH_SELECT_MEMORY_MODEL
1630 def_bool ARCH_SPARSEMEM_ENABLE
1632 config HAVE_ARCH_PFN_VALID
1633 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1636 bool "High Memory Support"
1639 The address space of ARM processors is only 4 Gigabytes large
1640 and it has to accommodate user address space, kernel address
1641 space as well as some memory mapped IO. That means that, if you
1642 have a large amount of physical memory and/or IO, not all of the
1643 memory can be "permanently mapped" by the kernel. The physical
1644 memory that is not permanently mapped is called "high memory".
1646 Depending on the selected kernel/user memory split, minimum
1647 vmalloc space and actual amount of RAM, you may not need this
1648 option which should result in a slightly faster kernel.
1653 bool "Allocate 2nd-level pagetables from highmem"
1656 config HW_PERF_EVENTS
1657 bool "Enable hardware performance counter support for perf events"
1658 depends on PERF_EVENTS
1661 Enable hardware performance counter support for perf events. If
1662 disabled, perf events will use software events only.
1664 config SYS_SUPPORTS_HUGETLBFS
1668 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1672 config ARCH_WANT_GENERAL_HUGETLB
1677 config FORCE_MAX_ZONEORDER
1678 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1679 range 11 64 if ARCH_SHMOBILE_LEGACY
1680 default "12" if SOC_AM33XX
1681 default "9" if SA1111 || ARCH_EFM32
1684 The kernel memory allocator divides physically contiguous memory
1685 blocks into "zones", where each zone is a power of two number of
1686 pages. This option selects the largest power of two that the kernel
1687 keeps in the memory allocator. If you need to allocate very large
1688 blocks of physically contiguous memory, then you may need to
1689 increase this value.
1691 This config option is actually maximum order plus one. For example,
1692 a value of 11 means that the largest free memory block is 2^10 pages.
1694 config ALIGNMENT_TRAP
1696 depends on CPU_CP15_MMU
1697 default y if !ARCH_EBSA110
1698 select HAVE_PROC_CPU if PROC_FS
1700 ARM processors cannot fetch/store information which is not
1701 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1702 address divisible by 4. On 32-bit ARM processors, these non-aligned
1703 fetch/store instructions will be emulated in software if you say
1704 here, which has a severe performance impact. This is necessary for
1705 correct operation of some network protocols. With an IP-only
1706 configuration it is safe to say N, otherwise say Y.
1708 config UACCESS_WITH_MEMCPY
1709 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1711 default y if CPU_FEROCEON
1713 Implement faster copy_to_user and clear_user methods for CPU
1714 cores where a 8-word STM instruction give significantly higher
1715 memory write throughput than a sequence of individual 32bit stores.
1717 A possible side effect is a slight increase in scheduling latency
1718 between threads sharing the same address space if they invoke
1719 such copy operations with large buffers.
1721 However, if the CPU data cache is using a write-allocate mode,
1722 this option is unlikely to provide any performance gain.
1726 prompt "Enable seccomp to safely compute untrusted bytecode"
1728 This kernel feature is useful for number crunching applications
1729 that may need to compute untrusted bytecode during their
1730 execution. By using pipes or other transports made available to
1731 the process as file descriptors supporting the read/write
1732 syscalls, it's possible to isolate those applications in
1733 their own address space using seccomp. Once seccomp is
1734 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1735 and the task is only allowed to execute a few safe syscalls
1736 defined by each seccomp mode.
1749 bool "Xen guest support on ARM (EXPERIMENTAL)"
1750 depends on ARM && AEABI && OF
1751 depends on CPU_V7 && !CPU_V6
1752 depends on !GENERIC_ATOMIC64
1754 select ARCH_DMA_ADDR_T_64BIT
1758 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1765 bool "Flattened Device Tree support"
1768 select OF_EARLY_FLATTREE
1769 select OF_RESERVED_MEM
1771 Include support for flattened device tree machine descriptions.
1774 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1777 This is the traditional way of passing data to the kernel at boot
1778 time. If you are solely relying on the flattened device tree (or
1779 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1780 to remove ATAGS support from your kernel binary. If unsure,
1783 config DEPRECATED_PARAM_STRUCT
1784 bool "Provide old way to pass kernel parameters"
1787 This was deprecated in 2001 and announced to live on for 5 years.
1788 Some old boot loaders still use this way.
1790 # Compressed boot loader in ROM. Yes, we really want to ask about
1791 # TEXT and BSS so we preserve their values in the config files.
1792 config ZBOOT_ROM_TEXT
1793 hex "Compressed ROM boot loader base address"
1796 The physical address at which the ROM-able zImage is to be
1797 placed in the target. Platforms which normally make use of
1798 ROM-able zImage formats normally set this to a suitable
1799 value in their defconfig file.
1801 If ZBOOT_ROM is not enabled, this has no effect.
1803 config ZBOOT_ROM_BSS
1804 hex "Compressed ROM boot loader BSS address"
1807 The base address of an area of read/write memory in the target
1808 for the ROM-able zImage which must be available while the
1809 decompressor is running. It must be large enough to hold the
1810 entire decompressed kernel plus an additional 128 KiB.
1811 Platforms which normally make use of ROM-able zImage formats
1812 normally set this to a suitable value in their defconfig file.
1814 If ZBOOT_ROM is not enabled, this has no effect.
1817 bool "Compressed boot loader in ROM/flash"
1818 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1819 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1821 Say Y here if you intend to execute your compressed kernel image
1822 (zImage) directly from ROM or flash. If unsure, say N.
1825 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1826 depends on ZBOOT_ROM && ARCH_SH7372
1827 default ZBOOT_ROM_NONE
1829 Include experimental SD/MMC loading code in the ROM-able zImage.
1830 With this enabled it is possible to write the ROM-able zImage
1831 kernel image to an MMC or SD card and boot the kernel straight
1832 from the reset vector. At reset the processor Mask ROM will load
1833 the first part of the ROM-able zImage which in turn loads the
1834 rest the kernel image to RAM.
1836 config ZBOOT_ROM_NONE
1837 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1839 Do not load image from SD or MMC
1841 config ZBOOT_ROM_MMCIF
1842 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1844 Load image from MMCIF hardware block.
1846 config ZBOOT_ROM_SH_MOBILE_SDHI
1847 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1849 Load image from SDHI hardware block
1853 config ARM_APPENDED_DTB
1854 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1857 With this option, the boot code will look for a device tree binary
1858 (DTB) appended to zImage
1859 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1861 This is meant as a backward compatibility convenience for those
1862 systems with a bootloader that can't be upgraded to accommodate
1863 the documented boot protocol using a device tree.
1865 Beware that there is very little in terms of protection against
1866 this option being confused by leftover garbage in memory that might
1867 look like a DTB header after a reboot if no actual DTB is appended
1868 to zImage. Do not leave this option active in a production kernel
1869 if you don't intend to always append a DTB. Proper passing of the
1870 location into r2 of a bootloader provided DTB is always preferable
1873 config ARM_ATAG_DTB_COMPAT
1874 bool "Supplement the appended DTB with traditional ATAG information"
1875 depends on ARM_APPENDED_DTB
1877 Some old bootloaders can't be updated to a DTB capable one, yet
1878 they provide ATAGs with memory configuration, the ramdisk address,
1879 the kernel cmdline string, etc. Such information is dynamically
1880 provided by the bootloader and can't always be stored in a static
1881 DTB. To allow a device tree enabled kernel to be used with such
1882 bootloaders, this option allows zImage to extract the information
1883 from the ATAG list and store it at run time into the appended DTB.
1886 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1887 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1889 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1890 bool "Use bootloader kernel arguments if available"
1892 Uses the command-line options passed by the boot loader instead of
1893 the device tree bootargs property. If the boot loader doesn't provide
1894 any, the device tree bootargs property will be used.
1896 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1897 bool "Extend with bootloader kernel arguments"
1899 The command-line arguments provided by the boot loader will be
1900 appended to the the device tree bootargs property.
1905 string "Default kernel command string"
1908 On some architectures (EBSA110 and CATS), there is currently no way
1909 for the boot loader to pass arguments to the kernel. For these
1910 architectures, you should supply some command-line options at build
1911 time by entering them here. As a minimum, you should specify the
1912 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1915 prompt "Kernel command line type" if CMDLINE != ""
1916 default CMDLINE_FROM_BOOTLOADER
1919 config CMDLINE_FROM_BOOTLOADER
1920 bool "Use bootloader kernel arguments if available"
1922 Uses the command-line options passed by the boot loader. If
1923 the boot loader doesn't provide any, the default kernel command
1924 string provided in CMDLINE will be used.
1926 config CMDLINE_EXTEND
1927 bool "Extend bootloader kernel arguments"
1929 The command-line arguments provided by the boot loader will be
1930 appended to the default kernel command string.
1932 config CMDLINE_FORCE
1933 bool "Always use the default kernel command string"
1935 Always use the default kernel command string, even if the boot
1936 loader passes other arguments to the kernel.
1937 This is useful if you cannot or don't want to change the
1938 command-line options your boot loader passes to the kernel.
1942 bool "Kernel Execute-In-Place from ROM"
1943 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1945 Execute-In-Place allows the kernel to run from non-volatile storage
1946 directly addressable by the CPU, such as NOR flash. This saves RAM
1947 space since the text section of the kernel is not loaded from flash
1948 to RAM. Read-write sections, such as the data section and stack,
1949 are still copied to RAM. The XIP kernel is not compressed since
1950 it has to run directly from flash, so it will take more space to
1951 store it. The flash address used to link the kernel object files,
1952 and for storing it, is configuration dependent. Therefore, if you
1953 say Y here, you must know the proper physical address where to
1954 store the kernel image depending on your own flash memory usage.
1956 Also note that the make target becomes "make xipImage" rather than
1957 "make zImage" or "make Image". The final kernel binary to put in
1958 ROM memory will be arch/arm/boot/xipImage.
1962 config XIP_PHYS_ADDR
1963 hex "XIP Kernel Physical Location"
1964 depends on XIP_KERNEL
1965 default "0x00080000"
1967 This is the physical address in your flash memory the kernel will
1968 be linked for and stored to. This address is dependent on your
1972 bool "Kexec system call (EXPERIMENTAL)"
1973 depends on (!SMP || PM_SLEEP_SMP)
1975 kexec is a system call that implements the ability to shutdown your
1976 current kernel, and to start another kernel. It is like a reboot
1977 but it is independent of the system firmware. And like a reboot
1978 you can start any kernel with it, not just Linux.
1980 It is an ongoing process to be certain the hardware in a machine
1981 is properly shutdown, so do not be surprised if this code does not
1982 initially work for you.
1985 bool "Export atags in procfs"
1986 depends on ATAGS && KEXEC
1989 Should the atags used to boot the kernel be exported in an "atags"
1990 file in procfs. Useful with kexec.
1993 bool "Build kdump crash kernel (EXPERIMENTAL)"
1995 Generate crash dump after being started by kexec. This should
1996 be normally only set in special crash dump kernels which are
1997 loaded in the main kernel with kexec-tools into a specially
1998 reserved region and then later executed after a crash by
1999 kdump/kexec. The crash dump kernel must be compiled to a
2000 memory address not used by the main kernel
2002 For more details see Documentation/kdump/kdump.txt
2004 config AUTO_ZRELADDR
2005 bool "Auto calculation of the decompressed kernel image address"
2007 ZRELADDR is the physical address where the decompressed kernel
2008 image will be placed. If AUTO_ZRELADDR is selected, the address
2009 will be determined at run-time by masking the current IP with
2010 0xf8000000. This assumes the zImage being placed in the first 128MB
2011 from start of memory.
2015 menu "CPU Power Management"
2017 source "drivers/cpufreq/Kconfig"
2019 source "drivers/cpuidle/Kconfig"
2023 menu "Floating point emulation"
2025 comment "At least one emulation must be selected"
2028 bool "NWFPE math emulation"
2029 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2031 Say Y to include the NWFPE floating point emulator in the kernel.
2032 This is necessary to run most binaries. Linux does not currently
2033 support floating point hardware so you need to say Y here even if
2034 your machine has an FPA or floating point co-processor podule.
2036 You may say N here if you are going to load the Acorn FPEmulator
2037 early in the bootup.
2040 bool "Support extended precision"
2041 depends on FPE_NWFPE
2043 Say Y to include 80-bit support in the kernel floating-point
2044 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2045 Note that gcc does not generate 80-bit operations by default,
2046 so in most cases this option only enlarges the size of the
2047 floating point emulator without any good reason.
2049 You almost surely want to say N here.
2052 bool "FastFPE math emulation (EXPERIMENTAL)"
2053 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2055 Say Y here to include the FAST floating point emulator in the kernel.
2056 This is an experimental much faster emulator which now also has full
2057 precision for the mantissa. It does not support any exceptions.
2058 It is very simple, and approximately 3-6 times faster than NWFPE.
2060 It should be sufficient for most programs. It may be not suitable
2061 for scientific calculations, but you have to check this for yourself.
2062 If you do not feel you need a faster FP emulation you should better
2066 bool "VFP-format floating point maths"
2067 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2069 Say Y to include VFP support code in the kernel. This is needed
2070 if your hardware includes a VFP unit.
2072 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2073 release notes and additional status information.
2075 Say N if your target does not have VFP hardware.
2083 bool "Advanced SIMD (NEON) Extension support"
2084 depends on VFPv3 && CPU_V7
2086 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2089 config KERNEL_MODE_NEON
2090 bool "Support for NEON in kernel mode"
2091 depends on NEON && AEABI
2093 Say Y to include support for NEON in kernel mode.
2097 menu "Userspace binary formats"
2099 source "fs/Kconfig.binfmt"
2102 tristate "RISC OS personality"
2105 Say Y here to include the kernel code necessary if you want to run
2106 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2107 experimental; if this sounds frightening, say N and sleep in peace.
2108 You can also say M here to compile this support as a module (which
2109 will be called arthur).
2113 menu "Power management options"
2115 source "kernel/power/Kconfig"
2117 config ARCH_SUSPEND_POSSIBLE
2118 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2119 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2122 config ARM_CPU_SUSPEND
2125 config ARCH_HIBERNATION_POSSIBLE
2128 default y if ARCH_SUSPEND_POSSIBLE
2132 source "net/Kconfig"
2134 source "drivers/Kconfig"
2138 source "arch/arm/Kconfig.debug"
2140 source "security/Kconfig"
2142 source "crypto/Kconfig"
2144 source "lib/Kconfig"
2146 source "arch/arm/kvm/Kconfig"