4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_SUPPORTS_UPROBES
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select ARM_HAS_SG_CHAIN
295 select ARM_PATCH_PHYS_VIRT
299 select GENERIC_CLOCKEVENTS
300 select MIGHT_HAVE_PCI
301 select MULTI_IRQ_HANDLER
305 config ARCH_INTEGRATOR
306 bool "ARM Ltd. Integrator family"
308 select ARM_PATCH_PHYS_VIRT
311 select COMMON_CLK_VERSATILE
312 select GENERIC_CLOCKEVENTS
315 select MULTI_IRQ_HANDLER
316 select PLAT_VERSATILE
319 select VERSATILE_FPGA_IRQ
321 Support for ARM's Integrator platform.
324 bool "ARM Ltd. RealView family"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select ARM_TIMER_SP804
329 select COMMON_CLK_VERSATILE
330 select GENERIC_CLOCKEVENTS
331 select GPIO_PL061 if GPIOLIB
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
335 select PLAT_VERSATILE_CLCD
337 This enables support for ARM Ltd RealView boards.
339 config ARCH_VERSATILE
340 bool "ARM Ltd. Versatile family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
347 select HAVE_MACH_CLKDEV
349 select PLAT_VERSATILE
350 select PLAT_VERSATILE_CLCD
351 select PLAT_VERSATILE_CLOCK
352 select VERSATILE_FPGA_IRQ
354 This enables support for ARM Ltd Versatile board.
358 select ARCH_REQUIRE_GPIOLIB
361 select NEED_MACH_IO_H if PCCARD
363 select PINCTRL_AT91 if USE_OF
365 This enables support for systems based on Atmel
366 AT91RM9200 and AT91SAM9* processors.
369 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
370 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
378 Support for Cirrus Logic 711x/721x/731x based boards.
381 bool "Cortina Systems Gemini"
382 select ARCH_REQUIRE_GPIOLIB
385 select GENERIC_CLOCKEVENTS
387 Support for the Cortina Systems Gemini family SoCs
391 select ARCH_USES_GETTIMEOFFSET
394 select NEED_MACH_IO_H
395 select NEED_MACH_MEMORY_H
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
404 bool "Energy Micro efm32"
406 select ARCH_REQUIRE_GPIOLIB
412 select GENERIC_CLOCKEVENTS
418 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H if !MMU
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Hilscher NetX based"
451 select GENERIC_CLOCKEVENTS
453 This enables support for systems based on the Hilscher NetX Soc
459 select NEED_MACH_MEMORY_H
460 select NEED_RET_TO_USER
466 Support for Intel's IOP13XX (XScale) family of processors.
471 select ARCH_REQUIRE_GPIOLIB
474 select NEED_RET_TO_USER
478 Support for Intel's 80219 and IOP32X (XScale) family of
484 select ARCH_REQUIRE_GPIOLIB
487 select NEED_RET_TO_USER
491 Support for Intel's IOP33X (XScale) family of processors.
496 select ARCH_HAS_DMA_SET_COHERENT_MASK
497 select ARCH_REQUIRE_GPIOLIB
498 select ARCH_SUPPORTS_BIG_ENDIAN
501 select DMABOUNCE if PCI
502 select GENERIC_CLOCKEVENTS
503 select MIGHT_HAVE_PCI
504 select NEED_MACH_IO_H
505 select USB_EHCI_BIG_ENDIAN_DESC
506 select USB_EHCI_BIG_ENDIAN_MMIO
508 Support for Intel's IXP4XX (XScale) family of processors.
512 select ARCH_REQUIRE_GPIOLIB
514 select GENERIC_CLOCKEVENTS
515 select MIGHT_HAVE_PCI
519 select PLAT_ORION_LEGACY
521 Support for the Marvell Dove SoC 88AP510
524 bool "Marvell Kirkwood"
525 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
532 select PINCTRL_KIRKWOOD
533 select PLAT_ORION_LEGACY
535 Support for the following Marvell Kirkwood series SoCs:
536 88F6180, 88F6192 and 88F6281.
539 bool "Marvell MV78xx0"
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
545 select PLAT_ORION_LEGACY
547 Support for the following Marvell MV78xx0 series SoCs:
553 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
558 select PLAT_ORION_LEGACY
560 Support for the following Marvell Orion 5x series SoCs:
561 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
562 Orion-2 (5281), Orion-1-90 (6183).
565 bool "Marvell PXA168/910/MMP2"
567 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_ALLOCATOR
570 select GENERIC_CLOCKEVENTS
573 select MULTI_IRQ_HANDLER
578 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
581 bool "Micrel/Kendin KS8695"
582 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_CLOCKEVENTS
586 select NEED_MACH_MEMORY_H
588 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
589 System-on-Chip devices.
592 bool "Nuvoton W90X900 CPU"
593 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
599 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
600 At present, the w90x900 has been renamed nuc900, regarding
601 the ARM series product line, you can login the following
602 link address to know more.
604 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
605 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
609 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
618 Support for the NXP LPC32XX family of processors
621 bool "PXA2xx/PXA3xx-based"
624 select ARCH_REQUIRE_GPIOLIB
625 select ARM_CPU_SUSPEND if PM
629 select GENERIC_CLOCKEVENTS
632 select MULTI_IRQ_HANDLER
636 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
639 bool "Qualcomm MSM (non-multiplatform)"
640 select ARCH_REQUIRE_GPIOLIB
642 select GENERIC_CLOCKEVENTS
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
650 config ARCH_SHMOBILE_LEGACY
651 bool "Renesas ARM SoCs (non-multiplatform)"
653 select ARM_PATCH_PHYS_VIRT
655 select GENERIC_CLOCKEVENTS
656 select HAVE_ARM_SCU if SMP
657 select HAVE_ARM_TWD if SMP
658 select HAVE_MACH_CLKDEV
660 select MIGHT_HAVE_CACHE_L2X0
661 select MULTI_IRQ_HANDLER
664 select PM_GENERIC_DOMAINS if PM
667 Support for Renesas ARM SoC platforms using a non-multiplatform
668 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
674 select ARCH_MAY_HAVE_PC_FDC
675 select ARCH_SPARSEMEM_ENABLE
676 select ARCH_USES_GETTIMEOFFSET
680 select HAVE_PATA_PLATFORM
682 select NEED_MACH_IO_H
683 select NEED_MACH_MEMORY_H
687 On the Acorn Risc-PC, Linux can support the internal IDE disk and
688 CD-ROM interface, serial and parallel port, and the floppy drive.
693 select ARCH_REQUIRE_GPIOLIB
694 select ARCH_SPARSEMEM_ENABLE
699 select GENERIC_CLOCKEVENTS
702 select NEED_MACH_MEMORY_H
705 Support for StrongARM 11x0 based boards.
708 bool "Samsung S3C24XX SoCs"
709 select ARCH_REQUIRE_GPIOLIB
712 select CLKSRC_SAMSUNG_PWM
713 select GENERIC_CLOCKEVENTS
715 select HAVE_S3C2410_I2C if I2C
716 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 select HAVE_S3C_RTC if RTC_CLASS
718 select MULTI_IRQ_HANDLER
719 select NEED_MACH_IO_H
722 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
723 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
724 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
725 Samsung SMDK2410 development board (and derivatives).
728 bool "Samsung S3C64XX"
729 select ARCH_REQUIRE_GPIOLIB
734 select CLKSRC_SAMSUNG_PWM
735 select COMMON_CLK_SAMSUNG
737 select GENERIC_CLOCKEVENTS
739 select HAVE_S3C2410_I2C if I2C
740 select HAVE_S3C2410_WATCHDOG if WATCHDOG
744 select PM_GENERIC_DOMAINS if PM
746 select S3C_GPIO_TRACK
748 select SAMSUNG_WAKEMASK
749 select SAMSUNG_WDT_RESET
751 Samsung S3C64XX series based systems
754 bool "Samsung S5PV210/S5PC110"
755 select ARCH_HAS_HOLES_MEMORYMODEL
756 select ARCH_SPARSEMEM_ENABLE
759 select CLKSRC_SAMSUNG_PWM
761 select GENERIC_CLOCKEVENTS
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select HAVE_S3C_RTC if RTC_CLASS
766 select NEED_MACH_MEMORY_H
769 Samsung S5PV210/S5PC110 series based systems
773 select ARCH_HAS_HOLES_MEMORYMODEL
774 select ARCH_REQUIRE_GPIOLIB
776 select GENERIC_ALLOCATOR
777 select GENERIC_CLOCKEVENTS
778 select GENERIC_IRQ_CHIP
784 Support for TI's DaVinci platform.
789 select ARCH_HAS_HOLES_MEMORYMODEL
791 select ARCH_REQUIRE_GPIOLIB
794 select GENERIC_CLOCKEVENTS
795 select GENERIC_IRQ_CHIP
798 select NEED_MACH_IO_H if PCCARD
799 select NEED_MACH_MEMORY_H
801 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
805 menu "Multiple platform selection"
806 depends on ARCH_MULTIPLATFORM
808 comment "CPU Core family selection"
811 bool "ARMv4 based platforms (FA526)"
812 depends on !ARCH_MULTI_V6_V7
813 select ARCH_MULTI_V4_V5
816 config ARCH_MULTI_V4T
817 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
818 depends on !ARCH_MULTI_V6_V7
819 select ARCH_MULTI_V4_V5
820 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
821 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
822 CPU_ARM925T || CPU_ARM940T)
825 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
826 depends on !ARCH_MULTI_V6_V7
827 select ARCH_MULTI_V4_V5
828 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
829 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
830 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
832 config ARCH_MULTI_V4_V5
836 bool "ARMv6 based platforms (ARM11)"
837 select ARCH_MULTI_V6_V7
841 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
843 select ARCH_MULTI_V6_V7
847 config ARCH_MULTI_V6_V7
849 select MIGHT_HAVE_CACHE_L2X0
851 config ARCH_MULTI_CPU_AUTO
852 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
858 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
862 select HAVE_ARM_ARCH_TIMER
865 # This is sorted alphabetically by mach-* pathname. However, plat-*
866 # Kconfigs may be included either alphabetically (according to the
867 # plat- suffix) or along side the corresponding mach-* source.
869 source "arch/arm/mach-mvebu/Kconfig"
871 source "arch/arm/mach-at91/Kconfig"
873 source "arch/arm/mach-axxia/Kconfig"
875 source "arch/arm/mach-bcm/Kconfig"
877 source "arch/arm/mach-berlin/Kconfig"
879 source "arch/arm/mach-clps711x/Kconfig"
881 source "arch/arm/mach-cns3xxx/Kconfig"
883 source "arch/arm/mach-davinci/Kconfig"
885 source "arch/arm/mach-dove/Kconfig"
887 source "arch/arm/mach-ep93xx/Kconfig"
889 source "arch/arm/mach-footbridge/Kconfig"
891 source "arch/arm/mach-gemini/Kconfig"
893 source "arch/arm/mach-highbank/Kconfig"
895 source "arch/arm/mach-hisi/Kconfig"
897 source "arch/arm/mach-integrator/Kconfig"
899 source "arch/arm/mach-iop32x/Kconfig"
901 source "arch/arm/mach-iop33x/Kconfig"
903 source "arch/arm/mach-iop13xx/Kconfig"
905 source "arch/arm/mach-ixp4xx/Kconfig"
907 source "arch/arm/mach-keystone/Kconfig"
909 source "arch/arm/mach-kirkwood/Kconfig"
911 source "arch/arm/mach-ks8695/Kconfig"
913 source "arch/arm/mach-msm/Kconfig"
915 source "arch/arm/mach-moxart/Kconfig"
917 source "arch/arm/mach-mv78xx0/Kconfig"
919 source "arch/arm/mach-imx/Kconfig"
921 source "arch/arm/mach-mxs/Kconfig"
923 source "arch/arm/mach-netx/Kconfig"
925 source "arch/arm/mach-nomadik/Kconfig"
927 source "arch/arm/mach-nspire/Kconfig"
929 source "arch/arm/plat-omap/Kconfig"
931 source "arch/arm/mach-omap1/Kconfig"
933 source "arch/arm/mach-omap2/Kconfig"
935 source "arch/arm/mach-orion5x/Kconfig"
937 source "arch/arm/mach-picoxcell/Kconfig"
939 source "arch/arm/mach-pxa/Kconfig"
940 source "arch/arm/plat-pxa/Kconfig"
942 source "arch/arm/mach-mmp/Kconfig"
944 source "arch/arm/mach-qcom/Kconfig"
946 source "arch/arm/mach-realview/Kconfig"
948 source "arch/arm/mach-rockchip/Kconfig"
950 source "arch/arm/mach-sa1100/Kconfig"
952 source "arch/arm/mach-socfpga/Kconfig"
954 source "arch/arm/mach-spear/Kconfig"
956 source "arch/arm/mach-sti/Kconfig"
958 source "arch/arm/mach-s3c24xx/Kconfig"
960 source "arch/arm/mach-s3c64xx/Kconfig"
962 source "arch/arm/mach-s5pv210/Kconfig"
964 source "arch/arm/mach-exynos/Kconfig"
965 source "arch/arm/plat-samsung/Kconfig"
967 source "arch/arm/mach-shmobile/Kconfig"
969 source "arch/arm/mach-sunxi/Kconfig"
971 source "arch/arm/mach-prima2/Kconfig"
973 source "arch/arm/mach-tegra/Kconfig"
975 source "arch/arm/mach-u300/Kconfig"
977 source "arch/arm/mach-ux500/Kconfig"
979 source "arch/arm/mach-versatile/Kconfig"
981 source "arch/arm/mach-vexpress/Kconfig"
982 source "arch/arm/plat-versatile/Kconfig"
984 source "arch/arm/mach-vt8500/Kconfig"
986 source "arch/arm/mach-w90x900/Kconfig"
988 source "arch/arm/mach-zynq/Kconfig"
990 # Definitions to make life easier
996 select GENERIC_CLOCKEVENTS
1002 select GENERIC_IRQ_CHIP
1005 config PLAT_ORION_LEGACY
1012 config PLAT_VERSATILE
1015 config ARM_TIMER_SP804
1018 select CLKSRC_OF if OF
1020 source "arch/arm/firmware/Kconfig"
1022 source arch/arm/mm/Kconfig
1025 bool "Enable iWMMXt support"
1026 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1027 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1029 Enable support for iWMMXt context switching at run time if
1030 running on a CPU that supports it.
1032 config MULTI_IRQ_HANDLER
1035 Allow each machine to specify it's own IRQ handler at run time.
1038 source "arch/arm/Kconfig-nommu"
1041 config PJ4B_ERRATA_4742
1042 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1043 depends on CPU_PJ4B && MACH_ARMADA_370
1046 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1047 Event (WFE) IDLE states, a specific timing sensitivity exists between
1048 the retiring WFI/WFE instructions and the newly issued subsequent
1049 instructions. This sensitivity can result in a CPU hang scenario.
1051 The software must insert either a Data Synchronization Barrier (DSB)
1052 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1055 config ARM_ERRATA_326103
1056 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1059 Executing a SWP instruction to read-only memory does not set bit 11
1060 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1061 treat the access as a read, preventing a COW from occurring and
1062 causing the faulting task to livelock.
1064 config ARM_ERRATA_411920
1065 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1066 depends on CPU_V6 || CPU_V6K
1068 Invalidation of the Instruction Cache operation can
1069 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1070 It does not affect the MPCore. This option enables the ARM Ltd.
1071 recommended workaround.
1073 config ARM_ERRATA_430973
1074 bool "ARM errata: Stale prediction on replaced interworking branch"
1077 This option enables the workaround for the 430973 Cortex-A8
1078 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1079 interworking branch is replaced with another code sequence at the
1080 same virtual address, whether due to self-modifying code or virtual
1081 to physical address re-mapping, Cortex-A8 does not recover from the
1082 stale interworking branch prediction. This results in Cortex-A8
1083 executing the new code sequence in the incorrect ARM or Thumb state.
1084 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1085 and also flushes the branch target cache at every context switch.
1086 Note that setting specific bits in the ACTLR register may not be
1087 available in non-secure mode.
1089 config ARM_ERRATA_458693
1090 bool "ARM errata: Processor deadlock when a false hazard is created"
1092 depends on !ARCH_MULTIPLATFORM
1094 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1095 erratum. For very specific sequences of memory operations, it is
1096 possible for a hazard condition intended for a cache line to instead
1097 be incorrectly associated with a different cache line. This false
1098 hazard might then cause a processor deadlock. The workaround enables
1099 the L1 caching of the NEON accesses and disables the PLD instruction
1100 in the ACTLR register. Note that setting specific bits in the ACTLR
1101 register may not be available in non-secure mode.
1103 config ARM_ERRATA_460075
1104 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1106 depends on !ARCH_MULTIPLATFORM
1108 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1109 erratum. Any asynchronous access to the L2 cache may encounter a
1110 situation in which recent store transactions to the L2 cache are lost
1111 and overwritten with stale memory contents from external memory. The
1112 workaround disables the write-allocate mode for the L2 cache via the
1113 ACTLR register. Note that setting specific bits in the ACTLR register
1114 may not be available in non-secure mode.
1116 config ARM_ERRATA_742230
1117 bool "ARM errata: DMB operation may be faulty"
1118 depends on CPU_V7 && SMP
1119 depends on !ARCH_MULTIPLATFORM
1121 This option enables the workaround for the 742230 Cortex-A9
1122 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1123 between two write operations may not ensure the correct visibility
1124 ordering of the two writes. This workaround sets a specific bit in
1125 the diagnostic register of the Cortex-A9 which causes the DMB
1126 instruction to behave as a DSB, ensuring the correct behaviour of
1129 config ARM_ERRATA_742231
1130 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1131 depends on CPU_V7 && SMP
1132 depends on !ARCH_MULTIPLATFORM
1134 This option enables the workaround for the 742231 Cortex-A9
1135 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1136 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1137 accessing some data located in the same cache line, may get corrupted
1138 data due to bad handling of the address hazard when the line gets
1139 replaced from one of the CPUs at the same time as another CPU is
1140 accessing it. This workaround sets specific bits in the diagnostic
1141 register of the Cortex-A9 which reduces the linefill issuing
1142 capabilities of the processor.
1144 config ARM_ERRATA_643719
1145 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1146 depends on CPU_V7 && SMP
1148 This option enables the workaround for the 643719 Cortex-A9 (prior to
1149 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1150 register returns zero when it should return one. The workaround
1151 corrects this value, ensuring cache maintenance operations which use
1152 it behave as intended and avoiding data corruption.
1154 config ARM_ERRATA_720789
1155 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1158 This option enables the workaround for the 720789 Cortex-A9 (prior to
1159 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1160 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1161 As a consequence of this erratum, some TLB entries which should be
1162 invalidated are not, resulting in an incoherency in the system page
1163 tables. The workaround changes the TLB flushing routines to invalidate
1164 entries regardless of the ASID.
1166 config ARM_ERRATA_743622
1167 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 743622 Cortex-A9
1172 (r2p*) erratum. Under very rare conditions, a faulty
1173 optimisation in the Cortex-A9 Store Buffer may lead to data
1174 corruption. This workaround sets a specific bit in the diagnostic
1175 register of the Cortex-A9 which disables the Store Buffer
1176 optimisation, preventing the defect from occurring. This has no
1177 visible impact on the overall performance or power consumption of the
1180 config ARM_ERRATA_751472
1181 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1183 depends on !ARCH_MULTIPLATFORM
1185 This option enables the workaround for the 751472 Cortex-A9 (prior
1186 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1187 completion of a following broadcasted operation if the second
1188 operation is received by a CPU before the ICIALLUIS has completed,
1189 potentially leading to corrupted entries in the cache or TLB.
1191 config ARM_ERRATA_754322
1192 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1195 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1196 r3p*) erratum. A speculative memory access may cause a page table walk
1197 which starts prior to an ASID switch but completes afterwards. This
1198 can populate the micro-TLB with a stale entry which may be hit with
1199 the new ASID. This workaround places two dsb instructions in the mm
1200 switching code so that no page table walks can cross the ASID switch.
1202 config ARM_ERRATA_754327
1203 bool "ARM errata: no automatic Store Buffer drain"
1204 depends on CPU_V7 && SMP
1206 This option enables the workaround for the 754327 Cortex-A9 (prior to
1207 r2p0) erratum. The Store Buffer does not have any automatic draining
1208 mechanism and therefore a livelock may occur if an external agent
1209 continuously polls a memory location waiting to observe an update.
1210 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1211 written polling loops from denying visibility of updates to memory.
1213 config ARM_ERRATA_364296
1214 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1217 This options enables the workaround for the 364296 ARM1136
1218 r0p2 erratum (possible cache data corruption with
1219 hit-under-miss enabled). It sets the undocumented bit 31 in
1220 the auxiliary control register and the FI bit in the control
1221 register, thus disabling hit-under-miss without putting the
1222 processor into full low interrupt latency mode. ARM11MPCore
1225 config ARM_ERRATA_764369
1226 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for erratum 764369
1230 affecting Cortex-A9 MPCore with two or more processors (all
1231 current revisions). Under certain timing circumstances, a data
1232 cache line maintenance operation by MVA targeting an Inner
1233 Shareable memory region may fail to proceed up to either the
1234 Point of Coherency or to the Point of Unification of the
1235 system. This workaround adds a DSB instruction before the
1236 relevant cache maintenance functions and sets a specific bit
1237 in the diagnostic control register of the SCU.
1239 config ARM_ERRATA_775420
1240 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1243 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1244 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1245 operation aborts with MMU exception, it might cause the processor
1246 to deadlock. This workaround puts DSB before executing ISB if
1247 an abort may occur on cache maintenance.
1249 config ARM_ERRATA_798181
1250 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1251 depends on CPU_V7 && SMP
1253 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1254 adequately shooting down all use of the old entries. This
1255 option enables the Linux kernel workaround for this erratum
1256 which sends an IPI to the CPUs that are running the same ASID
1257 as the one being invalidated.
1259 config ARM_ERRATA_773022
1260 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1263 This option enables the workaround for the 773022 Cortex-A15
1264 (up to r0p4) erratum. In certain rare sequences of code, the
1265 loop buffer may deliver incorrect instructions. This
1266 workaround disables the loop buffer to avoid the erratum.
1270 source "arch/arm/common/Kconfig"
1280 Find out whether you have ISA slots on your motherboard. ISA is the
1281 name of a bus system, i.e. the way the CPU talks to the other stuff
1282 inside your box. Other bus systems are PCI, EISA, MicroChannel
1283 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1284 newer boards don't support it. If you have ISA, say Y, otherwise N.
1286 # Select ISA DMA controller support
1291 # Select ISA DMA interface
1296 bool "PCI support" if MIGHT_HAVE_PCI
1298 Find out whether you have a PCI motherboard. PCI is the name of a
1299 bus system, i.e. the way the CPU talks to the other stuff inside
1300 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1301 VESA. If you have PCI, say Y, otherwise N.
1307 config PCI_NANOENGINE
1308 bool "BSE nanoEngine PCI support"
1309 depends on SA1100_NANOENGINE
1311 Enable PCI on the BSE nanoEngine board.
1316 config PCI_HOST_ITE8152
1318 depends on PCI && MACH_ARMCORE
1322 source "drivers/pci/Kconfig"
1323 source "drivers/pci/pcie/Kconfig"
1325 source "drivers/pcmcia/Kconfig"
1329 menu "Kernel Features"
1334 This option should be selected by machines which have an SMP-
1337 The only effect of this option is to make the SMP-related
1338 options available to the user for configuration.
1341 bool "Symmetric Multi-Processing"
1342 depends on CPU_V6K || CPU_V7
1343 depends on GENERIC_CLOCKEVENTS
1345 depends on MMU || ARM_MPU
1347 This enables support for systems with more than one CPU. If you have
1348 a system with only one CPU, say N. If you have a system with more
1349 than one CPU, say Y.
1351 If you say N here, the kernel will run on uni- and multiprocessor
1352 machines, but will use only one CPU of a multiprocessor machine. If
1353 you say Y here, the kernel will run on many, but not all,
1354 uniprocessor machines. On a uniprocessor machine, the kernel
1355 will run faster if you say N here.
1357 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1358 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1359 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1361 If you don't know what to do here, say N.
1364 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1365 depends on SMP && !XIP_KERNEL && MMU
1368 SMP kernels contain instructions which fail on non-SMP processors.
1369 Enabling this option allows the kernel to modify itself to make
1370 these instructions safe. Disabling it allows about 1K of space
1373 If you don't know what to do here, say Y.
1375 config ARM_CPU_TOPOLOGY
1376 bool "Support cpu topology definition"
1377 depends on SMP && CPU_V7
1380 Support ARM cpu topology definition. The MPIDR register defines
1381 affinity between processors which is then used to describe the cpu
1382 topology of an ARM System.
1385 bool "Multi-core scheduler support"
1386 depends on ARM_CPU_TOPOLOGY
1388 Multi-core scheduler support improves the CPU scheduler's decision
1389 making when dealing with multi-core CPU chips at a cost of slightly
1390 increased overhead in some places. If unsure say N here.
1393 bool "SMT scheduler support"
1394 depends on ARM_CPU_TOPOLOGY
1396 Improves the CPU scheduler's decision making when dealing with
1397 MultiThreading at a cost of slightly increased overhead in some
1398 places. If unsure say N here.
1403 This option enables support for the ARM system coherency unit
1405 config HAVE_ARM_ARCH_TIMER
1406 bool "Architected timer support"
1408 select ARM_ARCH_TIMER
1409 select GENERIC_CLOCKEVENTS
1411 This option enables support for the ARM architected timer
1416 select CLKSRC_OF if OF
1418 This options enables support for the ARM timer and watchdog unit
1421 bool "Multi-Cluster Power Management"
1422 depends on CPU_V7 && SMP
1424 This option provides the common power management infrastructure
1425 for (multi-)cluster based systems, such as big.LITTLE based
1429 bool "big.LITTLE support (Experimental)"
1430 depends on CPU_V7 && SMP
1433 This option enables support selections for the big.LITTLE
1434 system architecture.
1437 bool "big.LITTLE switcher support"
1438 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1439 select ARM_CPU_SUSPEND
1442 The big.LITTLE "switcher" provides the core functionality to
1443 transparently handle transition between a cluster of A15's
1444 and a cluster of A7's in a big.LITTLE system.
1446 config BL_SWITCHER_DUMMY_IF
1447 tristate "Simple big.LITTLE switcher user interface"
1448 depends on BL_SWITCHER && DEBUG_KERNEL
1450 This is a simple and dummy char dev interface to control
1451 the big.LITTLE switcher core code. It is meant for
1452 debugging purposes only.
1455 prompt "Memory split"
1459 Select the desired split between kernel and user memory.
1461 If you are not absolutely sure what you are doing, leave this
1465 bool "3G/1G user/kernel split"
1467 bool "2G/2G user/kernel split"
1469 bool "1G/3G user/kernel split"
1474 default PHYS_OFFSET if !MMU
1475 default 0x40000000 if VMSPLIT_1G
1476 default 0x80000000 if VMSPLIT_2G
1480 int "Maximum number of CPUs (2-32)"
1486 bool "Support for hot-pluggable CPUs"
1489 Say Y here to experiment with turning CPUs off and on. CPUs
1490 can be controlled through /sys/devices/system/cpu.
1493 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1496 Say Y here if you want Linux to communicate with system firmware
1497 implementing the PSCI specification for CPU-centric power
1498 management operations described in ARM document number ARM DEN
1499 0022A ("Power State Coordination Interface System Software on
1502 # The GPIO number here must be sorted by descending number. In case of
1503 # a multiplatform kernel, we just want the highest value required by the
1504 # selected platforms.
1507 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1508 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1509 default 416 if ARCH_SUNXI
1510 default 392 if ARCH_U8500
1511 default 352 if ARCH_VT8500
1512 default 264 if MACH_H4700
1515 Maximum number of GPIOs in the system.
1517 If unsure, leave the default value.
1519 source kernel/Kconfig.preempt
1523 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1524 ARCH_S5PV210 || ARCH_EXYNOS4
1525 default AT91_TIMER_HZ if ARCH_AT91
1526 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1530 depends on HZ_FIXED = 0
1531 prompt "Timer frequency"
1555 default HZ_FIXED if HZ_FIXED != 0
1556 default 100 if HZ_100
1557 default 200 if HZ_200
1558 default 250 if HZ_250
1559 default 300 if HZ_300
1560 default 500 if HZ_500
1564 def_bool HIGH_RES_TIMERS
1566 config THUMB2_KERNEL
1567 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1568 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1569 default y if CPU_THUMBONLY
1571 select ARM_ASM_UNIFIED
1574 By enabling this option, the kernel will be compiled in
1575 Thumb-2 mode. A compiler/assembler that understand the unified
1576 ARM-Thumb syntax is needed.
1580 config THUMB2_AVOID_R_ARM_THM_JUMP11
1581 bool "Work around buggy Thumb-2 short branch relocations in gas"
1582 depends on THUMB2_KERNEL && MODULES
1585 Various binutils versions can resolve Thumb-2 branches to
1586 locally-defined, preemptible global symbols as short-range "b.n"
1587 branch instructions.
1589 This is a problem, because there's no guarantee the final
1590 destination of the symbol, or any candidate locations for a
1591 trampoline, are within range of the branch. For this reason, the
1592 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1593 relocation in modules at all, and it makes little sense to add
1596 The symptom is that the kernel fails with an "unsupported
1597 relocation" error when loading some modules.
1599 Until fixed tools are available, passing
1600 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1601 code which hits this problem, at the cost of a bit of extra runtime
1602 stack usage in some cases.
1604 The problem is described in more detail at:
1605 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1607 Only Thumb-2 kernels are affected.
1609 Unless you are sure your tools don't have this problem, say Y.
1611 config ARM_ASM_UNIFIED
1615 bool "Use the ARM EABI to compile the kernel"
1617 This option allows for the kernel to be compiled using the latest
1618 ARM ABI (aka EABI). This is only useful if you are using a user
1619 space environment that is also compiled with EABI.
1621 Since there are major incompatibilities between the legacy ABI and
1622 EABI, especially with regard to structure member alignment, this
1623 option also changes the kernel syscall calling convention to
1624 disambiguate both ABIs and allow for backward compatibility support
1625 (selected with CONFIG_OABI_COMPAT).
1627 To use this you need GCC version 4.0.0 or later.
1630 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1631 depends on AEABI && !THUMB2_KERNEL
1633 This option preserves the old syscall interface along with the
1634 new (ARM EABI) one. It also provides a compatibility layer to
1635 intercept syscalls that have structure arguments which layout
1636 in memory differs between the legacy ABI and the new ARM EABI
1637 (only for non "thumb" binaries). This option adds a tiny
1638 overhead to all syscalls and produces a slightly larger kernel.
1640 The seccomp filter system will not be available when this is
1641 selected, since there is no way yet to sensibly distinguish
1642 between calling conventions during filtering.
1644 If you know you'll be using only pure EABI user space then you
1645 can say N here. If this option is not selected and you attempt
1646 to execute a legacy ABI binary then the result will be
1647 UNPREDICTABLE (in fact it can be predicted that it won't work
1648 at all). If in doubt say N.
1650 config ARCH_HAS_HOLES_MEMORYMODEL
1653 config ARCH_SPARSEMEM_ENABLE
1656 config ARCH_SPARSEMEM_DEFAULT
1657 def_bool ARCH_SPARSEMEM_ENABLE
1659 config ARCH_SELECT_MEMORY_MODEL
1660 def_bool ARCH_SPARSEMEM_ENABLE
1662 config HAVE_ARCH_PFN_VALID
1663 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1666 bool "High Memory Support"
1669 The address space of ARM processors is only 4 Gigabytes large
1670 and it has to accommodate user address space, kernel address
1671 space as well as some memory mapped IO. That means that, if you
1672 have a large amount of physical memory and/or IO, not all of the
1673 memory can be "permanently mapped" by the kernel. The physical
1674 memory that is not permanently mapped is called "high memory".
1676 Depending on the selected kernel/user memory split, minimum
1677 vmalloc space and actual amount of RAM, you may not need this
1678 option which should result in a slightly faster kernel.
1683 bool "Allocate 2nd-level pagetables from highmem"
1686 config HW_PERF_EVENTS
1687 bool "Enable hardware performance counter support for perf events"
1688 depends on PERF_EVENTS
1691 Enable hardware performance counter support for perf events. If
1692 disabled, perf events will use software events only.
1694 config SYS_SUPPORTS_HUGETLBFS
1698 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1702 config ARCH_WANT_GENERAL_HUGETLB
1707 config FORCE_MAX_ZONEORDER
1708 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1709 range 11 64 if ARCH_SHMOBILE_LEGACY
1710 default "12" if SOC_AM33XX
1711 default "9" if SA1111 || ARCH_EFM32
1714 The kernel memory allocator divides physically contiguous memory
1715 blocks into "zones", where each zone is a power of two number of
1716 pages. This option selects the largest power of two that the kernel
1717 keeps in the memory allocator. If you need to allocate very large
1718 blocks of physically contiguous memory, then you may need to
1719 increase this value.
1721 This config option is actually maximum order plus one. For example,
1722 a value of 11 means that the largest free memory block is 2^10 pages.
1724 config ALIGNMENT_TRAP
1726 depends on CPU_CP15_MMU
1727 default y if !ARCH_EBSA110
1728 select HAVE_PROC_CPU if PROC_FS
1730 ARM processors cannot fetch/store information which is not
1731 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1732 address divisible by 4. On 32-bit ARM processors, these non-aligned
1733 fetch/store instructions will be emulated in software if you say
1734 here, which has a severe performance impact. This is necessary for
1735 correct operation of some network protocols. With an IP-only
1736 configuration it is safe to say N, otherwise say Y.
1738 config UACCESS_WITH_MEMCPY
1739 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1741 default y if CPU_FEROCEON
1743 Implement faster copy_to_user and clear_user methods for CPU
1744 cores where a 8-word STM instruction give significantly higher
1745 memory write throughput than a sequence of individual 32bit stores.
1747 A possible side effect is a slight increase in scheduling latency
1748 between threads sharing the same address space if they invoke
1749 such copy operations with large buffers.
1751 However, if the CPU data cache is using a write-allocate mode,
1752 this option is unlikely to provide any performance gain.
1756 prompt "Enable seccomp to safely compute untrusted bytecode"
1758 This kernel feature is useful for number crunching applications
1759 that may need to compute untrusted bytecode during their
1760 execution. By using pipes or other transports made available to
1761 the process as file descriptors supporting the read/write
1762 syscalls, it's possible to isolate those applications in
1763 their own address space using seccomp. Once seccomp is
1764 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1765 and the task is only allowed to execute a few safe syscalls
1766 defined by each seccomp mode.
1779 bool "Xen guest support on ARM (EXPERIMENTAL)"
1780 depends on ARM && AEABI && OF
1781 depends on CPU_V7 && !CPU_V6
1782 depends on !GENERIC_ATOMIC64
1784 select ARCH_DMA_ADDR_T_64BIT
1788 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1795 bool "Flattened Device Tree support"
1798 select OF_EARLY_FLATTREE
1799 select OF_RESERVED_MEM
1801 Include support for flattened device tree machine descriptions.
1804 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1807 This is the traditional way of passing data to the kernel at boot
1808 time. If you are solely relying on the flattened device tree (or
1809 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1810 to remove ATAGS support from your kernel binary. If unsure,
1813 config DEPRECATED_PARAM_STRUCT
1814 bool "Provide old way to pass kernel parameters"
1817 This was deprecated in 2001 and announced to live on for 5 years.
1818 Some old boot loaders still use this way.
1820 # Compressed boot loader in ROM. Yes, we really want to ask about
1821 # TEXT and BSS so we preserve their values in the config files.
1822 config ZBOOT_ROM_TEXT
1823 hex "Compressed ROM boot loader base address"
1826 The physical address at which the ROM-able zImage is to be
1827 placed in the target. Platforms which normally make use of
1828 ROM-able zImage formats normally set this to a suitable
1829 value in their defconfig file.
1831 If ZBOOT_ROM is not enabled, this has no effect.
1833 config ZBOOT_ROM_BSS
1834 hex "Compressed ROM boot loader BSS address"
1837 The base address of an area of read/write memory in the target
1838 for the ROM-able zImage which must be available while the
1839 decompressor is running. It must be large enough to hold the
1840 entire decompressed kernel plus an additional 128 KiB.
1841 Platforms which normally make use of ROM-able zImage formats
1842 normally set this to a suitable value in their defconfig file.
1844 If ZBOOT_ROM is not enabled, this has no effect.
1847 bool "Compressed boot loader in ROM/flash"
1848 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1849 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1851 Say Y here if you intend to execute your compressed kernel image
1852 (zImage) directly from ROM or flash. If unsure, say N.
1855 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1856 depends on ZBOOT_ROM && ARCH_SH7372
1857 default ZBOOT_ROM_NONE
1859 Include experimental SD/MMC loading code in the ROM-able zImage.
1860 With this enabled it is possible to write the ROM-able zImage
1861 kernel image to an MMC or SD card and boot the kernel straight
1862 from the reset vector. At reset the processor Mask ROM will load
1863 the first part of the ROM-able zImage which in turn loads the
1864 rest the kernel image to RAM.
1866 config ZBOOT_ROM_NONE
1867 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1869 Do not load image from SD or MMC
1871 config ZBOOT_ROM_MMCIF
1872 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1874 Load image from MMCIF hardware block.
1876 config ZBOOT_ROM_SH_MOBILE_SDHI
1877 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1879 Load image from SDHI hardware block
1883 config ARM_APPENDED_DTB
1884 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1887 With this option, the boot code will look for a device tree binary
1888 (DTB) appended to zImage
1889 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1891 This is meant as a backward compatibility convenience for those
1892 systems with a bootloader that can't be upgraded to accommodate
1893 the documented boot protocol using a device tree.
1895 Beware that there is very little in terms of protection against
1896 this option being confused by leftover garbage in memory that might
1897 look like a DTB header after a reboot if no actual DTB is appended
1898 to zImage. Do not leave this option active in a production kernel
1899 if you don't intend to always append a DTB. Proper passing of the
1900 location into r2 of a bootloader provided DTB is always preferable
1903 config ARM_ATAG_DTB_COMPAT
1904 bool "Supplement the appended DTB with traditional ATAG information"
1905 depends on ARM_APPENDED_DTB
1907 Some old bootloaders can't be updated to a DTB capable one, yet
1908 they provide ATAGs with memory configuration, the ramdisk address,
1909 the kernel cmdline string, etc. Such information is dynamically
1910 provided by the bootloader and can't always be stored in a static
1911 DTB. To allow a device tree enabled kernel to be used with such
1912 bootloaders, this option allows zImage to extract the information
1913 from the ATAG list and store it at run time into the appended DTB.
1916 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1917 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 bool "Use bootloader kernel arguments if available"
1922 Uses the command-line options passed by the boot loader instead of
1923 the device tree bootargs property. If the boot loader doesn't provide
1924 any, the device tree bootargs property will be used.
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1927 bool "Extend with bootloader kernel arguments"
1929 The command-line arguments provided by the boot loader will be
1930 appended to the the device tree bootargs property.
1935 string "Default kernel command string"
1938 On some architectures (EBSA110 and CATS), there is currently no way
1939 for the boot loader to pass arguments to the kernel. For these
1940 architectures, you should supply some command-line options at build
1941 time by entering them here. As a minimum, you should specify the
1942 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945 prompt "Kernel command line type" if CMDLINE != ""
1946 default CMDLINE_FROM_BOOTLOADER
1949 config CMDLINE_FROM_BOOTLOADER
1950 bool "Use bootloader kernel arguments if available"
1952 Uses the command-line options passed by the boot loader. If
1953 the boot loader doesn't provide any, the default kernel command
1954 string provided in CMDLINE will be used.
1956 config CMDLINE_EXTEND
1957 bool "Extend bootloader kernel arguments"
1959 The command-line arguments provided by the boot loader will be
1960 appended to the default kernel command string.
1962 config CMDLINE_FORCE
1963 bool "Always use the default kernel command string"
1965 Always use the default kernel command string, even if the boot
1966 loader passes other arguments to the kernel.
1967 This is useful if you cannot or don't want to change the
1968 command-line options your boot loader passes to the kernel.
1972 bool "Kernel Execute-In-Place from ROM"
1973 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1975 Execute-In-Place allows the kernel to run from non-volatile storage
1976 directly addressable by the CPU, such as NOR flash. This saves RAM
1977 space since the text section of the kernel is not loaded from flash
1978 to RAM. Read-write sections, such as the data section and stack,
1979 are still copied to RAM. The XIP kernel is not compressed since
1980 it has to run directly from flash, so it will take more space to
1981 store it. The flash address used to link the kernel object files,
1982 and for storing it, is configuration dependent. Therefore, if you
1983 say Y here, you must know the proper physical address where to
1984 store the kernel image depending on your own flash memory usage.
1986 Also note that the make target becomes "make xipImage" rather than
1987 "make zImage" or "make Image". The final kernel binary to put in
1988 ROM memory will be arch/arm/boot/xipImage.
1992 config XIP_PHYS_ADDR
1993 hex "XIP Kernel Physical Location"
1994 depends on XIP_KERNEL
1995 default "0x00080000"
1997 This is the physical address in your flash memory the kernel will
1998 be linked for and stored to. This address is dependent on your
2002 bool "Kexec system call (EXPERIMENTAL)"
2003 depends on (!SMP || PM_SLEEP_SMP)
2005 kexec is a system call that implements the ability to shutdown your
2006 current kernel, and to start another kernel. It is like a reboot
2007 but it is independent of the system firmware. And like a reboot
2008 you can start any kernel with it, not just Linux.
2010 It is an ongoing process to be certain the hardware in a machine
2011 is properly shutdown, so do not be surprised if this code does not
2012 initially work for you.
2015 bool "Export atags in procfs"
2016 depends on ATAGS && KEXEC
2019 Should the atags used to boot the kernel be exported in an "atags"
2020 file in procfs. Useful with kexec.
2023 bool "Build kdump crash kernel (EXPERIMENTAL)"
2025 Generate crash dump after being started by kexec. This should
2026 be normally only set in special crash dump kernels which are
2027 loaded in the main kernel with kexec-tools into a specially
2028 reserved region and then later executed after a crash by
2029 kdump/kexec. The crash dump kernel must be compiled to a
2030 memory address not used by the main kernel
2032 For more details see Documentation/kdump/kdump.txt
2034 config AUTO_ZRELADDR
2035 bool "Auto calculation of the decompressed kernel image address"
2037 ZRELADDR is the physical address where the decompressed kernel
2038 image will be placed. If AUTO_ZRELADDR is selected, the address
2039 will be determined at run-time by masking the current IP with
2040 0xf8000000. This assumes the zImage being placed in the first 128MB
2041 from start of memory.
2045 menu "CPU Power Management"
2047 source "drivers/cpufreq/Kconfig"
2049 source "drivers/cpuidle/Kconfig"
2053 menu "Floating point emulation"
2055 comment "At least one emulation must be selected"
2058 bool "NWFPE math emulation"
2059 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2061 Say Y to include the NWFPE floating point emulator in the kernel.
2062 This is necessary to run most binaries. Linux does not currently
2063 support floating point hardware so you need to say Y here even if
2064 your machine has an FPA or floating point co-processor podule.
2066 You may say N here if you are going to load the Acorn FPEmulator
2067 early in the bootup.
2070 bool "Support extended precision"
2071 depends on FPE_NWFPE
2073 Say Y to include 80-bit support in the kernel floating-point
2074 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2075 Note that gcc does not generate 80-bit operations by default,
2076 so in most cases this option only enlarges the size of the
2077 floating point emulator without any good reason.
2079 You almost surely want to say N here.
2082 bool "FastFPE math emulation (EXPERIMENTAL)"
2083 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2085 Say Y here to include the FAST floating point emulator in the kernel.
2086 This is an experimental much faster emulator which now also has full
2087 precision for the mantissa. It does not support any exceptions.
2088 It is very simple, and approximately 3-6 times faster than NWFPE.
2090 It should be sufficient for most programs. It may be not suitable
2091 for scientific calculations, but you have to check this for yourself.
2092 If you do not feel you need a faster FP emulation you should better
2096 bool "VFP-format floating point maths"
2097 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2099 Say Y to include VFP support code in the kernel. This is needed
2100 if your hardware includes a VFP unit.
2102 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2103 release notes and additional status information.
2105 Say N if your target does not have VFP hardware.
2113 bool "Advanced SIMD (NEON) Extension support"
2114 depends on VFPv3 && CPU_V7
2116 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2119 config KERNEL_MODE_NEON
2120 bool "Support for NEON in kernel mode"
2121 depends on NEON && AEABI
2123 Say Y to include support for NEON in kernel mode.
2127 menu "Userspace binary formats"
2129 source "fs/Kconfig.binfmt"
2132 tristate "RISC OS personality"
2135 Say Y here to include the kernel code necessary if you want to run
2136 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2137 experimental; if this sounds frightening, say N and sleep in peace.
2138 You can also say M here to compile this support as a module (which
2139 will be called arthur).
2143 menu "Power management options"
2145 source "kernel/power/Kconfig"
2147 config ARCH_SUSPEND_POSSIBLE
2148 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2149 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2152 config ARM_CPU_SUSPEND
2155 config ARCH_HIBERNATION_POSSIBLE
2158 default y if ARCH_SUSPEND_POSSIBLE
2162 source "net/Kconfig"
2164 source "drivers/Kconfig"
2168 source "arch/arm/Kconfig.debug"
2170 source "security/Kconfig"
2172 source "crypto/Kconfig"
2174 source "lib/Kconfig"
2176 source "arch/arm/kvm/Kconfig"