4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
86 select ARCH_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_BANDGAP
182 config GENERIC_HWEIGHT
186 config GENERIC_CALIBRATE_DELAY
190 config ARCH_MAY_HAVE_PC_FDC
196 config NEED_DMA_MAP_STATE
199 config ARCH_SUPPORTS_UPROBES
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT
260 default DRAM_BASE if !MMU
261 default 0x00000000 if ARCH_EBSA110 || \
262 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
267 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269 default 0x20000000 if ARCH_S5PV210
270 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
271 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
272 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
273 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
274 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 source "init/Kconfig"
285 source "kernel/Kconfig.freezer"
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
297 # The "ARM system type" choice list is ordered alphabetically by option
298 # text. Please add new entries in the option alphabetic order.
301 prompt "ARM system type"
302 default ARCH_VERSATILE if !MMU
303 default ARCH_MULTIPLATFORM if MMU
305 config ARCH_MULTIPLATFORM
306 bool "Allow multiple platforms to be selected"
308 select ARCH_WANT_OPTIONAL_GPIOLIB
309 select ARM_HAS_SG_CHAIN
310 select ARM_PATCH_PHYS_VIRT
314 select GENERIC_CLOCKEVENTS
315 select MIGHT_HAVE_PCI
316 select MULTI_IRQ_HANDLER
320 config ARCH_INTEGRATOR
321 bool "ARM Ltd. Integrator family"
323 select ARM_PATCH_PHYS_VIRT if MMU
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
330 select MULTI_IRQ_HANDLER
331 select PLAT_VERSATILE
334 select VERSATILE_FPGA_IRQ
336 Support for ARM's Integrator platform.
339 bool "ARM Ltd. RealView family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
344 select COMMON_CLK_VERSATILE
345 select GENERIC_CLOCKEVENTS
346 select GPIO_PL061 if GPIOLIB
348 select NEED_MACH_MEMORY_H
349 select PLAT_VERSATILE
351 This enables support for ARM Ltd RealView boards.
353 config ARCH_VERSATILE
354 bool "ARM Ltd. Versatile family"
355 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_TIMER_SP804
360 select GENERIC_CLOCKEVENTS
361 select HAVE_MACH_CLKDEV
363 select PLAT_VERSATILE
364 select PLAT_VERSATILE_CLOCK
365 select VERSATILE_FPGA_IRQ
367 This enables support for ARM Ltd Versatile board.
371 select ARCH_REQUIRE_GPIOLIB
374 select NEED_MACH_IO_H if PCCARD
376 select PINCTRL_AT91 if USE_OF
378 This enables support for systems based on Atmel
379 AT91RM9200 and AT91SAM9* processors.
382 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
391 Support for Cirrus Logic 711x/721x/731x based boards.
394 bool "Cortina Systems Gemini"
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
400 Support for the Cortina Systems Gemini family SoCs
404 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
417 bool "Energy Micro efm32"
419 select ARCH_REQUIRE_GPIOLIB
425 select GENERIC_CLOCKEVENTS
431 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
436 select ARCH_HAS_HOLES_MEMORYMODEL
437 select ARCH_REQUIRE_GPIOLIB
438 select ARCH_USES_GETTIMEOFFSET
444 This enables support for the Cirrus EP93xx series of CPUs.
446 config ARCH_FOOTBRIDGE
450 select GENERIC_CLOCKEVENTS
452 select NEED_MACH_IO_H if !MMU
453 select NEED_MACH_MEMORY_H
455 Support for systems based on the DC21285 companion chip
456 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
459 bool "Hilscher NetX based"
463 select GENERIC_CLOCKEVENTS
465 This enables support for systems based on the Hilscher NetX Soc
471 select NEED_MACH_MEMORY_H
472 select NEED_RET_TO_USER
478 Support for Intel's IOP13XX (XScale) family of processors.
483 select ARCH_REQUIRE_GPIOLIB
486 select NEED_RET_TO_USER
490 Support for Intel's 80219 and IOP32X (XScale) family of
496 select ARCH_REQUIRE_GPIOLIB
499 select NEED_RET_TO_USER
503 Support for Intel's IOP33X (XScale) family of processors.
508 select ARCH_HAS_DMA_SET_COHERENT_MASK
509 select ARCH_REQUIRE_GPIOLIB
510 select ARCH_SUPPORTS_BIG_ENDIAN
513 select DMABOUNCE if PCI
514 select GENERIC_CLOCKEVENTS
515 select MIGHT_HAVE_PCI
516 select NEED_MACH_IO_H
517 select USB_EHCI_BIG_ENDIAN_DESC
518 select USB_EHCI_BIG_ENDIAN_MMIO
520 Support for Intel's IXP4XX (XScale) family of processors.
524 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
527 select MIGHT_HAVE_PCI
531 select PLAT_ORION_LEGACY
533 Support for the Marvell Dove SoC 88AP510
536 bool "Marvell MV78xx0"
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
542 select PLAT_ORION_LEGACY
544 Support for the following Marvell MV78xx0 series SoCs:
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Orion 5x series SoCs:
558 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
559 Orion-2 (5281), Orion-1-90 (6183).
562 bool "Marvell PXA168/910/MMP2"
564 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_ALLOCATOR
567 select GENERIC_CLOCKEVENTS
570 select MULTI_IRQ_HANDLER
575 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
578 bool "Micrel/Kendin KS8695"
579 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select NEED_MACH_MEMORY_H
585 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
586 System-on-Chip devices.
589 bool "Nuvoton W90X900 CPU"
590 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
596 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
597 At present, the w90x900 has been renamed nuc900, regarding
598 the ARM series product line, you can login the following
599 link address to know more.
601 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
602 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
606 select ARCH_REQUIRE_GPIOLIB
611 select GENERIC_CLOCKEVENTS
615 Support for the NXP LPC32XX family of processors
618 bool "PXA2xx/PXA3xx-based"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
627 select GENERIC_CLOCKEVENTS
630 select MULTI_IRQ_HANDLER
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
637 bool "Qualcomm MSM (non-multiplatform)"
638 select ARCH_REQUIRE_GPIOLIB
640 select GENERIC_CLOCKEVENTS
642 Support for Qualcomm MSM/QSD based systems. This runs on the
643 apps processor of the MSM/QSD and depends on a shared memory
644 interface to the modem processor which runs the baseband
645 stack and controls some vital subsystems
646 (clock and power control, etc).
648 config ARCH_SHMOBILE_LEGACY
649 bool "Renesas ARM SoCs (non-multiplatform)"
651 select ARM_PATCH_PHYS_VIRT if MMU
654 select GENERIC_CLOCKEVENTS
655 select HAVE_ARM_SCU if SMP
656 select HAVE_ARM_TWD if SMP
657 select HAVE_MACH_CLKDEV
659 select MIGHT_HAVE_CACHE_L2X0
660 select MULTI_IRQ_HANDLER
663 select PM_GENERIC_DOMAINS if PM
667 Support for Renesas ARM SoC platforms using a non-multiplatform
668 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
674 select ARCH_MAY_HAVE_PC_FDC
675 select ARCH_SPARSEMEM_ENABLE
676 select ARCH_USES_GETTIMEOFFSET
680 select HAVE_PATA_PLATFORM
682 select NEED_MACH_IO_H
683 select NEED_MACH_MEMORY_H
687 On the Acorn Risc-PC, Linux can support the internal IDE disk and
688 CD-ROM interface, serial and parallel port, and the floppy drive.
693 select ARCH_REQUIRE_GPIOLIB
694 select ARCH_SPARSEMEM_ENABLE
699 select GENERIC_CLOCKEVENTS
702 select NEED_MACH_MEMORY_H
705 Support for StrongARM 11x0 based boards.
708 bool "Samsung S3C24XX SoCs"
709 select ARCH_REQUIRE_GPIOLIB
712 select CLKSRC_SAMSUNG_PWM
713 select GENERIC_CLOCKEVENTS
715 select HAVE_S3C2410_I2C if I2C
716 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 select HAVE_S3C_RTC if RTC_CLASS
718 select MULTI_IRQ_HANDLER
719 select NEED_MACH_IO_H
722 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
723 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
724 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
725 Samsung SMDK2410 development board (and derivatives).
728 bool "Samsung S3C64XX"
729 select ARCH_REQUIRE_GPIOLIB
734 select CLKSRC_SAMSUNG_PWM
735 select COMMON_CLK_SAMSUNG
737 select GENERIC_CLOCKEVENTS
739 select HAVE_S3C2410_I2C if I2C
740 select HAVE_S3C2410_WATCHDOG if WATCHDOG
744 select PM_GENERIC_DOMAINS if PM
746 select S3C_GPIO_TRACK
748 select SAMSUNG_WAKEMASK
749 select SAMSUNG_WDT_RESET
751 Samsung S3C64XX series based systems
755 select ARCH_HAS_HOLES_MEMORYMODEL
756 select ARCH_REQUIRE_GPIOLIB
758 select GENERIC_ALLOCATOR
759 select GENERIC_CLOCKEVENTS
760 select GENERIC_IRQ_CHIP
766 Support for TI's DaVinci platform.
771 select ARCH_HAS_HOLES_MEMORYMODEL
773 select ARCH_REQUIRE_GPIOLIB
776 select GENERIC_CLOCKEVENTS
777 select GENERIC_IRQ_CHIP
780 select NEED_MACH_IO_H if PCCARD
781 select NEED_MACH_MEMORY_H
783 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
787 menu "Multiple platform selection"
788 depends on ARCH_MULTIPLATFORM
790 comment "CPU Core family selection"
793 bool "ARMv4 based platforms (FA526)"
794 depends on !ARCH_MULTI_V6_V7
795 select ARCH_MULTI_V4_V5
798 config ARCH_MULTI_V4T
799 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
800 depends on !ARCH_MULTI_V6_V7
801 select ARCH_MULTI_V4_V5
802 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
803 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
804 CPU_ARM925T || CPU_ARM940T)
807 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
808 depends on !ARCH_MULTI_V6_V7
809 select ARCH_MULTI_V4_V5
810 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
811 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
812 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
814 config ARCH_MULTI_V4_V5
818 bool "ARMv6 based platforms (ARM11)"
819 select ARCH_MULTI_V6_V7
823 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
825 select ARCH_MULTI_V6_V7
829 config ARCH_MULTI_V6_V7
831 select MIGHT_HAVE_CACHE_L2X0
833 config ARCH_MULTI_CPU_AUTO
834 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
840 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
844 select HAVE_ARM_ARCH_TIMER
847 # This is sorted alphabetically by mach-* pathname. However, plat-*
848 # Kconfigs may be included either alphabetically (according to the
849 # plat- suffix) or along side the corresponding mach-* source.
851 source "arch/arm/mach-mvebu/Kconfig"
853 source "arch/arm/mach-at91/Kconfig"
855 source "arch/arm/mach-axxia/Kconfig"
857 source "arch/arm/mach-bcm/Kconfig"
859 source "arch/arm/mach-berlin/Kconfig"
861 source "arch/arm/mach-clps711x/Kconfig"
863 source "arch/arm/mach-cns3xxx/Kconfig"
865 source "arch/arm/mach-davinci/Kconfig"
867 source "arch/arm/mach-dove/Kconfig"
869 source "arch/arm/mach-ep93xx/Kconfig"
871 source "arch/arm/mach-footbridge/Kconfig"
873 source "arch/arm/mach-gemini/Kconfig"
875 source "arch/arm/mach-highbank/Kconfig"
877 source "arch/arm/mach-hisi/Kconfig"
879 source "arch/arm/mach-integrator/Kconfig"
881 source "arch/arm/mach-iop32x/Kconfig"
883 source "arch/arm/mach-iop33x/Kconfig"
885 source "arch/arm/mach-iop13xx/Kconfig"
887 source "arch/arm/mach-ixp4xx/Kconfig"
889 source "arch/arm/mach-keystone/Kconfig"
891 source "arch/arm/mach-ks8695/Kconfig"
893 source "arch/arm/mach-msm/Kconfig"
895 source "arch/arm/mach-moxart/Kconfig"
897 source "arch/arm/mach-mv78xx0/Kconfig"
899 source "arch/arm/mach-imx/Kconfig"
901 source "arch/arm/mach-mediatek/Kconfig"
903 source "arch/arm/mach-mxs/Kconfig"
905 source "arch/arm/mach-netx/Kconfig"
907 source "arch/arm/mach-nomadik/Kconfig"
909 source "arch/arm/mach-nspire/Kconfig"
911 source "arch/arm/plat-omap/Kconfig"
913 source "arch/arm/mach-omap1/Kconfig"
915 source "arch/arm/mach-omap2/Kconfig"
917 source "arch/arm/mach-orion5x/Kconfig"
919 source "arch/arm/mach-picoxcell/Kconfig"
921 source "arch/arm/mach-pxa/Kconfig"
922 source "arch/arm/plat-pxa/Kconfig"
924 source "arch/arm/mach-mmp/Kconfig"
926 source "arch/arm/mach-qcom/Kconfig"
928 source "arch/arm/mach-realview/Kconfig"
930 source "arch/arm/mach-rockchip/Kconfig"
932 source "arch/arm/mach-sa1100/Kconfig"
934 source "arch/arm/mach-socfpga/Kconfig"
936 source "arch/arm/mach-spear/Kconfig"
938 source "arch/arm/mach-sti/Kconfig"
940 source "arch/arm/mach-s3c24xx/Kconfig"
942 source "arch/arm/mach-s3c64xx/Kconfig"
944 source "arch/arm/mach-s5pv210/Kconfig"
946 source "arch/arm/mach-exynos/Kconfig"
947 source "arch/arm/plat-samsung/Kconfig"
949 source "arch/arm/mach-shmobile/Kconfig"
951 source "arch/arm/mach-sunxi/Kconfig"
953 source "arch/arm/mach-prima2/Kconfig"
955 source "arch/arm/mach-tegra/Kconfig"
957 source "arch/arm/mach-u300/Kconfig"
959 source "arch/arm/mach-ux500/Kconfig"
961 source "arch/arm/mach-versatile/Kconfig"
963 source "arch/arm/mach-vexpress/Kconfig"
964 source "arch/arm/plat-versatile/Kconfig"
966 source "arch/arm/mach-vt8500/Kconfig"
968 source "arch/arm/mach-w90x900/Kconfig"
970 source "arch/arm/mach-zynq/Kconfig"
972 # Definitions to make life easier
978 select GENERIC_CLOCKEVENTS
984 select GENERIC_IRQ_CHIP
987 config PLAT_ORION_LEGACY
994 config PLAT_VERSATILE
997 config ARM_TIMER_SP804
1000 select CLKSRC_OF if OF
1002 source "arch/arm/firmware/Kconfig"
1004 source arch/arm/mm/Kconfig
1007 bool "Enable iWMMXt support"
1008 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1009 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1011 Enable support for iWMMXt context switching at run time if
1012 running on a CPU that supports it.
1014 config MULTI_IRQ_HANDLER
1017 Allow each machine to specify it's own IRQ handler at run time.
1020 source "arch/arm/Kconfig-nommu"
1023 config PJ4B_ERRATA_4742
1024 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1025 depends on CPU_PJ4B && MACH_ARMADA_370
1028 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1029 Event (WFE) IDLE states, a specific timing sensitivity exists between
1030 the retiring WFI/WFE instructions and the newly issued subsequent
1031 instructions. This sensitivity can result in a CPU hang scenario.
1033 The software must insert either a Data Synchronization Barrier (DSB)
1034 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1037 config ARM_ERRATA_326103
1038 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1041 Executing a SWP instruction to read-only memory does not set bit 11
1042 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1043 treat the access as a read, preventing a COW from occurring and
1044 causing the faulting task to livelock.
1046 config ARM_ERRATA_411920
1047 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1048 depends on CPU_V6 || CPU_V6K
1050 Invalidation of the Instruction Cache operation can
1051 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1052 It does not affect the MPCore. This option enables the ARM Ltd.
1053 recommended workaround.
1055 config ARM_ERRATA_430973
1056 bool "ARM errata: Stale prediction on replaced interworking branch"
1059 This option enables the workaround for the 430973 Cortex-A8
1060 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1061 interworking branch is replaced with another code sequence at the
1062 same virtual address, whether due to self-modifying code or virtual
1063 to physical address re-mapping, Cortex-A8 does not recover from the
1064 stale interworking branch prediction. This results in Cortex-A8
1065 executing the new code sequence in the incorrect ARM or Thumb state.
1066 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1067 and also flushes the branch target cache at every context switch.
1068 Note that setting specific bits in the ACTLR register may not be
1069 available in non-secure mode.
1071 config ARM_ERRATA_458693
1072 bool "ARM errata: Processor deadlock when a false hazard is created"
1074 depends on !ARCH_MULTIPLATFORM
1076 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1077 erratum. For very specific sequences of memory operations, it is
1078 possible for a hazard condition intended for a cache line to instead
1079 be incorrectly associated with a different cache line. This false
1080 hazard might then cause a processor deadlock. The workaround enables
1081 the L1 caching of the NEON accesses and disables the PLD instruction
1082 in the ACTLR register. Note that setting specific bits in the ACTLR
1083 register may not be available in non-secure mode.
1085 config ARM_ERRATA_460075
1086 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1088 depends on !ARCH_MULTIPLATFORM
1090 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1091 erratum. Any asynchronous access to the L2 cache may encounter a
1092 situation in which recent store transactions to the L2 cache are lost
1093 and overwritten with stale memory contents from external memory. The
1094 workaround disables the write-allocate mode for the L2 cache via the
1095 ACTLR register. Note that setting specific bits in the ACTLR register
1096 may not be available in non-secure mode.
1098 config ARM_ERRATA_742230
1099 bool "ARM errata: DMB operation may be faulty"
1100 depends on CPU_V7 && SMP
1101 depends on !ARCH_MULTIPLATFORM
1103 This option enables the workaround for the 742230 Cortex-A9
1104 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1105 between two write operations may not ensure the correct visibility
1106 ordering of the two writes. This workaround sets a specific bit in
1107 the diagnostic register of the Cortex-A9 which causes the DMB
1108 instruction to behave as a DSB, ensuring the correct behaviour of
1111 config ARM_ERRATA_742231
1112 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1113 depends on CPU_V7 && SMP
1114 depends on !ARCH_MULTIPLATFORM
1116 This option enables the workaround for the 742231 Cortex-A9
1117 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1118 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1119 accessing some data located in the same cache line, may get corrupted
1120 data due to bad handling of the address hazard when the line gets
1121 replaced from one of the CPUs at the same time as another CPU is
1122 accessing it. This workaround sets specific bits in the diagnostic
1123 register of the Cortex-A9 which reduces the linefill issuing
1124 capabilities of the processor.
1126 config ARM_ERRATA_643719
1127 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1128 depends on CPU_V7 && SMP
1130 This option enables the workaround for the 643719 Cortex-A9 (prior to
1131 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1132 register returns zero when it should return one. The workaround
1133 corrects this value, ensuring cache maintenance operations which use
1134 it behave as intended and avoiding data corruption.
1136 config ARM_ERRATA_720789
1137 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1140 This option enables the workaround for the 720789 Cortex-A9 (prior to
1141 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1142 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1143 As a consequence of this erratum, some TLB entries which should be
1144 invalidated are not, resulting in an incoherency in the system page
1145 tables. The workaround changes the TLB flushing routines to invalidate
1146 entries regardless of the ASID.
1148 config ARM_ERRATA_743622
1149 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1151 depends on !ARCH_MULTIPLATFORM
1153 This option enables the workaround for the 743622 Cortex-A9
1154 (r2p*) erratum. Under very rare conditions, a faulty
1155 optimisation in the Cortex-A9 Store Buffer may lead to data
1156 corruption. This workaround sets a specific bit in the diagnostic
1157 register of the Cortex-A9 which disables the Store Buffer
1158 optimisation, preventing the defect from occurring. This has no
1159 visible impact on the overall performance or power consumption of the
1162 config ARM_ERRATA_751472
1163 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1165 depends on !ARCH_MULTIPLATFORM
1167 This option enables the workaround for the 751472 Cortex-A9 (prior
1168 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1169 completion of a following broadcasted operation if the second
1170 operation is received by a CPU before the ICIALLUIS has completed,
1171 potentially leading to corrupted entries in the cache or TLB.
1173 config ARM_ERRATA_754322
1174 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1177 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1178 r3p*) erratum. A speculative memory access may cause a page table walk
1179 which starts prior to an ASID switch but completes afterwards. This
1180 can populate the micro-TLB with a stale entry which may be hit with
1181 the new ASID. This workaround places two dsb instructions in the mm
1182 switching code so that no page table walks can cross the ASID switch.
1184 config ARM_ERRATA_754327
1185 bool "ARM errata: no automatic Store Buffer drain"
1186 depends on CPU_V7 && SMP
1188 This option enables the workaround for the 754327 Cortex-A9 (prior to
1189 r2p0) erratum. The Store Buffer does not have any automatic draining
1190 mechanism and therefore a livelock may occur if an external agent
1191 continuously polls a memory location waiting to observe an update.
1192 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1193 written polling loops from denying visibility of updates to memory.
1195 config ARM_ERRATA_364296
1196 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1199 This options enables the workaround for the 364296 ARM1136
1200 r0p2 erratum (possible cache data corruption with
1201 hit-under-miss enabled). It sets the undocumented bit 31 in
1202 the auxiliary control register and the FI bit in the control
1203 register, thus disabling hit-under-miss without putting the
1204 processor into full low interrupt latency mode. ARM11MPCore
1207 config ARM_ERRATA_764369
1208 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for erratum 764369
1212 affecting Cortex-A9 MPCore with two or more processors (all
1213 current revisions). Under certain timing circumstances, a data
1214 cache line maintenance operation by MVA targeting an Inner
1215 Shareable memory region may fail to proceed up to either the
1216 Point of Coherency or to the Point of Unification of the
1217 system. This workaround adds a DSB instruction before the
1218 relevant cache maintenance functions and sets a specific bit
1219 in the diagnostic control register of the SCU.
1221 config ARM_ERRATA_775420
1222 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1225 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1226 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1227 operation aborts with MMU exception, it might cause the processor
1228 to deadlock. This workaround puts DSB before executing ISB if
1229 an abort may occur on cache maintenance.
1231 config ARM_ERRATA_798181
1232 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1233 depends on CPU_V7 && SMP
1235 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1236 adequately shooting down all use of the old entries. This
1237 option enables the Linux kernel workaround for this erratum
1238 which sends an IPI to the CPUs that are running the same ASID
1239 as the one being invalidated.
1241 config ARM_ERRATA_773022
1242 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1245 This option enables the workaround for the 773022 Cortex-A15
1246 (up to r0p4) erratum. In certain rare sequences of code, the
1247 loop buffer may deliver incorrect instructions. This
1248 workaround disables the loop buffer to avoid the erratum.
1252 source "arch/arm/common/Kconfig"
1262 Find out whether you have ISA slots on your motherboard. ISA is the
1263 name of a bus system, i.e. the way the CPU talks to the other stuff
1264 inside your box. Other bus systems are PCI, EISA, MicroChannel
1265 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1266 newer boards don't support it. If you have ISA, say Y, otherwise N.
1268 # Select ISA DMA controller support
1273 # Select ISA DMA interface
1278 bool "PCI support" if MIGHT_HAVE_PCI
1280 Find out whether you have a PCI motherboard. PCI is the name of a
1281 bus system, i.e. the way the CPU talks to the other stuff inside
1282 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1283 VESA. If you have PCI, say Y, otherwise N.
1289 config PCI_NANOENGINE
1290 bool "BSE nanoEngine PCI support"
1291 depends on SA1100_NANOENGINE
1293 Enable PCI on the BSE nanoEngine board.
1298 config PCI_HOST_ITE8152
1300 depends on PCI && MACH_ARMCORE
1304 source "drivers/pci/Kconfig"
1305 source "drivers/pci/pcie/Kconfig"
1307 source "drivers/pcmcia/Kconfig"
1311 menu "Kernel Features"
1316 This option should be selected by machines which have an SMP-
1319 The only effect of this option is to make the SMP-related
1320 options available to the user for configuration.
1323 bool "Symmetric Multi-Processing"
1324 depends on CPU_V6K || CPU_V7
1325 depends on GENERIC_CLOCKEVENTS
1327 depends on MMU || ARM_MPU
1329 This enables support for systems with more than one CPU. If you have
1330 a system with only one CPU, say N. If you have a system with more
1331 than one CPU, say Y.
1333 If you say N here, the kernel will run on uni- and multiprocessor
1334 machines, but will use only one CPU of a multiprocessor machine. If
1335 you say Y here, the kernel will run on many, but not all,
1336 uniprocessor machines. On a uniprocessor machine, the kernel
1337 will run faster if you say N here.
1339 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1340 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1341 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1343 If you don't know what to do here, say N.
1346 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1347 depends on SMP && !XIP_KERNEL && MMU
1350 SMP kernels contain instructions which fail on non-SMP processors.
1351 Enabling this option allows the kernel to modify itself to make
1352 these instructions safe. Disabling it allows about 1K of space
1355 If you don't know what to do here, say Y.
1357 config ARM_CPU_TOPOLOGY
1358 bool "Support cpu topology definition"
1359 depends on SMP && CPU_V7
1362 Support ARM cpu topology definition. The MPIDR register defines
1363 affinity between processors which is then used to describe the cpu
1364 topology of an ARM System.
1367 bool "Multi-core scheduler support"
1368 depends on ARM_CPU_TOPOLOGY
1370 Multi-core scheduler support improves the CPU scheduler's decision
1371 making when dealing with multi-core CPU chips at a cost of slightly
1372 increased overhead in some places. If unsure say N here.
1375 bool "SMT scheduler support"
1376 depends on ARM_CPU_TOPOLOGY
1378 Improves the CPU scheduler's decision making when dealing with
1379 MultiThreading at a cost of slightly increased overhead in some
1380 places. If unsure say N here.
1385 This option enables support for the ARM system coherency unit
1387 config HAVE_ARM_ARCH_TIMER
1388 bool "Architected timer support"
1390 select ARM_ARCH_TIMER
1391 select GENERIC_CLOCKEVENTS
1393 This option enables support for the ARM architected timer
1398 select CLKSRC_OF if OF
1400 This options enables support for the ARM timer and watchdog unit
1403 bool "Multi-Cluster Power Management"
1404 depends on CPU_V7 && SMP
1406 This option provides the common power management infrastructure
1407 for (multi-)cluster based systems, such as big.LITTLE based
1411 bool "big.LITTLE support (Experimental)"
1412 depends on CPU_V7 && SMP
1415 This option enables support selections for the big.LITTLE
1416 system architecture.
1419 bool "big.LITTLE switcher support"
1420 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1421 select ARM_CPU_SUSPEND
1424 The big.LITTLE "switcher" provides the core functionality to
1425 transparently handle transition between a cluster of A15's
1426 and a cluster of A7's in a big.LITTLE system.
1428 config BL_SWITCHER_DUMMY_IF
1429 tristate "Simple big.LITTLE switcher user interface"
1430 depends on BL_SWITCHER && DEBUG_KERNEL
1432 This is a simple and dummy char dev interface to control
1433 the big.LITTLE switcher core code. It is meant for
1434 debugging purposes only.
1437 prompt "Memory split"
1441 Select the desired split between kernel and user memory.
1443 If you are not absolutely sure what you are doing, leave this
1447 bool "3G/1G user/kernel split"
1449 bool "2G/2G user/kernel split"
1451 bool "1G/3G user/kernel split"
1456 default PHYS_OFFSET if !MMU
1457 default 0x40000000 if VMSPLIT_1G
1458 default 0x80000000 if VMSPLIT_2G
1462 int "Maximum number of CPUs (2-32)"
1468 bool "Support for hot-pluggable CPUs"
1471 Say Y here to experiment with turning CPUs off and on. CPUs
1472 can be controlled through /sys/devices/system/cpu.
1475 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1478 Say Y here if you want Linux to communicate with system firmware
1479 implementing the PSCI specification for CPU-centric power
1480 management operations described in ARM document number ARM DEN
1481 0022A ("Power State Coordination Interface System Software on
1484 # The GPIO number here must be sorted by descending number. In case of
1485 # a multiplatform kernel, we just want the highest value required by the
1486 # selected platforms.
1489 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1490 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1491 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1492 default 416 if ARCH_SUNXI
1493 default 392 if ARCH_U8500
1494 default 352 if ARCH_VT8500
1495 default 288 if ARCH_ROCKCHIP
1496 default 264 if MACH_H4700
1499 Maximum number of GPIOs in the system.
1501 If unsure, leave the default value.
1503 source kernel/Kconfig.preempt
1507 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1508 ARCH_S5PV210 || ARCH_EXYNOS4
1509 default AT91_TIMER_HZ if ARCH_AT91
1510 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1514 depends on HZ_FIXED = 0
1515 prompt "Timer frequency"
1539 default HZ_FIXED if HZ_FIXED != 0
1540 default 100 if HZ_100
1541 default 200 if HZ_200
1542 default 250 if HZ_250
1543 default 300 if HZ_300
1544 default 500 if HZ_500
1548 def_bool HIGH_RES_TIMERS
1550 config THUMB2_KERNEL
1551 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1552 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1553 default y if CPU_THUMBONLY
1555 select ARM_ASM_UNIFIED
1558 By enabling this option, the kernel will be compiled in
1559 Thumb-2 mode. A compiler/assembler that understand the unified
1560 ARM-Thumb syntax is needed.
1564 config THUMB2_AVOID_R_ARM_THM_JUMP11
1565 bool "Work around buggy Thumb-2 short branch relocations in gas"
1566 depends on THUMB2_KERNEL && MODULES
1569 Various binutils versions can resolve Thumb-2 branches to
1570 locally-defined, preemptible global symbols as short-range "b.n"
1571 branch instructions.
1573 This is a problem, because there's no guarantee the final
1574 destination of the symbol, or any candidate locations for a
1575 trampoline, are within range of the branch. For this reason, the
1576 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1577 relocation in modules at all, and it makes little sense to add
1580 The symptom is that the kernel fails with an "unsupported
1581 relocation" error when loading some modules.
1583 Until fixed tools are available, passing
1584 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1585 code which hits this problem, at the cost of a bit of extra runtime
1586 stack usage in some cases.
1588 The problem is described in more detail at:
1589 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1591 Only Thumb-2 kernels are affected.
1593 Unless you are sure your tools don't have this problem, say Y.
1595 config ARM_ASM_UNIFIED
1599 bool "Use the ARM EABI to compile the kernel"
1601 This option allows for the kernel to be compiled using the latest
1602 ARM ABI (aka EABI). This is only useful if you are using a user
1603 space environment that is also compiled with EABI.
1605 Since there are major incompatibilities between the legacy ABI and
1606 EABI, especially with regard to structure member alignment, this
1607 option also changes the kernel syscall calling convention to
1608 disambiguate both ABIs and allow for backward compatibility support
1609 (selected with CONFIG_OABI_COMPAT).
1611 To use this you need GCC version 4.0.0 or later.
1614 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1615 depends on AEABI && !THUMB2_KERNEL
1617 This option preserves the old syscall interface along with the
1618 new (ARM EABI) one. It also provides a compatibility layer to
1619 intercept syscalls that have structure arguments which layout
1620 in memory differs between the legacy ABI and the new ARM EABI
1621 (only for non "thumb" binaries). This option adds a tiny
1622 overhead to all syscalls and produces a slightly larger kernel.
1624 The seccomp filter system will not be available when this is
1625 selected, since there is no way yet to sensibly distinguish
1626 between calling conventions during filtering.
1628 If you know you'll be using only pure EABI user space then you
1629 can say N here. If this option is not selected and you attempt
1630 to execute a legacy ABI binary then the result will be
1631 UNPREDICTABLE (in fact it can be predicted that it won't work
1632 at all). If in doubt say N.
1634 config ARCH_HAS_HOLES_MEMORYMODEL
1637 config ARCH_SPARSEMEM_ENABLE
1640 config ARCH_SPARSEMEM_DEFAULT
1641 def_bool ARCH_SPARSEMEM_ENABLE
1643 config ARCH_SELECT_MEMORY_MODEL
1644 def_bool ARCH_SPARSEMEM_ENABLE
1646 config HAVE_ARCH_PFN_VALID
1647 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1650 bool "High Memory Support"
1653 The address space of ARM processors is only 4 Gigabytes large
1654 and it has to accommodate user address space, kernel address
1655 space as well as some memory mapped IO. That means that, if you
1656 have a large amount of physical memory and/or IO, not all of the
1657 memory can be "permanently mapped" by the kernel. The physical
1658 memory that is not permanently mapped is called "high memory".
1660 Depending on the selected kernel/user memory split, minimum
1661 vmalloc space and actual amount of RAM, you may not need this
1662 option which should result in a slightly faster kernel.
1667 bool "Allocate 2nd-level pagetables from highmem"
1670 config HW_PERF_EVENTS
1671 bool "Enable hardware performance counter support for perf events"
1672 depends on PERF_EVENTS
1675 Enable hardware performance counter support for perf events. If
1676 disabled, perf events will use software events only.
1678 config SYS_SUPPORTS_HUGETLBFS
1682 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1686 config ARCH_WANT_GENERAL_HUGETLB
1691 config FORCE_MAX_ZONEORDER
1692 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1693 range 11 64 if ARCH_SHMOBILE_LEGACY
1694 default "12" if SOC_AM33XX
1695 default "9" if SA1111 || ARCH_EFM32
1698 The kernel memory allocator divides physically contiguous memory
1699 blocks into "zones", where each zone is a power of two number of
1700 pages. This option selects the largest power of two that the kernel
1701 keeps in the memory allocator. If you need to allocate very large
1702 blocks of physically contiguous memory, then you may need to
1703 increase this value.
1705 This config option is actually maximum order plus one. For example,
1706 a value of 11 means that the largest free memory block is 2^10 pages.
1708 config ALIGNMENT_TRAP
1710 depends on CPU_CP15_MMU
1711 default y if !ARCH_EBSA110
1712 select HAVE_PROC_CPU if PROC_FS
1714 ARM processors cannot fetch/store information which is not
1715 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1716 address divisible by 4. On 32-bit ARM processors, these non-aligned
1717 fetch/store instructions will be emulated in software if you say
1718 here, which has a severe performance impact. This is necessary for
1719 correct operation of some network protocols. With an IP-only
1720 configuration it is safe to say N, otherwise say Y.
1722 config UACCESS_WITH_MEMCPY
1723 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1725 default y if CPU_FEROCEON
1727 Implement faster copy_to_user and clear_user methods for CPU
1728 cores where a 8-word STM instruction give significantly higher
1729 memory write throughput than a sequence of individual 32bit stores.
1731 A possible side effect is a slight increase in scheduling latency
1732 between threads sharing the same address space if they invoke
1733 such copy operations with large buffers.
1735 However, if the CPU data cache is using a write-allocate mode,
1736 this option is unlikely to provide any performance gain.
1740 prompt "Enable seccomp to safely compute untrusted bytecode"
1742 This kernel feature is useful for number crunching applications
1743 that may need to compute untrusted bytecode during their
1744 execution. By using pipes or other transports made available to
1745 the process as file descriptors supporting the read/write
1746 syscalls, it's possible to isolate those applications in
1747 their own address space using seccomp. Once seccomp is
1748 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1749 and the task is only allowed to execute a few safe syscalls
1750 defined by each seccomp mode.
1763 bool "Xen guest support on ARM (EXPERIMENTAL)"
1764 depends on ARM && AEABI && OF
1765 depends on CPU_V7 && !CPU_V6
1766 depends on !GENERIC_ATOMIC64
1768 select ARCH_DMA_ADDR_T_64BIT
1772 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1779 bool "Flattened Device Tree support"
1782 select OF_EARLY_FLATTREE
1783 select OF_RESERVED_MEM
1785 Include support for flattened device tree machine descriptions.
1788 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1791 This is the traditional way of passing data to the kernel at boot
1792 time. If you are solely relying on the flattened device tree (or
1793 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1794 to remove ATAGS support from your kernel binary. If unsure,
1797 config DEPRECATED_PARAM_STRUCT
1798 bool "Provide old way to pass kernel parameters"
1801 This was deprecated in 2001 and announced to live on for 5 years.
1802 Some old boot loaders still use this way.
1804 # Compressed boot loader in ROM. Yes, we really want to ask about
1805 # TEXT and BSS so we preserve their values in the config files.
1806 config ZBOOT_ROM_TEXT
1807 hex "Compressed ROM boot loader base address"
1810 The physical address at which the ROM-able zImage is to be
1811 placed in the target. Platforms which normally make use of
1812 ROM-able zImage formats normally set this to a suitable
1813 value in their defconfig file.
1815 If ZBOOT_ROM is not enabled, this has no effect.
1817 config ZBOOT_ROM_BSS
1818 hex "Compressed ROM boot loader BSS address"
1821 The base address of an area of read/write memory in the target
1822 for the ROM-able zImage which must be available while the
1823 decompressor is running. It must be large enough to hold the
1824 entire decompressed kernel plus an additional 128 KiB.
1825 Platforms which normally make use of ROM-able zImage formats
1826 normally set this to a suitable value in their defconfig file.
1828 If ZBOOT_ROM is not enabled, this has no effect.
1831 bool "Compressed boot loader in ROM/flash"
1832 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1833 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1835 Say Y here if you intend to execute your compressed kernel image
1836 (zImage) directly from ROM or flash. If unsure, say N.
1839 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1840 depends on ZBOOT_ROM && ARCH_SH7372
1841 default ZBOOT_ROM_NONE
1843 Include experimental SD/MMC loading code in the ROM-able zImage.
1844 With this enabled it is possible to write the ROM-able zImage
1845 kernel image to an MMC or SD card and boot the kernel straight
1846 from the reset vector. At reset the processor Mask ROM will load
1847 the first part of the ROM-able zImage which in turn loads the
1848 rest the kernel image to RAM.
1850 config ZBOOT_ROM_NONE
1851 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1853 Do not load image from SD or MMC
1855 config ZBOOT_ROM_MMCIF
1856 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1858 Load image from MMCIF hardware block.
1860 config ZBOOT_ROM_SH_MOBILE_SDHI
1861 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1863 Load image from SDHI hardware block
1867 config ARM_APPENDED_DTB
1868 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1871 With this option, the boot code will look for a device tree binary
1872 (DTB) appended to zImage
1873 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1875 This is meant as a backward compatibility convenience for those
1876 systems with a bootloader that can't be upgraded to accommodate
1877 the documented boot protocol using a device tree.
1879 Beware that there is very little in terms of protection against
1880 this option being confused by leftover garbage in memory that might
1881 look like a DTB header after a reboot if no actual DTB is appended
1882 to zImage. Do not leave this option active in a production kernel
1883 if you don't intend to always append a DTB. Proper passing of the
1884 location into r2 of a bootloader provided DTB is always preferable
1887 config ARM_ATAG_DTB_COMPAT
1888 bool "Supplement the appended DTB with traditional ATAG information"
1889 depends on ARM_APPENDED_DTB
1891 Some old bootloaders can't be updated to a DTB capable one, yet
1892 they provide ATAGs with memory configuration, the ramdisk address,
1893 the kernel cmdline string, etc. Such information is dynamically
1894 provided by the bootloader and can't always be stored in a static
1895 DTB. To allow a device tree enabled kernel to be used with such
1896 bootloaders, this option allows zImage to extract the information
1897 from the ATAG list and store it at run time into the appended DTB.
1900 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1901 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1903 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1904 bool "Use bootloader kernel arguments if available"
1906 Uses the command-line options passed by the boot loader instead of
1907 the device tree bootargs property. If the boot loader doesn't provide
1908 any, the device tree bootargs property will be used.
1910 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1911 bool "Extend with bootloader kernel arguments"
1913 The command-line arguments provided by the boot loader will be
1914 appended to the the device tree bootargs property.
1919 string "Default kernel command string"
1922 On some architectures (EBSA110 and CATS), there is currently no way
1923 for the boot loader to pass arguments to the kernel. For these
1924 architectures, you should supply some command-line options at build
1925 time by entering them here. As a minimum, you should specify the
1926 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1929 prompt "Kernel command line type" if CMDLINE != ""
1930 default CMDLINE_FROM_BOOTLOADER
1933 config CMDLINE_FROM_BOOTLOADER
1934 bool "Use bootloader kernel arguments if available"
1936 Uses the command-line options passed by the boot loader. If
1937 the boot loader doesn't provide any, the default kernel command
1938 string provided in CMDLINE will be used.
1940 config CMDLINE_EXTEND
1941 bool "Extend bootloader kernel arguments"
1943 The command-line arguments provided by the boot loader will be
1944 appended to the default kernel command string.
1946 config CMDLINE_FORCE
1947 bool "Always use the default kernel command string"
1949 Always use the default kernel command string, even if the boot
1950 loader passes other arguments to the kernel.
1951 This is useful if you cannot or don't want to change the
1952 command-line options your boot loader passes to the kernel.
1956 bool "Kernel Execute-In-Place from ROM"
1957 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1959 Execute-In-Place allows the kernel to run from non-volatile storage
1960 directly addressable by the CPU, such as NOR flash. This saves RAM
1961 space since the text section of the kernel is not loaded from flash
1962 to RAM. Read-write sections, such as the data section and stack,
1963 are still copied to RAM. The XIP kernel is not compressed since
1964 it has to run directly from flash, so it will take more space to
1965 store it. The flash address used to link the kernel object files,
1966 and for storing it, is configuration dependent. Therefore, if you
1967 say Y here, you must know the proper physical address where to
1968 store the kernel image depending on your own flash memory usage.
1970 Also note that the make target becomes "make xipImage" rather than
1971 "make zImage" or "make Image". The final kernel binary to put in
1972 ROM memory will be arch/arm/boot/xipImage.
1976 config XIP_PHYS_ADDR
1977 hex "XIP Kernel Physical Location"
1978 depends on XIP_KERNEL
1979 default "0x00080000"
1981 This is the physical address in your flash memory the kernel will
1982 be linked for and stored to. This address is dependent on your
1986 bool "Kexec system call (EXPERIMENTAL)"
1987 depends on (!SMP || PM_SLEEP_SMP)
1989 kexec is a system call that implements the ability to shutdown your
1990 current kernel, and to start another kernel. It is like a reboot
1991 but it is independent of the system firmware. And like a reboot
1992 you can start any kernel with it, not just Linux.
1994 It is an ongoing process to be certain the hardware in a machine
1995 is properly shutdown, so do not be surprised if this code does not
1996 initially work for you.
1999 bool "Export atags in procfs"
2000 depends on ATAGS && KEXEC
2003 Should the atags used to boot the kernel be exported in an "atags"
2004 file in procfs. Useful with kexec.
2007 bool "Build kdump crash kernel (EXPERIMENTAL)"
2009 Generate crash dump after being started by kexec. This should
2010 be normally only set in special crash dump kernels which are
2011 loaded in the main kernel with kexec-tools into a specially
2012 reserved region and then later executed after a crash by
2013 kdump/kexec. The crash dump kernel must be compiled to a
2014 memory address not used by the main kernel
2016 For more details see Documentation/kdump/kdump.txt
2018 config AUTO_ZRELADDR
2019 bool "Auto calculation of the decompressed kernel image address"
2021 ZRELADDR is the physical address where the decompressed kernel
2022 image will be placed. If AUTO_ZRELADDR is selected, the address
2023 will be determined at run-time by masking the current IP with
2024 0xf8000000. This assumes the zImage being placed in the first 128MB
2025 from start of memory.
2029 menu "CPU Power Management"
2031 source "drivers/cpufreq/Kconfig"
2033 source "drivers/cpuidle/Kconfig"
2037 menu "Floating point emulation"
2039 comment "At least one emulation must be selected"
2042 bool "NWFPE math emulation"
2043 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2045 Say Y to include the NWFPE floating point emulator in the kernel.
2046 This is necessary to run most binaries. Linux does not currently
2047 support floating point hardware so you need to say Y here even if
2048 your machine has an FPA or floating point co-processor podule.
2050 You may say N here if you are going to load the Acorn FPEmulator
2051 early in the bootup.
2054 bool "Support extended precision"
2055 depends on FPE_NWFPE
2057 Say Y to include 80-bit support in the kernel floating-point
2058 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2059 Note that gcc does not generate 80-bit operations by default,
2060 so in most cases this option only enlarges the size of the
2061 floating point emulator without any good reason.
2063 You almost surely want to say N here.
2066 bool "FastFPE math emulation (EXPERIMENTAL)"
2067 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2069 Say Y here to include the FAST floating point emulator in the kernel.
2070 This is an experimental much faster emulator which now also has full
2071 precision for the mantissa. It does not support any exceptions.
2072 It is very simple, and approximately 3-6 times faster than NWFPE.
2074 It should be sufficient for most programs. It may be not suitable
2075 for scientific calculations, but you have to check this for yourself.
2076 If you do not feel you need a faster FP emulation you should better
2080 bool "VFP-format floating point maths"
2081 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2083 Say Y to include VFP support code in the kernel. This is needed
2084 if your hardware includes a VFP unit.
2086 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2087 release notes and additional status information.
2089 Say N if your target does not have VFP hardware.
2097 bool "Advanced SIMD (NEON) Extension support"
2098 depends on VFPv3 && CPU_V7
2100 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2103 config KERNEL_MODE_NEON
2104 bool "Support for NEON in kernel mode"
2105 depends on NEON && AEABI
2107 Say Y to include support for NEON in kernel mode.
2111 menu "Userspace binary formats"
2113 source "fs/Kconfig.binfmt"
2116 tristate "RISC OS personality"
2119 Say Y here to include the kernel code necessary if you want to run
2120 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2121 experimental; if this sounds frightening, say N and sleep in peace.
2122 You can also say M here to compile this support as a module (which
2123 will be called arthur).
2127 menu "Power management options"
2129 source "kernel/power/Kconfig"
2131 config ARCH_SUSPEND_POSSIBLE
2132 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2133 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2136 config ARM_CPU_SUSPEND
2139 config ARCH_HIBERNATION_POSSIBLE
2142 default y if ARCH_SUSPEND_POSSIBLE
2146 source "net/Kconfig"
2148 source "drivers/Kconfig"
2152 source "arch/arm/Kconfig.debug"
2154 source "security/Kconfig"
2156 source "crypto/Kconfig"
2158 source "lib/Kconfig"
2160 source "arch/arm/kvm/Kconfig"