4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select GENERIC_ALLOCATOR
19 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
20 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_PROBE
23 select GENERIC_IRQ_SHOW
24 select GENERIC_IRQ_SHOW_LEVEL
25 select GENERIC_PCI_IOMAP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select HANDLE_DOMAIN_IRQ
31 select HARDIRQS_SW_RESEND
32 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
36 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_TRACEHOOK
39 select HAVE_CC_STACKPROTECTOR
40 select HAVE_CONTEXT_TRACKING
41 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_API_DEBUG
45 select HAVE_DMA_CONTIGUOUS if MMU
46 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
47 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
48 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
49 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
50 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
51 select HAVE_GENERIC_DMA_COHERENT
52 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
53 select HAVE_IDE if PCI || ISA || PCMCIA
54 select HAVE_IRQ_TIME_ACCOUNTING
55 select HAVE_KERNEL_GZIP
56 select HAVE_KERNEL_LZ4
57 select HAVE_KERNEL_LZMA
58 select HAVE_KERNEL_LZO
60 select HAVE_KPROBES if !XIP_KERNEL
61 select HAVE_KRETPROBES if (HAVE_KPROBES)
63 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
64 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
65 select HAVE_OPTPROBES if !THUMB2_KERNEL
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
70 select HAVE_REGS_AND_STACK_ACCESS_API
71 select HAVE_SYSCALL_TRACEPOINTS
73 select HAVE_VIRT_CPU_ACCOUNTING_GEN
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_REL
78 select OLD_SIGSUSPEND3
79 select PERF_USE_VMALLOC
81 select SYS_SUPPORTS_APM_EMULATION
82 # Above selects are sorted alphabetically; please add new ones
83 # according to that. Thanks.
85 The ARM series is a line of low-power-consumption RISC chip designs
86 licensed by ARM Ltd and targeted at embedded applications and
87 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
88 manufactured, but legacy ARM-based PC hardware remains popular in
89 Europe. There is an ARM Linux project with a web page at
90 <http://www.arm.linux.org.uk/>.
92 config ARM_HAS_SG_CHAIN
93 select ARCH_HAS_SG_CHAIN
96 config NEED_SG_DMA_LENGTH
99 config ARM_DMA_USE_IOMMU
101 select ARM_HAS_SG_CHAIN
102 select NEED_SG_DMA_LENGTH
106 config ARM_DMA_IOMMU_ALIGNMENT
107 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
111 DMA mapping framework by default aligns all buffers to the smallest
112 PAGE_SIZE order which is greater than or equal to the requested buffer
113 size. This works well for buffers up to a few hundreds kilobytes, but
114 for larger buffers it just a waste of address space. Drivers which has
115 relatively small addressing window (like 64Mib) might run out of
116 virtual space with just a few allocations.
118 With this parameter you can specify the maximum PAGE_SIZE order for
119 DMA IOMMU buffers. Larger buffers will be aligned only to this
120 specified order. The order is expressed as a power of two multiplied
125 config MIGHT_HAVE_PCI
128 config SYS_SUPPORTS_APM_EMULATION
133 select GENERIC_ALLOCATOR
144 The Extended Industry Standard Architecture (EISA) bus was
145 developed as an open alternative to the IBM MicroChannel bus.
147 The EISA bus provided some of the features of the IBM MicroChannel
148 bus while maintaining backward compatibility with cards made for
149 the older ISA bus. The EISA bus saw limited use between 1988 and
150 1995 when it was made obsolete by the PCI bus.
152 Say Y here if you are building a kernel for an EISA-based machine.
159 config STACKTRACE_SUPPORT
163 config HAVE_LATENCYTOP_SUPPORT
168 config LOCKDEP_SUPPORT
172 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
180 config ARCH_HAS_ILOG2_U32
183 config ARCH_HAS_ILOG2_U64
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text. Please add new entries in the option alphabetic order.
313 prompt "ARM system type"
314 default ARCH_VERSATILE if !MMU
315 default ARCH_MULTIPLATFORM if MMU
317 config ARCH_MULTIPLATFORM
318 bool "Allow multiple platforms to be selected"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
326 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select MULTI_IRQ_HANDLER
333 bool "ARM Ltd. RealView family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_TIMER_SP804
338 select COMMON_CLK_VERSATILE
339 select GENERIC_CLOCKEVENTS
340 select GPIO_PL061 if GPIOLIB
342 select NEED_MACH_MEMORY_H
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_SCHED_CLOCK
346 This enables support for ARM Ltd RealView boards.
348 config ARCH_VERSATILE
349 bool "ARM Ltd. Versatile family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select HAVE_MACH_CLKDEV
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_CLOCK
360 select PLAT_VERSATILE_SCHED_CLOCK
361 select VERSATILE_FPGA_IRQ
363 This enables support for ARM Ltd Versatile board.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_REQUIRE_GPIOLIB
372 select GENERIC_CLOCKEVENTS
376 Support for Cirrus Logic 711x/721x/731x based boards.
379 bool "Cortina Systems Gemini"
380 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 Support for the Cortina Systems Gemini family SoCs
389 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_IO_H
393 select NEED_MACH_MEMORY_H
396 This is an evaluation board for the StrongARM processor available
397 from Digital. It has limited hardware on-board, including an
398 Ethernet interface, two PCMCIA sockets, two serial ports and a
402 bool "Energy Micro efm32"
404 select ARCH_REQUIRE_GPIOLIB
410 select GENERIC_CLOCKEVENTS
416 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
421 select ARCH_HAS_HOLES_MEMORYMODEL
422 select ARCH_REQUIRE_GPIOLIB
423 select ARCH_USES_GETTIMEOFFSET
429 This enables support for the Cirrus EP93xx series of CPUs.
431 config ARCH_FOOTBRIDGE
435 select GENERIC_CLOCKEVENTS
437 select NEED_MACH_IO_H if !MMU
438 select NEED_MACH_MEMORY_H
440 Support for systems based on the DC21285 companion chip
441 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
444 bool "Hilscher NetX based"
448 select GENERIC_CLOCKEVENTS
450 This enables support for systems based on the Hilscher NetX Soc
456 select NEED_MACH_MEMORY_H
457 select NEED_RET_TO_USER
463 Support for Intel's IOP13XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
471 select NEED_RET_TO_USER
475 Support for Intel's 80219 and IOP32X (XScale) family of
481 select ARCH_REQUIRE_GPIOLIB
484 select NEED_RET_TO_USER
488 Support for Intel's IOP33X (XScale) family of processors.
493 select ARCH_HAS_DMA_SET_COHERENT_MASK
494 select ARCH_REQUIRE_GPIOLIB
495 select ARCH_SUPPORTS_BIG_ENDIAN
498 select DMABOUNCE if PCI
499 select GENERIC_CLOCKEVENTS
500 select MIGHT_HAVE_PCI
501 select NEED_MACH_IO_H
502 select USB_EHCI_BIG_ENDIAN_DESC
503 select USB_EHCI_BIG_ENDIAN_MMIO
505 Support for Intel's IXP4XX (XScale) family of processors.
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
512 select MIGHT_HAVE_PCI
516 select PLAT_ORION_LEGACY
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
527 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell Orion 5x series SoCs:
543 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544 Orion-2 (5281), Orion-1-90 (6183).
547 bool "Marvell PXA168/910/MMP2"
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_ALLOCATOR
552 select GENERIC_CLOCKEVENTS
555 select MULTI_IRQ_HANDLER
560 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
563 bool "Micrel/Kendin KS8695"
564 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
568 select NEED_MACH_MEMORY_H
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
575 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
590 bool "NXP LPC18xx/LPC43xx"
592 select ARCH_HAS_RESET_CONTROLLER
593 select ARCH_REQUIRE_GPIOLIB
597 select CLKSRC_LPC32XX
600 select GENERIC_CLOCKEVENTS
606 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
607 high performance microcontrollers.
611 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
620 Support for the NXP LPC32XX family of processors
623 bool "PXA2xx/PXA3xx-based"
626 select ARCH_REQUIRE_GPIOLIB
627 select ARM_CPU_SUSPEND if PM
633 select GENERIC_CLOCKEVENTS
637 select MULTI_IRQ_HANDLER
641 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
643 config ARCH_SHMOBILE_LEGACY
644 bool "Renesas ARM SoCs (non-multiplatform)"
646 select ARM_PATCH_PHYS_VIRT if MMU
649 select GENERIC_CLOCKEVENTS
650 select HAVE_ARM_SCU if SMP
651 select HAVE_ARM_TWD if SMP
653 select MIGHT_HAVE_CACHE_L2X0
654 select MULTI_IRQ_HANDLER
657 select PM_GENERIC_DOMAINS if PM
661 Support for Renesas ARM SoC platforms using a non-multiplatform
662 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
668 select ARCH_MAY_HAVE_PC_FDC
669 select ARCH_SPARSEMEM_ENABLE
670 select ARCH_USES_GETTIMEOFFSET
674 select HAVE_PATA_PLATFORM
676 select NEED_MACH_IO_H
677 select NEED_MACH_MEMORY_H
681 On the Acorn Risc-PC, Linux can support the internal IDE disk and
682 CD-ROM interface, serial and parallel port, and the floppy drive.
687 select ARCH_REQUIRE_GPIOLIB
688 select ARCH_SPARSEMEM_ENABLE
693 select GENERIC_CLOCKEVENTS
697 select MULTI_IRQ_HANDLER
698 select NEED_MACH_MEMORY_H
701 Support for StrongARM 11x0 based boards.
704 bool "Samsung S3C24XX SoCs"
705 select ARCH_REQUIRE_GPIOLIB
708 select CLKSRC_SAMSUNG_PWM
709 select GENERIC_CLOCKEVENTS
711 select HAVE_S3C2410_I2C if I2C
712 select HAVE_S3C2410_WATCHDOG if WATCHDOG
713 select HAVE_S3C_RTC if RTC_CLASS
714 select MULTI_IRQ_HANDLER
715 select NEED_MACH_IO_H
718 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
719 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
720 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
721 Samsung SMDK2410 development board (and derivatives).
724 bool "Samsung S3C64XX"
725 select ARCH_REQUIRE_GPIOLIB
730 select CLKSRC_SAMSUNG_PWM
731 select COMMON_CLK_SAMSUNG
733 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select PM_GENERIC_DOMAINS if PM
742 select S3C_GPIO_TRACK
744 select SAMSUNG_WAKEMASK
745 select SAMSUNG_WDT_RESET
747 Samsung S3C64XX series based systems
751 select ARCH_HAS_HOLES_MEMORYMODEL
752 select ARCH_REQUIRE_GPIOLIB
754 select GENERIC_ALLOCATOR
755 select GENERIC_CLOCKEVENTS
756 select GENERIC_IRQ_CHIP
762 Support for TI's DaVinci platform.
767 select ARCH_HAS_HOLES_MEMORYMODEL
769 select ARCH_REQUIRE_GPIOLIB
772 select GENERIC_CLOCKEVENTS
773 select GENERIC_IRQ_CHIP
776 select NEED_MACH_IO_H if PCCARD
777 select NEED_MACH_MEMORY_H
779 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
782 bool "STMicrolectronics STM32"
784 select ARCH_HAS_RESET_CONTROLLER
786 select ARMV7M_SYSTICK
791 select GENERIC_CLOCKEVENTS
793 select RESET_CONTROLLER
797 Support for STMicroelectronics STM32 processors.
801 menu "Multiple platform selection"
802 depends on ARCH_MULTIPLATFORM
804 comment "CPU Core family selection"
807 bool "ARMv4 based platforms (FA526)"
808 depends on !ARCH_MULTI_V6_V7
809 select ARCH_MULTI_V4_V5
812 config ARCH_MULTI_V4T
813 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
814 depends on !ARCH_MULTI_V6_V7
815 select ARCH_MULTI_V4_V5
816 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
817 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
818 CPU_ARM925T || CPU_ARM940T)
821 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
822 depends on !ARCH_MULTI_V6_V7
823 select ARCH_MULTI_V4_V5
824 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
825 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
826 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
828 config ARCH_MULTI_V4_V5
832 bool "ARMv6 based platforms (ARM11)"
833 select ARCH_MULTI_V6_V7
837 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
839 select ARCH_MULTI_V6_V7
843 config ARCH_MULTI_V6_V7
845 select MIGHT_HAVE_CACHE_L2X0
847 config ARCH_MULTI_CPU_AUTO
848 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
854 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
858 select HAVE_ARM_ARCH_TIMER
861 # This is sorted alphabetically by mach-* pathname. However, plat-*
862 # Kconfigs may be included either alphabetically (according to the
863 # plat- suffix) or along side the corresponding mach-* source.
865 source "arch/arm/mach-mvebu/Kconfig"
867 source "arch/arm/mach-alpine/Kconfig"
869 source "arch/arm/mach-asm9260/Kconfig"
871 source "arch/arm/mach-at91/Kconfig"
873 source "arch/arm/mach-axxia/Kconfig"
875 source "arch/arm/mach-bcm/Kconfig"
877 source "arch/arm/mach-berlin/Kconfig"
879 source "arch/arm/mach-clps711x/Kconfig"
881 source "arch/arm/mach-cns3xxx/Kconfig"
883 source "arch/arm/mach-davinci/Kconfig"
885 source "arch/arm/mach-digicolor/Kconfig"
887 source "arch/arm/mach-dove/Kconfig"
889 source "arch/arm/mach-ep93xx/Kconfig"
891 source "arch/arm/mach-footbridge/Kconfig"
893 source "arch/arm/mach-gemini/Kconfig"
895 source "arch/arm/mach-highbank/Kconfig"
897 source "arch/arm/mach-hisi/Kconfig"
899 source "arch/arm/mach-integrator/Kconfig"
901 source "arch/arm/mach-iop32x/Kconfig"
903 source "arch/arm/mach-iop33x/Kconfig"
905 source "arch/arm/mach-iop13xx/Kconfig"
907 source "arch/arm/mach-ixp4xx/Kconfig"
909 source "arch/arm/mach-keystone/Kconfig"
911 source "arch/arm/mach-ks8695/Kconfig"
913 source "arch/arm/mach-meson/Kconfig"
915 source "arch/arm/mach-moxart/Kconfig"
917 source "arch/arm/mach-mv78xx0/Kconfig"
919 source "arch/arm/mach-imx/Kconfig"
921 source "arch/arm/mach-mediatek/Kconfig"
923 source "arch/arm/mach-mxs/Kconfig"
925 source "arch/arm/mach-netx/Kconfig"
927 source "arch/arm/mach-nomadik/Kconfig"
929 source "arch/arm/mach-nspire/Kconfig"
931 source "arch/arm/plat-omap/Kconfig"
933 source "arch/arm/mach-omap1/Kconfig"
935 source "arch/arm/mach-omap2/Kconfig"
937 source "arch/arm/mach-orion5x/Kconfig"
939 source "arch/arm/mach-picoxcell/Kconfig"
941 source "arch/arm/mach-pxa/Kconfig"
942 source "arch/arm/plat-pxa/Kconfig"
944 source "arch/arm/mach-mmp/Kconfig"
946 source "arch/arm/mach-qcom/Kconfig"
948 source "arch/arm/mach-realview/Kconfig"
950 source "arch/arm/mach-rockchip/Kconfig"
952 source "arch/arm/mach-sa1100/Kconfig"
954 source "arch/arm/mach-socfpga/Kconfig"
956 source "arch/arm/mach-spear/Kconfig"
958 source "arch/arm/mach-sti/Kconfig"
960 source "arch/arm/mach-s3c24xx/Kconfig"
962 source "arch/arm/mach-s3c64xx/Kconfig"
964 source "arch/arm/mach-s5pv210/Kconfig"
966 source "arch/arm/mach-exynos/Kconfig"
967 source "arch/arm/plat-samsung/Kconfig"
969 source "arch/arm/mach-shmobile/Kconfig"
971 source "arch/arm/mach-sunxi/Kconfig"
973 source "arch/arm/mach-prima2/Kconfig"
975 source "arch/arm/mach-tegra/Kconfig"
977 source "arch/arm/mach-u300/Kconfig"
979 source "arch/arm/mach-uniphier/Kconfig"
981 source "arch/arm/mach-ux500/Kconfig"
983 source "arch/arm/mach-versatile/Kconfig"
985 source "arch/arm/mach-vexpress/Kconfig"
986 source "arch/arm/plat-versatile/Kconfig"
988 source "arch/arm/mach-vt8500/Kconfig"
990 source "arch/arm/mach-w90x900/Kconfig"
992 source "arch/arm/mach-zx/Kconfig"
994 source "arch/arm/mach-zynq/Kconfig"
996 # Definitions to make life easier
1002 select GENERIC_CLOCKEVENTS
1008 select GENERIC_IRQ_CHIP
1011 config PLAT_ORION_LEGACY
1018 config PLAT_VERSATILE
1021 config ARM_TIMER_SP804
1024 select CLKSRC_OF if OF
1026 source "arch/arm/firmware/Kconfig"
1028 source arch/arm/mm/Kconfig
1031 bool "Enable iWMMXt support"
1032 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1033 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1035 Enable support for iWMMXt context switching at run time if
1036 running on a CPU that supports it.
1038 config MULTI_IRQ_HANDLER
1041 Allow each machine to specify it's own IRQ handler at run time.
1044 source "arch/arm/Kconfig-nommu"
1047 config PJ4B_ERRATA_4742
1048 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1049 depends on CPU_PJ4B && MACH_ARMADA_370
1052 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1053 Event (WFE) IDLE states, a specific timing sensitivity exists between
1054 the retiring WFI/WFE instructions and the newly issued subsequent
1055 instructions. This sensitivity can result in a CPU hang scenario.
1057 The software must insert either a Data Synchronization Barrier (DSB)
1058 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1061 config ARM_ERRATA_326103
1062 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1065 Executing a SWP instruction to read-only memory does not set bit 11
1066 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1067 treat the access as a read, preventing a COW from occurring and
1068 causing the faulting task to livelock.
1070 config ARM_ERRATA_411920
1071 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1072 depends on CPU_V6 || CPU_V6K
1074 Invalidation of the Instruction Cache operation can
1075 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1076 It does not affect the MPCore. This option enables the ARM Ltd.
1077 recommended workaround.
1079 config ARM_ERRATA_430973
1080 bool "ARM errata: Stale prediction on replaced interworking branch"
1083 This option enables the workaround for the 430973 Cortex-A8
1084 r1p* erratum. If a code sequence containing an ARM/Thumb
1085 interworking branch is replaced with another code sequence at the
1086 same virtual address, whether due to self-modifying code or virtual
1087 to physical address re-mapping, Cortex-A8 does not recover from the
1088 stale interworking branch prediction. This results in Cortex-A8
1089 executing the new code sequence in the incorrect ARM or Thumb state.
1090 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1091 and also flushes the branch target cache at every context switch.
1092 Note that setting specific bits in the ACTLR register may not be
1093 available in non-secure mode.
1095 config ARM_ERRATA_458693
1096 bool "ARM errata: Processor deadlock when a false hazard is created"
1098 depends on !ARCH_MULTIPLATFORM
1100 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1101 erratum. For very specific sequences of memory operations, it is
1102 possible for a hazard condition intended for a cache line to instead
1103 be incorrectly associated with a different cache line. This false
1104 hazard might then cause a processor deadlock. The workaround enables
1105 the L1 caching of the NEON accesses and disables the PLD instruction
1106 in the ACTLR register. Note that setting specific bits in the ACTLR
1107 register may not be available in non-secure mode.
1109 config ARM_ERRATA_460075
1110 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1112 depends on !ARCH_MULTIPLATFORM
1114 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1115 erratum. Any asynchronous access to the L2 cache may encounter a
1116 situation in which recent store transactions to the L2 cache are lost
1117 and overwritten with stale memory contents from external memory. The
1118 workaround disables the write-allocate mode for the L2 cache via the
1119 ACTLR register. Note that setting specific bits in the ACTLR register
1120 may not be available in non-secure mode.
1122 config ARM_ERRATA_742230
1123 bool "ARM errata: DMB operation may be faulty"
1124 depends on CPU_V7 && SMP
1125 depends on !ARCH_MULTIPLATFORM
1127 This option enables the workaround for the 742230 Cortex-A9
1128 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1129 between two write operations may not ensure the correct visibility
1130 ordering of the two writes. This workaround sets a specific bit in
1131 the diagnostic register of the Cortex-A9 which causes the DMB
1132 instruction to behave as a DSB, ensuring the correct behaviour of
1135 config ARM_ERRATA_742231
1136 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1137 depends on CPU_V7 && SMP
1138 depends on !ARCH_MULTIPLATFORM
1140 This option enables the workaround for the 742231 Cortex-A9
1141 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1142 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1143 accessing some data located in the same cache line, may get corrupted
1144 data due to bad handling of the address hazard when the line gets
1145 replaced from one of the CPUs at the same time as another CPU is
1146 accessing it. This workaround sets specific bits in the diagnostic
1147 register of the Cortex-A9 which reduces the linefill issuing
1148 capabilities of the processor.
1150 config ARM_ERRATA_643719
1151 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1152 depends on CPU_V7 && SMP
1155 This option enables the workaround for the 643719 Cortex-A9 (prior to
1156 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1157 register returns zero when it should return one. The workaround
1158 corrects this value, ensuring cache maintenance operations which use
1159 it behave as intended and avoiding data corruption.
1161 config ARM_ERRATA_720789
1162 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1165 This option enables the workaround for the 720789 Cortex-A9 (prior to
1166 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1167 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1168 As a consequence of this erratum, some TLB entries which should be
1169 invalidated are not, resulting in an incoherency in the system page
1170 tables. The workaround changes the TLB flushing routines to invalidate
1171 entries regardless of the ASID.
1173 config ARM_ERRATA_743622
1174 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1176 depends on !ARCH_MULTIPLATFORM
1178 This option enables the workaround for the 743622 Cortex-A9
1179 (r2p*) erratum. Under very rare conditions, a faulty
1180 optimisation in the Cortex-A9 Store Buffer may lead to data
1181 corruption. This workaround sets a specific bit in the diagnostic
1182 register of the Cortex-A9 which disables the Store Buffer
1183 optimisation, preventing the defect from occurring. This has no
1184 visible impact on the overall performance or power consumption of the
1187 config ARM_ERRATA_751472
1188 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1190 depends on !ARCH_MULTIPLATFORM
1192 This option enables the workaround for the 751472 Cortex-A9 (prior
1193 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1194 completion of a following broadcasted operation if the second
1195 operation is received by a CPU before the ICIALLUIS has completed,
1196 potentially leading to corrupted entries in the cache or TLB.
1198 config ARM_ERRATA_754322
1199 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1202 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1203 r3p*) erratum. A speculative memory access may cause a page table walk
1204 which starts prior to an ASID switch but completes afterwards. This
1205 can populate the micro-TLB with a stale entry which may be hit with
1206 the new ASID. This workaround places two dsb instructions in the mm
1207 switching code so that no page table walks can cross the ASID switch.
1209 config ARM_ERRATA_754327
1210 bool "ARM errata: no automatic Store Buffer drain"
1211 depends on CPU_V7 && SMP
1213 This option enables the workaround for the 754327 Cortex-A9 (prior to
1214 r2p0) erratum. The Store Buffer does not have any automatic draining
1215 mechanism and therefore a livelock may occur if an external agent
1216 continuously polls a memory location waiting to observe an update.
1217 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1218 written polling loops from denying visibility of updates to memory.
1220 config ARM_ERRATA_364296
1221 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1224 This options enables the workaround for the 364296 ARM1136
1225 r0p2 erratum (possible cache data corruption with
1226 hit-under-miss enabled). It sets the undocumented bit 31 in
1227 the auxiliary control register and the FI bit in the control
1228 register, thus disabling hit-under-miss without putting the
1229 processor into full low interrupt latency mode. ARM11MPCore
1232 config ARM_ERRATA_764369
1233 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1234 depends on CPU_V7 && SMP
1236 This option enables the workaround for erratum 764369
1237 affecting Cortex-A9 MPCore with two or more processors (all
1238 current revisions). Under certain timing circumstances, a data
1239 cache line maintenance operation by MVA targeting an Inner
1240 Shareable memory region may fail to proceed up to either the
1241 Point of Coherency or to the Point of Unification of the
1242 system. This workaround adds a DSB instruction before the
1243 relevant cache maintenance functions and sets a specific bit
1244 in the diagnostic control register of the SCU.
1246 config ARM_ERRATA_775420
1247 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1250 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1251 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1252 operation aborts with MMU exception, it might cause the processor
1253 to deadlock. This workaround puts DSB before executing ISB if
1254 an abort may occur on cache maintenance.
1256 config ARM_ERRATA_798181
1257 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1258 depends on CPU_V7 && SMP
1260 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1261 adequately shooting down all use of the old entries. This
1262 option enables the Linux kernel workaround for this erratum
1263 which sends an IPI to the CPUs that are running the same ASID
1264 as the one being invalidated.
1266 config ARM_ERRATA_773022
1267 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1270 This option enables the workaround for the 773022 Cortex-A15
1271 (up to r0p4) erratum. In certain rare sequences of code, the
1272 loop buffer may deliver incorrect instructions. This
1273 workaround disables the loop buffer to avoid the erratum.
1277 source "arch/arm/common/Kconfig"
1284 Find out whether you have ISA slots on your motherboard. ISA is the
1285 name of a bus system, i.e. the way the CPU talks to the other stuff
1286 inside your box. Other bus systems are PCI, EISA, MicroChannel
1287 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1288 newer boards don't support it. If you have ISA, say Y, otherwise N.
1290 # Select ISA DMA controller support
1295 # Select ISA DMA interface
1300 bool "PCI support" if MIGHT_HAVE_PCI
1302 Find out whether you have a PCI motherboard. PCI is the name of a
1303 bus system, i.e. the way the CPU talks to the other stuff inside
1304 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1305 VESA. If you have PCI, say Y, otherwise N.
1311 config PCI_DOMAINS_GENERIC
1312 def_bool PCI_DOMAINS
1314 config PCI_NANOENGINE
1315 bool "BSE nanoEngine PCI support"
1316 depends on SA1100_NANOENGINE
1318 Enable PCI on the BSE nanoEngine board.
1323 config PCI_HOST_ITE8152
1325 depends on PCI && MACH_ARMCORE
1329 source "drivers/pci/Kconfig"
1330 source "drivers/pci/pcie/Kconfig"
1332 source "drivers/pcmcia/Kconfig"
1336 menu "Kernel Features"
1341 This option should be selected by machines which have an SMP-
1344 The only effect of this option is to make the SMP-related
1345 options available to the user for configuration.
1348 bool "Symmetric Multi-Processing"
1349 depends on CPU_V6K || CPU_V7
1350 depends on GENERIC_CLOCKEVENTS
1352 depends on MMU || ARM_MPU
1354 This enables support for systems with more than one CPU. If you have
1355 a system with only one CPU, say N. If you have a system with more
1356 than one CPU, say Y.
1358 If you say N here, the kernel will run on uni- and multiprocessor
1359 machines, but will use only one CPU of a multiprocessor machine. If
1360 you say Y here, the kernel will run on many, but not all,
1361 uniprocessor machines. On a uniprocessor machine, the kernel
1362 will run faster if you say N here.
1364 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1365 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1366 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1368 If you don't know what to do here, say N.
1371 bool "Allow booting SMP kernel on uniprocessor systems"
1372 depends on SMP && !XIP_KERNEL && MMU
1375 SMP kernels contain instructions which fail on non-SMP processors.
1376 Enabling this option allows the kernel to modify itself to make
1377 these instructions safe. Disabling it allows about 1K of space
1380 If you don't know what to do here, say Y.
1382 config ARM_CPU_TOPOLOGY
1383 bool "Support cpu topology definition"
1384 depends on SMP && CPU_V7
1387 Support ARM cpu topology definition. The MPIDR register defines
1388 affinity between processors which is then used to describe the cpu
1389 topology of an ARM System.
1392 bool "Multi-core scheduler support"
1393 depends on ARM_CPU_TOPOLOGY
1395 Multi-core scheduler support improves the CPU scheduler's decision
1396 making when dealing with multi-core CPU chips at a cost of slightly
1397 increased overhead in some places. If unsure say N here.
1400 bool "SMT scheduler support"
1401 depends on ARM_CPU_TOPOLOGY
1403 Improves the CPU scheduler's decision making when dealing with
1404 MultiThreading at a cost of slightly increased overhead in some
1405 places. If unsure say N here.
1410 This option enables support for the ARM system coherency unit
1412 config HAVE_ARM_ARCH_TIMER
1413 bool "Architected timer support"
1415 select ARM_ARCH_TIMER
1416 select GENERIC_CLOCKEVENTS
1418 This option enables support for the ARM architected timer
1423 select CLKSRC_OF if OF
1425 This options enables support for the ARM timer and watchdog unit
1428 bool "Multi-Cluster Power Management"
1429 depends on CPU_V7 && SMP
1431 This option provides the common power management infrastructure
1432 for (multi-)cluster based systems, such as big.LITTLE based
1435 config MCPM_QUAD_CLUSTER
1439 To avoid wasting resources unnecessarily, MCPM only supports up
1440 to 2 clusters by default.
1441 Platforms with 3 or 4 clusters that use MCPM must select this
1442 option to allow the additional clusters to be managed.
1445 bool "big.LITTLE support (Experimental)"
1446 depends on CPU_V7 && SMP
1449 This option enables support selections for the big.LITTLE
1450 system architecture.
1453 bool "big.LITTLE switcher support"
1454 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1455 select ARM_CPU_SUSPEND
1458 The big.LITTLE "switcher" provides the core functionality to
1459 transparently handle transition between a cluster of A15's
1460 and a cluster of A7's in a big.LITTLE system.
1462 config BL_SWITCHER_DUMMY_IF
1463 tristate "Simple big.LITTLE switcher user interface"
1464 depends on BL_SWITCHER && DEBUG_KERNEL
1466 This is a simple and dummy char dev interface to control
1467 the big.LITTLE switcher core code. It is meant for
1468 debugging purposes only.
1471 prompt "Memory split"
1475 Select the desired split between kernel and user memory.
1477 If you are not absolutely sure what you are doing, leave this
1481 bool "3G/1G user/kernel split"
1483 bool "2G/2G user/kernel split"
1485 bool "1G/3G user/kernel split"
1490 default PHYS_OFFSET if !MMU
1491 default 0x40000000 if VMSPLIT_1G
1492 default 0x80000000 if VMSPLIT_2G
1496 int "Maximum number of CPUs (2-32)"
1502 bool "Support for hot-pluggable CPUs"
1505 Say Y here to experiment with turning CPUs off and on. CPUs
1506 can be controlled through /sys/devices/system/cpu.
1509 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1512 Say Y here if you want Linux to communicate with system firmware
1513 implementing the PSCI specification for CPU-centric power
1514 management operations described in ARM document number ARM DEN
1515 0022A ("Power State Coordination Interface System Software on
1518 # The GPIO number here must be sorted by descending number. In case of
1519 # a multiplatform kernel, we just want the highest value required by the
1520 # selected platforms.
1523 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1524 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1525 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1526 default 416 if ARCH_SUNXI
1527 default 392 if ARCH_U8500
1528 default 352 if ARCH_VT8500
1529 default 288 if ARCH_ROCKCHIP
1530 default 264 if MACH_H4700
1533 Maximum number of GPIOs in the system.
1535 If unsure, leave the default value.
1537 source kernel/Kconfig.preempt
1541 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1542 ARCH_S5PV210 || ARCH_EXYNOS4
1543 default 128 if SOC_AT91RM9200
1544 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1548 depends on HZ_FIXED = 0
1549 prompt "Timer frequency"
1573 default HZ_FIXED if HZ_FIXED != 0
1574 default 100 if HZ_100
1575 default 200 if HZ_200
1576 default 250 if HZ_250
1577 default 300 if HZ_300
1578 default 500 if HZ_500
1582 def_bool HIGH_RES_TIMERS
1584 config THUMB2_KERNEL
1585 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1586 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1587 default y if CPU_THUMBONLY
1589 select ARM_ASM_UNIFIED
1592 By enabling this option, the kernel will be compiled in
1593 Thumb-2 mode. A compiler/assembler that understand the unified
1594 ARM-Thumb syntax is needed.
1598 config THUMB2_AVOID_R_ARM_THM_JUMP11
1599 bool "Work around buggy Thumb-2 short branch relocations in gas"
1600 depends on THUMB2_KERNEL && MODULES
1603 Various binutils versions can resolve Thumb-2 branches to
1604 locally-defined, preemptible global symbols as short-range "b.n"
1605 branch instructions.
1607 This is a problem, because there's no guarantee the final
1608 destination of the symbol, or any candidate locations for a
1609 trampoline, are within range of the branch. For this reason, the
1610 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1611 relocation in modules at all, and it makes little sense to add
1614 The symptom is that the kernel fails with an "unsupported
1615 relocation" error when loading some modules.
1617 Until fixed tools are available, passing
1618 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1619 code which hits this problem, at the cost of a bit of extra runtime
1620 stack usage in some cases.
1622 The problem is described in more detail at:
1623 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1625 Only Thumb-2 kernels are affected.
1627 Unless you are sure your tools don't have this problem, say Y.
1629 config ARM_ASM_UNIFIED
1633 bool "Use the ARM EABI to compile the kernel"
1635 This option allows for the kernel to be compiled using the latest
1636 ARM ABI (aka EABI). This is only useful if you are using a user
1637 space environment that is also compiled with EABI.
1639 Since there are major incompatibilities between the legacy ABI and
1640 EABI, especially with regard to structure member alignment, this
1641 option also changes the kernel syscall calling convention to
1642 disambiguate both ABIs and allow for backward compatibility support
1643 (selected with CONFIG_OABI_COMPAT).
1645 To use this you need GCC version 4.0.0 or later.
1648 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1649 depends on AEABI && !THUMB2_KERNEL
1651 This option preserves the old syscall interface along with the
1652 new (ARM EABI) one. It also provides a compatibility layer to
1653 intercept syscalls that have structure arguments which layout
1654 in memory differs between the legacy ABI and the new ARM EABI
1655 (only for non "thumb" binaries). This option adds a tiny
1656 overhead to all syscalls and produces a slightly larger kernel.
1658 The seccomp filter system will not be available when this is
1659 selected, since there is no way yet to sensibly distinguish
1660 between calling conventions during filtering.
1662 If you know you'll be using only pure EABI user space then you
1663 can say N here. If this option is not selected and you attempt
1664 to execute a legacy ABI binary then the result will be
1665 UNPREDICTABLE (in fact it can be predicted that it won't work
1666 at all). If in doubt say N.
1668 config ARCH_HAS_HOLES_MEMORYMODEL
1671 config ARCH_SPARSEMEM_ENABLE
1674 config ARCH_SPARSEMEM_DEFAULT
1675 def_bool ARCH_SPARSEMEM_ENABLE
1677 config ARCH_SELECT_MEMORY_MODEL
1678 def_bool ARCH_SPARSEMEM_ENABLE
1680 config HAVE_ARCH_PFN_VALID
1681 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1683 config HAVE_GENERIC_RCU_GUP
1688 bool "High Memory Support"
1691 The address space of ARM processors is only 4 Gigabytes large
1692 and it has to accommodate user address space, kernel address
1693 space as well as some memory mapped IO. That means that, if you
1694 have a large amount of physical memory and/or IO, not all of the
1695 memory can be "permanently mapped" by the kernel. The physical
1696 memory that is not permanently mapped is called "high memory".
1698 Depending on the selected kernel/user memory split, minimum
1699 vmalloc space and actual amount of RAM, you may not need this
1700 option which should result in a slightly faster kernel.
1705 bool "Allocate 2nd-level pagetables from highmem"
1708 config HW_PERF_EVENTS
1709 bool "Enable hardware performance counter support for perf events"
1710 depends on PERF_EVENTS
1713 Enable hardware performance counter support for perf events. If
1714 disabled, perf events will use software events only.
1716 config SYS_SUPPORTS_HUGETLBFS
1720 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1724 config ARCH_WANT_GENERAL_HUGETLB
1729 config FORCE_MAX_ZONEORDER
1730 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1731 range 11 64 if ARCH_SHMOBILE_LEGACY
1732 default "12" if SOC_AM33XX
1733 default "9" if SA1111 || ARCH_EFM32
1736 The kernel memory allocator divides physically contiguous memory
1737 blocks into "zones", where each zone is a power of two number of
1738 pages. This option selects the largest power of two that the kernel
1739 keeps in the memory allocator. If you need to allocate very large
1740 blocks of physically contiguous memory, then you may need to
1741 increase this value.
1743 This config option is actually maximum order plus one. For example,
1744 a value of 11 means that the largest free memory block is 2^10 pages.
1746 config ALIGNMENT_TRAP
1748 depends on CPU_CP15_MMU
1749 default y if !ARCH_EBSA110
1750 select HAVE_PROC_CPU if PROC_FS
1752 ARM processors cannot fetch/store information which is not
1753 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1754 address divisible by 4. On 32-bit ARM processors, these non-aligned
1755 fetch/store instructions will be emulated in software if you say
1756 here, which has a severe performance impact. This is necessary for
1757 correct operation of some network protocols. With an IP-only
1758 configuration it is safe to say N, otherwise say Y.
1760 config UACCESS_WITH_MEMCPY
1761 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1763 default y if CPU_FEROCEON
1765 Implement faster copy_to_user and clear_user methods for CPU
1766 cores where a 8-word STM instruction give significantly higher
1767 memory write throughput than a sequence of individual 32bit stores.
1769 A possible side effect is a slight increase in scheduling latency
1770 between threads sharing the same address space if they invoke
1771 such copy operations with large buffers.
1773 However, if the CPU data cache is using a write-allocate mode,
1774 this option is unlikely to provide any performance gain.
1778 prompt "Enable seccomp to safely compute untrusted bytecode"
1780 This kernel feature is useful for number crunching applications
1781 that may need to compute untrusted bytecode during their
1782 execution. By using pipes or other transports made available to
1783 the process as file descriptors supporting the read/write
1784 syscalls, it's possible to isolate those applications in
1785 their own address space using seccomp. Once seccomp is
1786 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1787 and the task is only allowed to execute a few safe syscalls
1788 defined by each seccomp mode.
1801 bool "Xen guest support on ARM"
1802 depends on ARM && AEABI && OF
1803 depends on CPU_V7 && !CPU_V6
1804 depends on !GENERIC_ATOMIC64
1806 select ARCH_DMA_ADDR_T_64BIT
1810 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1817 bool "Flattened Device Tree support"
1820 select OF_EARLY_FLATTREE
1821 select OF_RESERVED_MEM
1823 Include support for flattened device tree machine descriptions.
1826 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1829 This is the traditional way of passing data to the kernel at boot
1830 time. If you are solely relying on the flattened device tree (or
1831 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1832 to remove ATAGS support from your kernel binary. If unsure,
1835 config DEPRECATED_PARAM_STRUCT
1836 bool "Provide old way to pass kernel parameters"
1839 This was deprecated in 2001 and announced to live on for 5 years.
1840 Some old boot loaders still use this way.
1842 # Compressed boot loader in ROM. Yes, we really want to ask about
1843 # TEXT and BSS so we preserve their values in the config files.
1844 config ZBOOT_ROM_TEXT
1845 hex "Compressed ROM boot loader base address"
1848 The physical address at which the ROM-able zImage is to be
1849 placed in the target. Platforms which normally make use of
1850 ROM-able zImage formats normally set this to a suitable
1851 value in their defconfig file.
1853 If ZBOOT_ROM is not enabled, this has no effect.
1855 config ZBOOT_ROM_BSS
1856 hex "Compressed ROM boot loader BSS address"
1859 The base address of an area of read/write memory in the target
1860 for the ROM-able zImage which must be available while the
1861 decompressor is running. It must be large enough to hold the
1862 entire decompressed kernel plus an additional 128 KiB.
1863 Platforms which normally make use of ROM-able zImage formats
1864 normally set this to a suitable value in their defconfig file.
1866 If ZBOOT_ROM is not enabled, this has no effect.
1869 bool "Compressed boot loader in ROM/flash"
1870 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1871 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1873 Say Y here if you intend to execute your compressed kernel image
1874 (zImage) directly from ROM or flash. If unsure, say N.
1876 config ARM_APPENDED_DTB
1877 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1880 With this option, the boot code will look for a device tree binary
1881 (DTB) appended to zImage
1882 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1884 This is meant as a backward compatibility convenience for those
1885 systems with a bootloader that can't be upgraded to accommodate
1886 the documented boot protocol using a device tree.
1888 Beware that there is very little in terms of protection against
1889 this option being confused by leftover garbage in memory that might
1890 look like a DTB header after a reboot if no actual DTB is appended
1891 to zImage. Do not leave this option active in a production kernel
1892 if you don't intend to always append a DTB. Proper passing of the
1893 location into r2 of a bootloader provided DTB is always preferable
1896 config ARM_ATAG_DTB_COMPAT
1897 bool "Supplement the appended DTB with traditional ATAG information"
1898 depends on ARM_APPENDED_DTB
1900 Some old bootloaders can't be updated to a DTB capable one, yet
1901 they provide ATAGs with memory configuration, the ramdisk address,
1902 the kernel cmdline string, etc. Such information is dynamically
1903 provided by the bootloader and can't always be stored in a static
1904 DTB. To allow a device tree enabled kernel to be used with such
1905 bootloaders, this option allows zImage to extract the information
1906 from the ATAG list and store it at run time into the appended DTB.
1909 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1910 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1912 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913 bool "Use bootloader kernel arguments if available"
1915 Uses the command-line options passed by the boot loader instead of
1916 the device tree bootargs property. If the boot loader doesn't provide
1917 any, the device tree bootargs property will be used.
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1920 bool "Extend with bootloader kernel arguments"
1922 The command-line arguments provided by the boot loader will be
1923 appended to the the device tree bootargs property.
1928 string "Default kernel command string"
1931 On some architectures (EBSA110 and CATS), there is currently no way
1932 for the boot loader to pass arguments to the kernel. For these
1933 architectures, you should supply some command-line options at build
1934 time by entering them here. As a minimum, you should specify the
1935 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1938 prompt "Kernel command line type" if CMDLINE != ""
1939 default CMDLINE_FROM_BOOTLOADER
1942 config CMDLINE_FROM_BOOTLOADER
1943 bool "Use bootloader kernel arguments if available"
1945 Uses the command-line options passed by the boot loader. If
1946 the boot loader doesn't provide any, the default kernel command
1947 string provided in CMDLINE will be used.
1949 config CMDLINE_EXTEND
1950 bool "Extend bootloader kernel arguments"
1952 The command-line arguments provided by the boot loader will be
1953 appended to the default kernel command string.
1955 config CMDLINE_FORCE
1956 bool "Always use the default kernel command string"
1958 Always use the default kernel command string, even if the boot
1959 loader passes other arguments to the kernel.
1960 This is useful if you cannot or don't want to change the
1961 command-line options your boot loader passes to the kernel.
1965 bool "Kernel Execute-In-Place from ROM"
1966 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1968 Execute-In-Place allows the kernel to run from non-volatile storage
1969 directly addressable by the CPU, such as NOR flash. This saves RAM
1970 space since the text section of the kernel is not loaded from flash
1971 to RAM. Read-write sections, such as the data section and stack,
1972 are still copied to RAM. The XIP kernel is not compressed since
1973 it has to run directly from flash, so it will take more space to
1974 store it. The flash address used to link the kernel object files,
1975 and for storing it, is configuration dependent. Therefore, if you
1976 say Y here, you must know the proper physical address where to
1977 store the kernel image depending on your own flash memory usage.
1979 Also note that the make target becomes "make xipImage" rather than
1980 "make zImage" or "make Image". The final kernel binary to put in
1981 ROM memory will be arch/arm/boot/xipImage.
1985 config XIP_PHYS_ADDR
1986 hex "XIP Kernel Physical Location"
1987 depends on XIP_KERNEL
1988 default "0x00080000"
1990 This is the physical address in your flash memory the kernel will
1991 be linked for and stored to. This address is dependent on your
1995 bool "Kexec system call (EXPERIMENTAL)"
1996 depends on (!SMP || PM_SLEEP_SMP)
1998 kexec is a system call that implements the ability to shutdown your
1999 current kernel, and to start another kernel. It is like a reboot
2000 but it is independent of the system firmware. And like a reboot
2001 you can start any kernel with it, not just Linux.
2003 It is an ongoing process to be certain the hardware in a machine
2004 is properly shutdown, so do not be surprised if this code does not
2005 initially work for you.
2008 bool "Export atags in procfs"
2009 depends on ATAGS && KEXEC
2012 Should the atags used to boot the kernel be exported in an "atags"
2013 file in procfs. Useful with kexec.
2016 bool "Build kdump crash kernel (EXPERIMENTAL)"
2018 Generate crash dump after being started by kexec. This should
2019 be normally only set in special crash dump kernels which are
2020 loaded in the main kernel with kexec-tools into a specially
2021 reserved region and then later executed after a crash by
2022 kdump/kexec. The crash dump kernel must be compiled to a
2023 memory address not used by the main kernel
2025 For more details see Documentation/kdump/kdump.txt
2027 config AUTO_ZRELADDR
2028 bool "Auto calculation of the decompressed kernel image address"
2030 ZRELADDR is the physical address where the decompressed kernel
2031 image will be placed. If AUTO_ZRELADDR is selected, the address
2032 will be determined at run-time by masking the current IP with
2033 0xf8000000. This assumes the zImage being placed in the first 128MB
2034 from start of memory.
2038 menu "CPU Power Management"
2040 source "drivers/cpufreq/Kconfig"
2042 source "drivers/cpuidle/Kconfig"
2046 menu "Floating point emulation"
2048 comment "At least one emulation must be selected"
2051 bool "NWFPE math emulation"
2052 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2054 Say Y to include the NWFPE floating point emulator in the kernel.
2055 This is necessary to run most binaries. Linux does not currently
2056 support floating point hardware so you need to say Y here even if
2057 your machine has an FPA or floating point co-processor podule.
2059 You may say N here if you are going to load the Acorn FPEmulator
2060 early in the bootup.
2063 bool "Support extended precision"
2064 depends on FPE_NWFPE
2066 Say Y to include 80-bit support in the kernel floating-point
2067 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2068 Note that gcc does not generate 80-bit operations by default,
2069 so in most cases this option only enlarges the size of the
2070 floating point emulator without any good reason.
2072 You almost surely want to say N here.
2075 bool "FastFPE math emulation (EXPERIMENTAL)"
2076 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2078 Say Y here to include the FAST floating point emulator in the kernel.
2079 This is an experimental much faster emulator which now also has full
2080 precision for the mantissa. It does not support any exceptions.
2081 It is very simple, and approximately 3-6 times faster than NWFPE.
2083 It should be sufficient for most programs. It may be not suitable
2084 for scientific calculations, but you have to check this for yourself.
2085 If you do not feel you need a faster FP emulation you should better
2089 bool "VFP-format floating point maths"
2090 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2092 Say Y to include VFP support code in the kernel. This is needed
2093 if your hardware includes a VFP unit.
2095 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2096 release notes and additional status information.
2098 Say N if your target does not have VFP hardware.
2106 bool "Advanced SIMD (NEON) Extension support"
2107 depends on VFPv3 && CPU_V7
2109 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2112 config KERNEL_MODE_NEON
2113 bool "Support for NEON in kernel mode"
2114 depends on NEON && AEABI
2116 Say Y to include support for NEON in kernel mode.
2120 menu "Userspace binary formats"
2122 source "fs/Kconfig.binfmt"
2126 menu "Power management options"
2128 source "kernel/power/Kconfig"
2130 config ARCH_SUSPEND_POSSIBLE
2131 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2132 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2135 config ARM_CPU_SUSPEND
2138 config ARCH_HIBERNATION_POSSIBLE
2141 default y if ARCH_SUSPEND_POSSIBLE
2145 source "net/Kconfig"
2147 source "drivers/Kconfig"
2149 source "drivers/firmware/Kconfig"
2153 source "arch/arm/Kconfig.debug"
2155 source "security/Kconfig"
2157 source "crypto/Kconfig"
2159 source "arch/arm/crypto/Kconfig"
2162 source "lib/Kconfig"
2164 source "arch/arm/kvm/Kconfig"