arch/arm/boot/dts/am43x-epos-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM43x EPOS EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pwm/pwm.h>
  17
  18 / {
  19         model = "TI AM43x EPOS EVM";
  20         compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
  21
  22         vmmcsd_fixed: fixedregulator-sd {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "vmmcsd_fixed";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27                 enable-active-high;
  28         };
  29
  30         am43xx_pinmux: pinmux@44e10800 {
  31                 cpsw_default: cpsw_default {
  32                         pinctrl-single,pins = <
  33                                 /* Slave 1 */
  34                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
  35                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxerr.rmii1_rxerr */
  36                                 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
  37                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxdv.rmii1_rxdv */
  38                                 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
  39                                 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
  40                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd1.rmii1_rxd1 */
  41                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd0.rmii1_rxd0 */
  42                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk.rmii1_refclk */
  43                         >;
  44                 };
  45
  46                 cpsw_sleep: cpsw_sleep {
  47                         pinctrl-single,pins = <
  48                                 /* Slave 1 reset value */
  49                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  50                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  51                                 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  52                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  53                                 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  54                                 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  55                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  56                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  57                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  58                         >;
  59                 };
  60
  61                 davinci_mdio_default: davinci_mdio_default {
  62                         pinctrl-single,pins = <
  63                                 /* MDIO */
  64                                 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
  65                                 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
  66                         >;
  67                 };
  68
  69                 davinci_mdio_sleep: davinci_mdio_sleep {
  70                         pinctrl-single,pins = <
  71                                 /* MDIO reset value */
  72                                 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  73                                 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  74                         >;
  75                 };
  76
  77                 i2c0_pins: pinmux_i2c0_pins {
  78                         pinctrl-single,pins = <
  79                                 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
  80                                 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
  81                         >;
  82                 };
  83
  84                 nand_flash_x8: nand_flash_x8 {
  85                         pinctrl-single,pins = <
  86                                 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.SELQSPIorNAND/GPIO */
  87                                 0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
  88                                 0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
  89                                 0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
  90                                 0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
  91                                 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
  92                                 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
  93                                 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
  94                                 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
  95                                 0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
  96                                 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
  97                                 0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
  98                                 0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
  99                                 0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 100                                 0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 101                                 0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 102                         >;
 103                 };
 104
 105                 ecap0_pins: backlight_pins {
 106                         pinctrl-single,pins = <
 107                                 0x164 MUX_MODE0         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 108                         >;
 109                 };
 110
 111                 i2c2_pins: pinmux_i2c2_pins {
 112                         pinctrl-single,pins = <
 113                                 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
 114                                 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
 115                         >;
 116                 };
 117
 118                 spi0_pins: pinmux_spi0_pins {
 119                         pinctrl-single,pins = <
 120                                 0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
 121                                 0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
 122                                 0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
 123                                 0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
 124                         >;
 125                 };
 126
 127                 spi1_pins: pinmux_spi1_pins {
 128                         pinctrl-single,pins = <
 129                                 0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
 130                                 0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
 131                                 0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
 132                                 0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
 133                         >;
 134                 };
 135
 136                 mmc1_pins: pinmux_mmc1_pins {
 137                         pinctrl-single,pins = <
 138                                 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 139                         >;
 140                 };
 141
 142                 qspi1_default: qspi1_default {
 143                         pinctrl-single,pins = <
 144                                 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
 145                                 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
 146                                 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
 147                                 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
 148                                 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
 149                                 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
 150                         >;
 151                 };
 152
 153                 pixcir_ts_pins: pixcir_ts_pins {
 154                         pinctrl-single,pins = <
 155                                 0x44 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_a1.gpio1_17 */
 156                         >;
 157                 };
 158
 159                 hdq_pins: pinmux_hdq_pins {
 160                         pinctrl-single,pins = <
 161                                 0x234 (PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
 162                         >;
 163                 };
 164         };
 165
 166         matrix_keypad: matrix_keypad@0 {
 167                         compatible = "gpio-matrix-keypad";
 168                         debounce-delay-ms = <5>;
 169                         col-scan-delay-us = <2>;
 170
 171                         row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
 172                                      &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
 173                                      &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
 174                                      &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
 175
 176                         col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
 177                                      &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
 178                                      &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
 179                                      &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
 180
 181                         linux,keymap = <0x00000201      /* P1 */
 182                                 0x01000204      /* P4 */
 183                                 0x02000207      /* P7 */
 184                                 0x0300020a      /* NUMERIC_STAR */
 185                                 0x00010202      /* P2 */
 186                                 0x01010205      /* P5 */
 187                                 0x02010208      /* P8 */
 188                                 0x03010200      /* P0 */
 189                                 0x00020203      /* P3 */
 190                                 0x01020206      /* P6 */
 191                                 0x02020209      /* P9 */
 192                                 0x0302020b      /* NUMERIC_POUND */
 193                                 0x00030067      /* UP */
 194                                 0x0103006a      /* RIGHT */
 195                                 0x0203006c      /* DOWN */
 196                                 0x03030069>;    /* LEFT */
 197                 };
 198
 199         backlight {
 200                 compatible = "pwm-backlight";
 201                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
 202                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 203                 default-brightness-level = <8>;
 204         };
 205 };
 206
 207 &mmc1 {
 208         status = "okay";
 209         vmmc-supply = <&vmmcsd_fixed>;
 210         bus-width = <4>;
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&mmc1_pins>;
 213         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 214 };
 215
 216 &mac {
 217         pinctrl-names = "default", "sleep";
 218         pinctrl-0 = <&cpsw_default>;
 219         pinctrl-1 = <&cpsw_sleep>;
 220         status = "okay";
 221 };
 222
 223 &davinci_mdio {
 224         pinctrl-names = "default", "sleep";
 225         pinctrl-0 = <&davinci_mdio_default>;
 226         pinctrl-1 = <&davinci_mdio_sleep>;
 227         status = "okay";
 228 };
 229
 230 &cpsw_emac0 {
 231         phy_id = <&davinci_mdio>, <16>;
 232         phy-mode = "rmii";
 233 };
 234
 235 &cpsw_emac1 {
 236         phy_id = <&davinci_mdio>, <1>;
 237         phy-mode = "rmii";
 238 };
 239
 240 &i2c0 {
 241         status = "okay";
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&i2c0_pins>;
 244
 245         at24@50 {
 246                 compatible = "at24,24c256";
 247                 pagesize = <64>;
 248                 reg = <0x50>;
 249         };
 250
 251         pixcir_ts@5c {
 252                 compatible = "pixcir,pixcir_tangoc";
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&pixcir_ts_pins>;
 255                 reg = <0x5c>;
 256                 interrupt-parent = <&gpio1>;
 257                 interrupts = <17 0>;
 258
 259                 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 260
 261                 x-size = <1024>;
 262                 y-size = <600>;
 263         };
 264 };
 265
 266 &i2c2 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&i2c2_pins>;
 269         status = "okay";
 270 };
 271
 272 &gpio0 {
 273         status = "okay";
 274 };
 275
 276 &gpio1 {
 277         status = "okay";
 278 };
 279
 280 &gpio2 {
 281         status = "okay";
 282 };
 283
 284 &gpio3 {
 285         status = "okay";
 286 };
 287
 288 &elm {
 289         status = "okay";
 290 };
 291
 292 &gpmc {
 293         status = "okay";
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&nand_flash_x8>;
 296         ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
 297         nand@0,0 {
 298                 reg = <0 0 0>; /* CS0, offset 0 */
 299                 ti,nand-ecc-opt = "bch8";
 300                 ti,elm-id = <&elm>;
 301                 nand-bus-width = <8>;
 302                 gpmc,device-width = <1>;
 303                 gpmc,sync-clk-ps = <0>;
 304                 gpmc,cs-on-ns = <0>;
 305                 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
 306                 gpmc,cs-wr-off-ns = <40>;
 307                 gpmc,adv-on-ns = <0>;  /* cs-on-ns */
 308                 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
 309                 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
 310                 gpmc,we-on-ns = <0>;   /* cs-on-ns */
 311                 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
 312                 gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
 313                 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
 314                 gpmc,access-ns = <30>; /* tCEA + 4*/
 315                 gpmc,rd-cycle-ns = <40>;
 316                 gpmc,wr-cycle-ns = <40>;
 317                 gpmc,wait-on-read = "true";
 318                 gpmc,wait-on-write = "true";
 319                 gpmc,bus-turnaround-ns = <0>;
 320                 gpmc,cycle2cycle-delay-ns = <0>;
 321                 gpmc,clk-activation-ns = <0>;
 322                 gpmc,wait-monitoring-ns = <0>;
 323                 gpmc,wr-access-ns = <40>;
 324                 gpmc,wr-data-mux-bus-ns = <0>;
 325                 /* MTD partition table */
 326                 /* All SPL-* partitions are sized to minimal length
 327                  * which can be independently programmable. For
 328                  * NAND flash this is equal to size of erase-block */
 329                 #address-cells = <1>;
 330                 #size-cells = <1>;
 331                 partition@0 {
 332                         label = "NAND.SPL";
 333                         reg = <0x00000000 0x00040000>;
 334                 };
 335                 partition@1 {
 336                         label = "NAND.SPL.backup1";
 337                         reg = <0x00040000 0x00040000>;
 338                 };
 339                 partition@2 {
 340                         label = "NAND.SPL.backup2";
 341                         reg = <0x00080000 0x00040000>;
 342                 };
 343                 partition@3 {
 344                         label = "NAND.SPL.backup3";
 345                         reg = <0x000C0000 0x00040000>;
 346                 };
 347                 partition@4 {
 348                         label = "NAND.u-boot-spl-os";
 349                         reg = <0x00100000 0x00080000>;
 350                 };
 351                 partition@5 {
 352                         label = "NAND.u-boot";
 353                         reg = <0x00180000 0x00100000>;
 354                 };
 355                 partition@6 {
 356                         label = "NAND.u-boot-env";
 357                         reg = <0x00280000 0x00040000>;
 358                 };
 359                 partition@7 {
 360                         label = "NAND.u-boot-env.backup1";
 361                         reg = <0x002C0000 0x00040000>;
 362                 };
 363                 partition@8 {
 364                         label = "NAND.kernel";
 365                         reg = <0x00300000 0x00700000>;
 366                 };
 367                 partition@9 {
 368                         label = "NAND.file-system";
 369                         reg = <0x00a00000 0x1f600000>;
 370                 };
 371         };
 372 };
 373
 374 &epwmss0 {
 375         status = "okay";
 376 };
 377
 378 &ecap0 {
 379                 status = "okay";
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&ecap0_pins>;
 382 };
 383
 384 &spi0 {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&spi0_pins>;
 387         status = "okay";
 388 };
 389
 390 &spi1 {
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&spi1_pins>;
 393         status = "okay";
 394 };
 395
 396 &usb2_phy1 {
 397         status = "okay";
 398 };
 399
 400 &usb1 {
 401         dr_mode = "peripheral";
 402         status = "okay";
 403 };
 404
 405 &usb2_phy2 {
 406         status = "okay";
 407 };
 408
 409 &usb2 {
 410         dr_mode = "host";
 411         status = "okay";
 412 };
 413
 414 &qspi {
 415         status = "okay";
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&qspi1_default>;
 418
 419         spi-max-frequency = <48000000>;
 420         m25p80@0 {
 421                 compatible = "mx66l51235l";
 422                 spi-max-frequency = <48000000>;
 423                 reg = <0>;
 424                 spi-cpol;
 425                 spi-cpha;
 426                 spi-tx-bus-width = <1>;
 427                 spi-rx-bus-width = <4>;
 428                 #address-cells = <1>;
 429                 #size-cells = <1>;
 430
 431                 /* MTD partition table.
 432                  * The ROM checks the first 512KiB
 433                  * for a valid file to boot(XIP).
 434                  */
 435                 partition@0 {
 436                         label = "QSPI.U_BOOT";
 437                         reg = <0x00000000 0x000080000>;
 438                 };
 439                 partition@1 {
 440                         label = "QSPI.U_BOOT.backup";
 441                         reg = <0x00080000 0x00080000>;
 442                 };
 443                 partition@2 {
 444                         label = "QSPI.U-BOOT-SPL_OS";
 445                         reg = <0x00100000 0x00010000>;
 446                 };
 447                 partition@3 {
 448                         label = "QSPI.U_BOOT_ENV";
 449                         reg = <0x00110000 0x00010000>;
 450                 };
 451                 partition@4 {
 452                         label = "QSPI.U-BOOT-ENV.backup";
 453                         reg = <0x00120000 0x00010000>;
 454                 };
 455                 partition@5 {
 456                         label = "QSPI.KERNEL";
 457                         reg = <0x00130000 0x0800000>;
 458                 };
 459                 partition@6 {
 460                         label = "QSPI.FILESYSTEM";
 461                         reg = <0x00930000 0x36D0000>;
 462                 };
 463         };
 464 };
 465
 466 &hdq {
 467         status = "okay";
 468         pinctrl-names = "default";
 469         pinctrl-0 = <&hdq_pins>;
 470 };