2 * Copyright 2015 Linaro Ltd
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "skeleton.dtsi"
29 model = "ARM RealView PB11MPcore";
30 compatible = "arm,realview-pb11mp";
35 serial0 = &pb11mp_serial0;
36 serial1 = &pb11mp_serial1;
37 serial2 = &pb11mp_serial2;
38 serial3 = &pb11mp_serial3;
43 * The PB11MPCore has 512 MiB memory @ 0x70000000
44 * and the first 256 are also remapped @ 0x00000000
46 reg = <0x70000000 0x20000000>;
52 enable-method = "arm,realview-smp";
56 compatible = "arm,arm11mpcore";
58 next-level-cache = <&L2>;
63 compatible = "arm,arm11mpcore";
65 next-level-cache = <&L2>;
70 compatible = "arm,arm11mpcore";
72 next-level-cache = <&L2>;
77 compatible = "arm,arm11mpcore";
79 next-level-cache = <&L2>;
83 /* Primary TestChip GIC synthesized with the CPU */
84 intc_tc11mp: interrupt-controller@1f000100 {
85 compatible = "arm,tc11mp-gic";
86 #interrupt-cells = <3>;
89 reg = <0x1f001000 0x1000>,
94 compatible = "arm,l220-cache";
95 reg = <0x1f002000 0x1000>;
96 interrupt-parent = <&intc_tc11mp>;
97 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
98 <0 30 IRQ_TYPE_LEVEL_HIGH>,
99 <0 31 IRQ_TYPE_LEVEL_HIGH>;
103 * Override default cache size, sets and
104 * associativity as these may be erroneously set
105 * up by boot loader(s), probably for safety
106 * since th outer sync operation can cause the
107 * cache to hang unless disabled.
109 cache-size = <1048576>; // 1MB
111 cache-line-size = <32>;
114 arm,outer-sync-disable;
118 compatible = "arm,arm11mp-scu";
119 reg = <0x1f000000 0x100>;
123 compatible = "arm,arm11mp-twd-timer";
124 reg = <0x1f000600 0x20>;
125 interrupt-parent = <&intc_tc11mp>;
126 interrupts = <1 13 0xf04>;
130 compatible = "arm,arm11mp-twd-wdt";
131 reg = <0x1f000620 0x20>;
132 interrupt-parent = <&intc_tc11mp>;
133 interrupts = <1 14 0xf04>;
136 /* PMU with one IRQ line per core */
138 compatible = "arm,arm11mpcore-pmu";
139 interrupt-parent = <&intc_tc11mp>;
140 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
141 <0 18 IRQ_TYPE_LEVEL_HIGH>,
142 <0 19 IRQ_TYPE_LEVEL_HIGH>,
143 <0 20 IRQ_TYPE_LEVEL_HIGH>;
144 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
147 /* The voltage to the MMC card is hardwired at 3.3V */
148 vmmc: fixedregulator@0 {
149 compatible = "regulator-fixed";
150 regulator-name = "vmmc";
151 regulator-min-microvolt = <3300000>;
152 regulator-max-microvolt = <3300000>;
156 veth: fixedregulator@0 {
157 compatible = "regulator-fixed";
158 regulator-name = "veth";
159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>;
164 xtal24mhz: xtal24mhz@24M {
166 compatible = "fixed-clock";
167 clock-frequency = <24000000>;
170 refclk32khz: refclk32khz {
171 compatible = "fixed-clock";
173 clock-frequency = <32768>;
178 compatible = "fixed-factor-clock";
181 clocks = <&xtal24mhz>;
186 compatible = "fixed-factor-clock";
189 clocks = <&xtal24mhz>;
194 compatible = "fixed-factor-clock";
197 clocks = <&xtal24mhz>;
202 compatible = "fixed-factor-clock";
205 clocks = <&xtal24mhz>;
208 uartclk: uartclk@24M {
210 compatible = "fixed-factor-clock";
213 clocks = <&xtal24mhz>;
216 wdogclk: wdogclk@24M {
218 compatible = "fixed-factor-clock";
221 clocks = <&xtal24mhz>;
224 /* FIXME: this actually hangs off the PLL clocks */
227 compatible = "fixed-clock";
228 clock-frequency = <0>;
232 /* 2 * 32MiB NOR Flash memory */
233 compatible = "arm,vexpress-flash", "cfi-flash";
234 reg = <0x40000000 0x04000000>;
239 // 2 * 32MiB NOR Flash memory
240 compatible = "arm,vexpress-flash", "cfi-flash";
241 reg = <0x44000000 0x04000000>;
246 #address-cells = <1>;
248 compatible = "arm,realview-pb11mp-soc", "simple-bus";
249 regmap = <&pb11mp_syscon>;
252 pb11mp_syscon: syscon@10000000 {
253 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
254 reg = <0x10000000 0x1000>;
257 compatible = "register-bit-led";
260 label = "versatile:0";
261 linux,default-trigger = "heartbeat";
262 default-state = "on";
265 compatible = "register-bit-led";
268 label = "versatile:1";
269 linux,default-trigger = "mmc0";
270 default-state = "off";
273 compatible = "register-bit-led";
276 label = "versatile:2";
277 linux,default-trigger = "cpu0";
278 default-state = "off";
281 compatible = "register-bit-led";
284 label = "versatile:3";
285 linux,default-trigger = "cpu1";
286 default-state = "off";
289 compatible = "register-bit-led";
292 label = "versatile:4";
293 linux,default-trigger = "cpu2";
294 default-state = "off";
297 compatible = "register-bit-led";
300 label = "versatile:5";
301 linux,default-trigger = "cpu3";
302 default-state = "off";
305 compatible = "register-bit-led";
308 label = "versatile:6";
309 default-state = "off";
312 compatible = "register-bit-led";
315 label = "versatile:7";
316 default-state = "off";
320 compatible = "arm,syscon-icst307";
322 lock-offset = <0x20>;
324 clocks = <&xtal24mhz>;
327 compatible = "arm,syscon-icst307";
329 lock-offset = <0x20>;
331 clocks = <&xtal24mhz>;
334 compatible = "arm,syscon-icst307";
336 lock-offset = <0x20>;
338 clocks = <&xtal24mhz>;
341 compatible = "arm,syscon-icst307";
343 lock-offset = <0x20>;
345 clocks = <&xtal24mhz>;
348 compatible = "arm,syscon-icst307";
350 lock-offset = <0x20>;
352 clocks = <&xtal24mhz>;
355 compatible = "arm,syscon-icst307";
357 lock-offset = <0x20>;
359 clocks = <&xtal24mhz>;
362 compatible = "arm,syscon-icst307";
364 lock-offset = <0x20>;
366 clocks = <&xtal24mhz>;
370 sp810_syscon: sysctl@10001000 {
371 compatible = "arm,sp810", "arm,primecell";
372 reg = <0x10001000 0x1000>;
373 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
374 clock-names = "refclk", "timclk", "apb_pclk";
376 clock-output-names = "timerclk0",
380 assigned-clocks = <&sp810_syscon 0>,
384 assigned-clock-parents = <&timclk>,
391 #address-cells = <1>;
393 compatible = "arm,versatile-i2c";
394 reg = <0x10002000 0x1000>;
397 compatible = "dallas,ds1338";
402 aaci: aaci@10004000 {
403 compatible = "arm,pl041", "arm,primecell";
404 reg = <0x10004000 0x1000>;
405 interrupt-parent = <&intc_tc11mp>;
406 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
408 clock-names = "apb_pclk";
411 mci: mmcsd@10005000 {
412 compatible = "arm,pl18x", "arm,primecell";
413 reg = <0x10005000 0x1000>;
414 interrupt-parent = <&intc_tc11mp>;
415 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
416 <0 15 IRQ_TYPE_LEVEL_HIGH>;
417 /* Due to frequent FIFO overruns, use just 500 kHz */
418 max-frequency = <500000>;
422 clocks = <&mclk>, <&pclk>;
423 clock-names = "mclk", "apb_pclk";
424 vmmc-supply = <&vmmc>;
425 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
426 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
430 compatible = "arm,pl050", "arm,primecell";
431 reg = <0x10006000 0x1000>;
432 interrupt-parent = <&intc_tc11mp>;
433 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&kmiclk>, <&pclk>;
435 clock-names = "KMIREFCLK", "apb_pclk";
439 compatible = "arm,pl050", "arm,primecell";
440 reg = <0x10007000 0x1000>;
441 interrupt-parent = <&intc_tc11mp>;
442 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&kmiclk>, <&pclk>;
444 clock-names = "KMIREFCLK", "apb_pclk";
447 pb11mp_serial0: serial@10009000 {
448 compatible = "arm,pl011", "arm,primecell";
449 reg = <0x10009000 0x1000>;
450 interrupt-parent = <&intc_tc11mp>;
451 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&uartclk>, <&pclk>;
453 clock-names = "uartclk", "apb_pclk";
456 pb11mp_serial1: serial@1000a000 {
457 compatible = "arm,pl011", "arm,primecell";
458 reg = <0x1000a000 0x1000>;
459 interrupt-parent = <&intc_tc11mp>;
460 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&uartclk>, <&pclk>;
462 clock-names = "uartclk", "apb_pclk";
465 pb11mp_serial2: serial@1000b000 {
466 compatible = "arm,pl011", "arm,primecell";
467 reg = <0x1000b000 0x1000>;
468 interrupt-parent = <&intc_pb11mp>;
469 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&uartclk>, <&pclk>;
471 clock-names = "uartclk", "apb_pclk";
474 pb11mp_serial3: serial@1000c000 {
475 compatible = "arm,pl011", "arm,primecell";
476 reg = <0x1000c000 0x1000>;
477 interrupt-parent = <&intc_pb11mp>;
478 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&uartclk>, <&pclk>;
480 clock-names = "uartclk", "apb_pclk";
484 compatible = "arm,pl022", "arm,primecell";
485 reg = <0x1000d000 0x1000>;
486 interrupt-parent = <&intc_pb11mp>;
487 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&sspclk>, <&pclk>;
489 clock-names = "SSPCLK", "apb_pclk";
493 compatible = "arm,sp805", "arm,primecell";
494 reg = <0x1000f000 0x1000>;
495 interrupt-parent = <&intc_pb11mp>;
496 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&wdogclk>, <&pclk>;
498 clock-names = "wdogclk", "apb_pclk";
503 compatible = "arm,sp805", "arm,primecell";
504 reg = <0x10010000 0x1000>;
505 interrupt-parent = <&intc_pb11mp>;
506 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&wdogclk>, <&pclk>;
508 clock-names = "wdogclk", "apb_pclk";
511 timer01: timer@10011000 {
512 compatible = "arm,sp804", "arm,primecell";
513 reg = <0x10011000 0x1000>;
514 interrupt-parent = <&intc_tc11mp>;
515 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
516 arm,sp804-has-irq = <1>;
517 clocks = <&sp810_syscon 0>,
520 clock-names = "timerclk0",
525 timer23: timer@10012000 {
526 compatible = "arm,sp804", "arm,primecell";
527 reg = <0x10012000 0x1000>;
528 interrupt-parent = <&intc_tc11mp>;
529 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
530 arm,sp804-has-irq = <1>;
531 clocks = <&sp810_syscon 2>,
534 clock-names = "timerclk2",
539 gpio0: gpio@10013000 {
540 compatible = "arm,pl061", "arm,primecell";
541 reg = <0x10013000 0x1000>;
543 interrupt-parent = <&intc_pb11mp>;
544 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
549 clock-names = "apb_pclk";
552 gpio1: gpio@10014000 {
553 compatible = "arm,pl061", "arm,primecell";
554 reg = <0x10014000 0x1000>;
556 interrupt-parent = <&intc_pb11mp>;
557 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
562 clock-names = "apb_pclk";
565 gpio2: gpio@10015000 {
566 compatible = "arm,pl061", "arm,primecell";
567 reg = <0x10015000 0x1000>;
569 interrupt-parent = <&intc_pb11mp>;
570 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-controller;
573 #interrupt-cells = <2>;
575 clock-names = "apb_pclk";
579 compatible = "arm,pl031", "arm,primecell";
580 reg = <0x10017000 0x1000>;
581 interrupt-parent = <&intc_tc11mp>;
582 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
584 clock-names = "apb_pclk";
587 timer45: timer@10018000 {
588 compatible = "arm,sp804", "arm,primecell";
589 reg = <0x10018000 0x1000>;
590 clocks = <&timclk>, <&pclk>;
591 clock-names = "timer", "apb_pclk";
595 timer67: timer@10019000 {
596 compatible = "arm,sp804", "arm,primecell";
597 reg = <0x10019000 0x1000>;
598 clocks = <&timclk>, <&pclk>;
599 clock-names = "timer", "apb_pclk";
605 compatible = "arm,pl111", "arm,primecell";
606 reg = <0x10020000 0x1000>;
607 interrupt-parent = <&intc_pb11mp>;
608 interrupt-names = "combined";
609 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&oscclk4>, <&pclk>;
611 clock-names = "clcdclk", "apb_pclk";
612 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
615 clcd_pads: endpoint {
616 remote-endpoint = <&clcd_panel>;
617 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
622 compatible = "panel-dpi";
625 clcd_panel: endpoint {
626 remote-endpoint = <&clcd_pads>;
631 clock-frequency = <63500127>;
645 * This GIC on the Platform Baseboard is cascaded off the
648 intc_pb11mp: interrupt-controller@1e000000 {
649 compatible = "arm,arm11mp-gic";
650 #interrupt-cells = <3>;
651 #address-cells = <1>;
652 interrupt-controller;
653 reg = <0x1e001000 0x1000>,
655 interrupt-parent = <&intc_tc11mp>;
656 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
659 /* SMSC 9118 ethernet with PHY and EEPROM */
661 compatible = "smsc,lan9118", "smsc,lan9115";
662 reg = <0x4e000000 0x10000>;
663 interrupt-parent = <&intc_tc11mp>;
664 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
667 smsc,irq-active-high;
669 vdd33a-supply = <&veth>;
670 vddvario-supply = <&veth>;
674 compatible = "nxp,usb-isp1761";
675 reg = <0x4f000000 0x20000>;
676 interrupt-parent = <&intc_tc11mp>;
677 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;