arch/arm/boot/dts/armada-375.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 375 family SoC
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  19
  20 / {
  21         model = "Marvell Armada 375 family SoC";
  22         compatible = "marvell,armada375";
  23
  24         aliases {
  25                 gpio0 = &gpio0;
  26                 gpio1 = &gpio1;
  27                 gpio2 = &gpio2;
  28                 ethernet0 = &eth0;
  29                 ethernet1 = &eth1;
  30         };
  31
  32         clocks {
  33                 /* 2 GHz fixed main PLL */
  34                 mainpll: mainpll {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <2000000000>;
  38                 };
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44                 enable-method = "marvell,armada-375-smp";
  45
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <0>;
  50                 };
  51                 cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         reg = <1>;
  55                 };
  56         };
  57
  58         soc {
  59                 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
  60                 #address-cells = <2>;
  61                 #size-cells = <1>;
  62                 controller = <&mbusc>;
  63                 interrupt-parent = <&gic>;
  64                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  65                 pcie-io-aperture  = <0xe8000000 0x100000>;
  66
  67                 bootrom {
  68                         compatible = "marvell,bootrom";
  69                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  70                 };
  71
  72                 devbus-bootcs {
  73                         compatible = "marvell,mvebu-devbus";
  74                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  75                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  76                         #address-cells = <1>;
  77                         #size-cells = <1>;
  78                         clocks = <&coreclk 0>;
  79                         status = "disabled";
  80                 };
  81
  82                 devbus-cs0 {
  83                         compatible = "marvell,mvebu-devbus";
  84                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  85                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         clocks = <&coreclk 0>;
  89                         status = "disabled";
  90                 };
  91
  92                 devbus-cs1 {
  93                         compatible = "marvell,mvebu-devbus";
  94                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  95                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         clocks = <&coreclk 0>;
  99                         status = "disabled";
 100                 };
 101
 102                 devbus-cs2 {
 103                         compatible = "marvell,mvebu-devbus";
 104                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 105                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         clocks = <&coreclk 0>;
 109                         status = "disabled";
 110                 };
 111
 112                 devbus-cs3 {
 113                         compatible = "marvell,mvebu-devbus";
 114                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 115                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 116                         #address-cells = <1>;
 117                         #size-cells = <1>;
 118                         clocks = <&coreclk 0>;
 119                         status = "disabled";
 120                 };
 121
 122                 internal-regs {
 123                         compatible = "simple-bus";
 124                         #address-cells = <1>;
 125                         #size-cells = <1>;
 126                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 127
 128                         L2: cache-controller@8000 {
 129                                 compatible = "arm,pl310-cache";
 130                                 reg = <0x8000 0x1000>;
 131                                 cache-unified;
 132                                 cache-level = <2>;
 133                         };
 134
 135                         scu@c000 {
 136                                 compatible = "arm,cortex-a9-scu";
 137                                 reg = <0xc000 0x58>;
 138                         };
 139
 140                         timer@c600 {
 141                                 compatible = "arm,cortex-a9-twd-timer";
 142                                 reg = <0xc600 0x20>;
 143                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 144                                 clocks = <&coreclk 2>;
 145                         };
 146
 147                         gic: interrupt-controller@d000 {
 148                                 compatible = "arm,cortex-a9-gic";
 149                                 #interrupt-cells = <3>;
 150                                 #size-cells = <0>;
 151                                 interrupt-controller;
 152                                 reg = <0xd000 0x1000>,
 153                                       <0xc100 0x100>;
 154                         };
 155
 156                         mdio {
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                                 compatible = "marvell,orion-mdio";
 160                                 reg = <0xc0054 0x4>;
 161                                 clocks = <&gateclk 19>;
 162                         };
 163
 164                         /* Network controller */
 165                         ethernet@f0000 {
 166                                 compatible = "marvell,armada-375-pp2";
 167                                 reg = <0xf0000 0xa000>, /* Packet Processor regs */
 168                                       <0xc0000 0x3060>, /* LMS regs */
 169                                       <0xc4000 0x100>,  /* eth0 regs */
 170                                       <0xc5000 0x100>;  /* eth1 regs */
 171                                 clocks = <&gateclk 3>, <&gateclk 19>;
 172                                 clock-names = "pp_clk", "gop_clk";
 173                                 status = "disabled";
 174
 175                                 eth0: eth0@c4000 {
 176                                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 177                                         port-id = <0>;
 178                                         status = "disabled";
 179                                 };
 180
 181                                 eth1: eth1@c5000 {
 182                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 183                                         port-id = <1>;
 184                                         status = "disabled";
 185                                 };
 186                         };
 187
 188                         rtc@10300 {
 189                                 compatible = "marvell,orion-rtc";
 190                                 reg = <0x10300 0x20>;
 191                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 192                         };
 193
 194                         spi0: spi@10600 {
 195                                 compatible = "marvell,orion-spi";
 196                                 reg = <0x10600 0x50>;
 197                                 #address-cells = <1>;
 198                                 #size-cells = <0>;
 199                                 cell-index = <0>;
 200                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 201                                 clocks = <&coreclk 0>;
 202                                 status = "disabled";
 203                         };
 204
 205                         spi1: spi@10680 {
 206                                 compatible = "marvell,orion-spi";
 207                                 reg = <0x10680 0x50>;
 208                                 #address-cells = <1>;
 209                                 #size-cells = <0>;
 210                                 cell-index = <1>;
 211                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 212                                 clocks = <&coreclk 0>;
 213                                 status = "disabled";
 214                         };
 215
 216                         i2c0: i2c@11000 {
 217                                 compatible = "marvell,mv64xxx-i2c";
 218                                 reg = <0x11000 0x20>;
 219                                 #address-cells = <1>;
 220                                 #size-cells = <0>;
 221                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 222                                 timeout-ms = <1000>;
 223                                 clocks = <&coreclk 0>;
 224                                 status = "disabled";
 225                         };
 226
 227                         i2c1: i2c@11100 {
 228                                 compatible = "marvell,mv64xxx-i2c";
 229                                 reg = <0x11100 0x20>;
 230                                 #address-cells = <1>;
 231                                 #size-cells = <0>;
 232                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 233                                 timeout-ms = <1000>;
 234                                 clocks = <&coreclk 0>;
 235                                 status = "disabled";
 236                         };
 237
 238                         serial@12000 {
 239                                 compatible = "snps,dw-apb-uart";
 240                                 reg = <0x12000 0x100>;
 241                                 reg-shift = <2>;
 242                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 243                                 reg-io-width = <1>;
 244                                 clocks = <&coreclk 0>;
 245                                 status = "disabled";
 246                         };
 247
 248                         serial@12100 {
 249                                 compatible = "snps,dw-apb-uart";
 250                                 reg = <0x12100 0x100>;
 251                                 reg-shift = <2>;
 252                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 253                                 reg-io-width = <1>;
 254                                 clocks = <&coreclk 0>;
 255                                 status = "disabled";
 256                         };
 257
 258                         pinctrl {
 259                                 compatible = "marvell,mv88f6720-pinctrl";
 260                                 reg = <0x18000 0x24>;
 261
 262                                 i2c0_pins: i2c0-pins {
 263                                         marvell,pins = "mpp14",  "mpp15";
 264                                         marvell,function = "i2c0";
 265                                 };
 266
 267                                 i2c1_pins: i2c1-pins {
 268                                         marvell,pins = "mpp61",  "mpp62";
 269                                         marvell,function = "i2c1";
 270                                 };
 271
 272                                 nand_pins: nand-pins {
 273                                         marvell,pins = "mpp0", "mpp1", "mpp2",
 274                                                 "mpp3", "mpp4", "mpp5",
 275                                                 "mpp6", "mpp7", "mpp8",
 276                                                 "mpp9", "mpp10", "mpp11",
 277                                                 "mpp12", "mpp13";
 278                                         marvell,function = "nand";
 279                                 };
 280
 281                                 sdio_pins: sdio-pins {
 282                                         marvell,pins = "mpp24",  "mpp25", "mpp26",
 283                                                      "mpp27", "mpp28", "mpp29";
 284                                         marvell,function = "sd";
 285                                 };
 286
 287                                 spi0_pins: spi0-pins {
 288                                         marvell,pins = "mpp0",  "mpp1", "mpp4",
 289                                                      "mpp5", "mpp8", "mpp9";
 290                                         marvell,function = "spi0";
 291                                 };
 292                         };
 293
 294                         gpio0: gpio@18100 {
 295                                 compatible = "marvell,orion-gpio";
 296                                 reg = <0x18100 0x40>;
 297                                 ngpios = <32>;
 298                                 gpio-controller;
 299                                 #gpio-cells = <2>;
 300                                 interrupt-controller;
 301                                 #interrupt-cells = <2>;
 302                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 303                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 304                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 305                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 306                         };
 307
 308                         gpio1: gpio@18140 {
 309                                 compatible = "marvell,orion-gpio";
 310                                 reg = <0x18140 0x40>;
 311                                 ngpios = <32>;
 312                                 gpio-controller;
 313                                 #gpio-cells = <2>;
 314                                 interrupt-controller;
 315                                 #interrupt-cells = <2>;
 316                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 317                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 318                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 319                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 320                         };
 321
 322                         gpio2: gpio@18180 {
 323                                 compatible = "marvell,orion-gpio";
 324                                 reg = <0x18180 0x40>;
 325                                 ngpios = <3>;
 326                                 gpio-controller;
 327                                 #gpio-cells = <2>;
 328                                 interrupt-controller;
 329                                 #interrupt-cells = <2>;
 330                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 331                         };
 332
 333                         system-controller@18200 {
 334                                 compatible = "marvell,armada-375-system-controller";
 335                                 reg = <0x18200 0x100>;
 336                         };
 337
 338                         gateclk: clock-gating-control@18220 {
 339                                 compatible = "marvell,armada-375-gating-clock";
 340                                 reg = <0x18220 0x4>;
 341                                 clocks = <&coreclk 0>;
 342                                 #clock-cells = <1>;
 343                         };
 344
 345                         mbusc: mbus-controller@20000 {
 346                                 compatible = "marvell,mbus-controller";
 347                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 348                         };
 349
 350                         mpic: interrupt-controller@20000 {
 351                                 compatible = "marvell,mpic";
 352                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 353                                 #interrupt-cells = <1>;
 354                                 #size-cells = <1>;
 355                                 interrupt-controller;
 356                                 msi-controller;
 357                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 358                         };
 359
 360                         timer@20300 {
 361                                 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
 362                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 363                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 364                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 365                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 366                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 367                                                       <&mpic 5>,
 368                                                       <&mpic 6>;
 369                                 clocks = <&coreclk 0>;
 370                         };
 371
 372                         watchdog@20300 {
 373                                 compatible = "marvell,armada-375-wdt";
 374                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
 375                                 clocks = <&coreclk 0>;
 376                         };
 377
 378                         cpurst@20800 {
 379                                 compatible = "marvell,armada-370-cpu-reset";
 380                                 reg = <0x20800 0x10>;
 381                         };
 382
 383                         coherency-fabric@21010 {
 384                                 compatible = "marvell,armada-375-coherency-fabric";
 385                                 reg = <0x21010 0x1c>;
 386                         };
 387
 388                         usb@50000 {
 389                                 compatible = "marvell,orion-ehci";
 390                                 reg = <0x50000 0x500>;
 391                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&gateclk 18>;
 393                                 status = "disabled";
 394                         };
 395
 396                         usb@54000 {
 397                                 compatible = "marvell,orion-ehci";
 398                                 reg = <0x54000 0x500>;
 399                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 400                                 clocks = <&gateclk 26>;
 401                                 status = "disabled";
 402                         };
 403
 404                         usb3@58000 {
 405                                 compatible = "marvell,armada-375-xhci";
 406                                 reg = <0x58000 0x20000>,<0x5b880 0x80>;
 407                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 408                                 clocks = <&gateclk 16>;
 409                                 status = "disabled";
 410                         };
 411
 412                         xor@60800 {
 413                                 compatible = "marvell,orion-xor";
 414                                 reg = <0x60800 0x100
 415                                        0x60A00 0x100>;
 416                                 clocks = <&gateclk 22>;
 417                                 status = "okay";
 418
 419                                 xor00 {
 420                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 421                                         dmacap,memcpy;
 422                                         dmacap,xor;
 423                                 };
 424                                 xor01 {
 425                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 426                                         dmacap,memcpy;
 427                                         dmacap,xor;
 428                                         dmacap,memset;
 429                                 };
 430                         };
 431
 432                         xor@60900 {
 433                                 compatible = "marvell,orion-xor";
 434                                 reg = <0x60900 0x100
 435                                        0x60b00 0x100>;
 436                                 clocks = <&gateclk 23>;
 437                                 status = "okay";
 438
 439                                 xor10 {
 440                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                                         dmacap,memcpy;
 442                                         dmacap,xor;
 443                                 };
 444                                 xor11 {
 445                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 446                                         dmacap,memcpy;
 447                                         dmacap,xor;
 448                                         dmacap,memset;
 449                                 };
 450                         };
 451
 452                         sata@a0000 {
 453                                 compatible = "marvell,orion-sata";
 454                                 reg = <0xa0000 0x5000>;
 455                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 456                                 clocks = <&gateclk 14>, <&gateclk 20>;
 457                                 clock-names = "0", "1";
 458                                 status = "disabled";
 459                         };
 460
 461                         nand@d0000 {
 462                                 compatible = "marvell,armada370-nand";
 463                                 reg = <0xd0000 0x54>;
 464                                 #address-cells = <1>;
 465                                 #size-cells = <1>;
 466                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 467                                 clocks = <&gateclk 11>;
 468                                 status = "disabled";
 469                         };
 470
 471                         mvsdio@d4000 {
 472                                 compatible = "marvell,orion-sdio";
 473                                 reg = <0xd4000 0x200>;
 474                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&gateclk 17>;
 476                                 bus-width = <4>;
 477                                 cap-sdio-irq;
 478                                 cap-sd-highspeed;
 479                                 cap-mmc-highspeed;
 480                                 status = "disabled";
 481                         };
 482
 483                         thermal@e8078 {
 484                                 compatible = "marvell,armada375-thermal";
 485                                 reg = <0xe8078 0x4>, <0xe807c 0x8>;
 486                                 status = "okay";
 487                         };
 488
 489                         coreclk: mvebu-sar@e8204 {
 490                                 compatible = "marvell,armada-375-core-clock";
 491                                 reg = <0xe8204 0x04>;
 492                                 #clock-cells = <1>;
 493                         };
 494
 495                         coredivclk: corediv-clock@e8250 {
 496                                 compatible = "marvell,armada-375-corediv-clock";
 497                                 reg = <0xe8250 0xc>;
 498                                 #clock-cells = <1>;
 499                                 clocks = <&mainpll>;
 500                                 clock-output-names = "nand";
 501                         };
 502                 };
 503
 504                 pcie-controller {
 505                         compatible = "marvell,armada-370-pcie";
 506                         status = "disabled";
 507                         device_type = "pci";
 508
 509                         #address-cells = <3>;
 510                         #size-cells = <2>;
 511
 512                         msi-parent = <&mpic>;
 513                         bus-range = <0x00 0xff>;
 514
 515                         ranges =
 516                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 517                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 518                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
 519                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
 520                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
 521                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
 522
 523                         pcie@1,0 {
 524                                 device_type = "pci";
 525                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 526                                 reg = <0x0800 0 0 0 0>;
 527                                 #address-cells = <3>;
 528                                 #size-cells = <2>;
 529                                 #interrupt-cells = <1>;
 530                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 531                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 532                                 interrupt-map-mask = <0 0 0 0>;
 533                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 534                                 marvell,pcie-port = <0>;
 535                                 marvell,pcie-lane = <0>;
 536                                 clocks = <&gateclk 5>;
 537                                 status = "disabled";
 538                         };
 539
 540                         pcie@2,0 {
 541                                 device_type = "pci";
 542                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 543                                 reg = <0x1000 0 0 0 0>;
 544                                 #address-cells = <3>;
 545                                 #size-cells = <2>;
 546                                 #interrupt-cells = <1>;
 547                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 548                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 549                                 interrupt-map-mask = <0 0 0 0>;
 550                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 551                                 marvell,pcie-port = <0>;
 552                                 marvell,pcie-lane = <1>;
 553                                 clocks = <&gateclk 6>;
 554                                 status = "disabled";
 555                         };
 556
 557                 };
 558         };
 559 };