2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
7 * Licensed under GPLv2 or later.
10 /include/ "skeleton.dtsi"
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
35 compatible = "arm,arm926ejs";
40 reg = <0x20000000 0x10000000>;
44 compatible = "simple-bus";
50 compatible = "simple-bus";
55 aic: interrupt-controller@fffff000 {
56 #interrupt-cells = <3>;
57 compatible = "atmel,at91rm9200-aic";
59 reg = <0xfffff000 0x200>;
62 ramc0: ramc@ffffe800 {
63 compatible = "atmel,at91sam9g45-ddramc";
64 reg = <0xffffe800 0x200>;
68 compatible = "atmel,at91rm9200-pmc";
69 reg = <0xfffffc00 0x100>;
73 compatible = "atmel,at91sam9g45-rstc";
74 reg = <0xfffffe00 0x10>;
78 compatible = "atmel,at91sam9260-pit";
79 reg = <0xfffffe30 0xf>;
84 compatible = "atmel,at91sam9x5-shdwc";
85 reg = <0xfffffe10 0x10>;
89 compatible = "atmel,hsmci";
90 reg = <0xf0008000 0x600>;
91 interrupts = <12 4 0>;
97 tcb0: timer@f8008000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf8008000 0x100>;
100 interrupts = <17 4 0>;
103 tcb1: timer@f800c000 {
104 compatible = "atmel,at91sam9x5-tcb";
105 reg = <0xf800c000 0x100>;
106 interrupts = <17 4 0>;
109 dma: dma-controller@ffffec00 {
110 compatible = "atmel,at91sam9g45-dma";
111 reg = <0xffffec00 0x200>;
112 interrupts = <20 4 0>;
117 #address-cells = <1>;
119 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
120 ranges = <0xfffff400 0xfffff400 0x800>;
124 0xffffffff 0xffe07983 0x00000000 /* pioA */
125 0x00040000 0x00047e0f 0x00000000 /* pioB */
126 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
127 0x003fffff 0x003f8000 0x00000000 /* pioD */
130 /* shared pinctrl settings */
132 pinctrl_dbgu: dbgu-0 {
134 <0 9 0x1 0x0 /* PA9 periph A */
135 0 10 0x1 0x1>; /* PA10 periph with pullup */
140 pinctrl_usart0: usart0-0 {
142 <0 1 0x1 0x1 /* PA1 periph A with pullup */
143 0 0 0x1 0x0>; /* PA0 periph A */
146 pinctrl_usart0_rts: usart0_rts-0 {
148 <0 2 0x1 0x0>; /* PA2 periph A */
151 pinctrl_usart0_cts: usart0_cts-0 {
153 <0 3 0x1 0x0>; /* PA3 periph A */
158 pinctrl_usart1: usart1-0 {
160 <0 6 0x1 0x1 /* PA6 periph A with pullup */
161 0 5 0x1 0x0>; /* PA5 periph A */
166 pinctrl_usart2: usart2-0 {
168 <0 8 0x1 0x1 /* PA8 periph A with pullup */
169 0 7 0x1 0x0>; /* PA7 periph A */
172 pinctrl_usart2_rts: usart2_rts-0 {
174 <1 0 0x2 0x0>; /* PB0 periph B */
177 pinctrl_usart2_cts: usart2_cts-0 {
179 <1 1 0x2 0x0>; /* PB1 periph B */
184 pinctrl_usart3: usart3-0 {
186 <2 23 0x2 0x1 /* PC23 periph B with pullup */
187 2 22 0x2 0x0>; /* PC22 periph B */
190 pinctrl_usart3_rts: usart3_rts-0 {
192 <2 24 0x2 0x0>; /* PC24 periph B */
195 pinctrl_usart3_cts: usart3_cts-0 {
197 <2 25 0x2 0x0>; /* PC25 periph B */
202 pinctrl_uart0: uart0-0 {
204 <2 9 0x3 0x1 /* PC9 periph C with pullup */
205 2 8 0x3 0x0>; /* PC8 periph C */
210 pinctrl_uart1: uart1-0 {
212 <2 16 0x3 0x1 /* PC17 periph C with pullup */
213 2 17 0x3 0x0>; /* PC16 periph C */
218 pinctrl_nand: nand-0 {
220 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
221 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
226 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
228 <0 17 0x1 0x0 /* PA17 periph A */
229 0 16 0x1 0x1 /* PA16 periph A with pullup */
230 0 15 0x1 0x1>; /* PA15 periph A with pullup */
233 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
235 <0 18 0x1 0x1 /* PA18 periph A with pullup */
236 0 19 0x1 0x1 /* PA19 periph A with pullup */
237 0 20 0x1 0x1>; /* PA20 periph A with pullup */
240 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
242 <0 11 0x2 0x1 /* PA11 periph B with pullup */
243 0 12 0x2 0x1 /* PA12 periph B with pullup */
244 0 13 0x2 0x1 /* PA13 periph B with pullup */
245 0 14 0x2 0x1>; /* PA14 periph B with pullup */
250 pinctrl_ssc0_tx: ssc0_tx-0 {
252 <0 24 0x2 0x0 /* PA24 periph B */
253 0 25 0x2 0x0 /* PA25 periph B */
254 0 26 0x2 0x0>; /* PA26 periph B */
257 pinctrl_ssc0_rx: ssc0_rx-0 {
259 <0 27 0x2 0x0 /* PA27 periph B */
260 0 28 0x2 0x0 /* PA28 periph B */
261 0 29 0x2 0x0>; /* PA29 periph B */
265 pioA: gpio@fffff400 {
266 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
267 reg = <0xfffff400 0x200>;
268 interrupts = <2 4 1>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
275 pioB: gpio@fffff600 {
276 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
277 reg = <0xfffff600 0x200>;
278 interrupts = <2 4 1>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
285 pioC: gpio@fffff800 {
286 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
287 reg = <0xfffff800 0x200>;
288 interrupts = <3 4 1>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
295 pioD: gpio@fffffa00 {
296 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
297 reg = <0xfffffa00 0x200>;
298 interrupts = <3 4 1>;
301 interrupt-controller;
302 #interrupt-cells = <2>;
306 dbgu: serial@fffff200 {
307 compatible = "atmel,at91sam9260-usart";
308 reg = <0xfffff200 0x200>;
309 interrupts = <1 4 7>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_dbgu>;
316 compatible = "atmel,at91sam9g45-ssc";
317 reg = <0xf0010000 0x4000>;
318 interrupts = <28 4 5>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
324 usart0: serial@f801c000 {
325 compatible = "atmel,at91sam9260-usart";
326 reg = <0xf801c000 0x4000>;
327 interrupts = <5 4 5>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usart0>;
333 usart1: serial@f8020000 {
334 compatible = "atmel,at91sam9260-usart";
335 reg = <0xf8020000 0x4000>;
336 interrupts = <6 4 5>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_usart1>;
342 usart2: serial@f8024000 {
343 compatible = "atmel,at91sam9260-usart";
344 reg = <0xf8024000 0x4000>;
345 interrupts = <7 4 5>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_usart2>;
351 usart3: serial@f8028000 {
352 compatible = "atmel,at91sam9260-usart";
353 reg = <0xf8028000 0x4000>;
354 interrupts = <8 4 5>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_usart3>;
361 compatible = "atmel,at91sam9x5-i2c";
362 reg = <0xf8010000 0x100>;
363 interrupts = <9 4 6>;
366 dma-names = "tx", "rx";
367 #address-cells = <1>;
373 compatible = "atmel,at91sam9x5-i2c";
374 reg = <0xf8014000 0x100>;
375 interrupts = <10 4 6>;
378 dma-names = "tx", "rx";
379 #address-cells = <1>;
385 nand0: nand@40000000 {
386 compatible = "atmel,at91rm9200-nand";
387 #address-cells = <1>;
389 reg = < 0x40000000 0x10000000
390 0xffffe000 0x00000600
391 0xffffe600 0x00000200
392 0x00108000 0x00018000
394 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
395 atmel,nand-addr-offset = <21>;
396 atmel,nand-cmd-offset = <22>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_nand>;
406 usb0: ohci@00500000 {
407 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
408 reg = <0x00500000 0x00100000>;
409 interrupts = <22 4 2>;
415 compatible = "i2c-gpio";
416 gpios = <&pioA 30 0 /* sda */
419 i2c-gpio,sda-open-drain;
420 i2c-gpio,scl-open-drain;
421 i2c-gpio,delay-us = <2>; /* ~100 kHz */
422 #address-cells = <1>;