arch/arm/boot/dts/bcm-cygnus.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35 #include <dt-bindings/clock/bcm-cygnus.h>
  36
  37 #include "skeleton.dtsi"
  38
  39 / {
  40         compatible = "brcm,cygnus";
  41         model = "Broadcom Cygnus SoC";
  42         interrupt-parent = <&gic>;
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         next-level-cache = <&L2>;
  52                         reg = <0x0>;
  53                 };
  54         };
  55
  56         /include/ "bcm-cygnus-clock.dtsi"
  57
  58         core {
  59                 compatible = "simple-bus";
  60                 ranges = <0x00000000 0x19000000 0x1000000>;
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63
  64                 timer@20200 {
  65                         compatible = "arm,cortex-a9-global-timer";
  66                         reg = <0x20200 0x100>;
  67                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  68                         clocks = <&periph_clk>;
  69                 };
  70
  71                 gic: interrupt-controller@21000 {
  72                         compatible = "arm,cortex-a9-gic";
  73                         #interrupt-cells = <3>;
  74                         #address-cells = <0>;
  75                         interrupt-controller;
  76                         reg = <0x21000 0x1000>,
  77                               <0x20100 0x100>;
  78                 };
  79
  80                 L2: l2-cache {
  81                         compatible = "arm,pl310-cache";
  82                         reg = <0x22000 0x1000>;
  83                         cache-unified;
  84                         cache-level = <2>;
  85                 };
  86         };
  87
  88         axi {
  89                 compatible = "simple-bus";
  90                 ranges;
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93
  94                 pcie_phy: phy@0301d0a0 {
  95                         compatible = "brcm,cygnus-pcie-phy";
  96                         reg = <0x0301d0a0 0x14>;
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99
 100                         pcie0_phy: phy@0 {
 101                                 reg = <0>;
 102                                 #phy-cells = <0>;
 103                         };
 104
 105                         pcie1_phy: phy@1 {
 106                                 reg = <1>;
 107                                 #phy-cells = <0>;
 108                         };
 109                 };
 110
 111                 pinctrl: pinctrl@0x0301d0c8 {
 112                         compatible = "brcm,cygnus-pinmux";
 113                         reg = <0x0301d0c8 0x30>,
 114                               <0x0301d24c 0x2c>;
 115                 };
 116
 117                 gpio_crmu: gpio@03024800 {
 118                         compatible = "brcm,cygnus-crmu-gpio";
 119                         reg = <0x03024800 0x50>,
 120                               <0x03024008 0x18>;
 121                         ngpios = <6>;
 122                         #gpio-cells = <2>;
 123                         gpio-controller;
 124                 };
 125
 126                 i2c0: i2c@18008000 {
 127                         compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 128                         reg = <0x18008000 0x100>;
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
 132                         clock-frequency = <100000>;
 133                         status = "disabled";
 134                 };
 135
 136                 wdt0: wdt@18009000 {
 137                         compatible = "arm,sp805" , "arm,primecell";
 138                         reg = <0x18009000 0x1000>;
 139                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 140                         clocks = <&axi81_clk>;
 141                         clock-names = "apb_pclk";
 142                 };
 143
 144                 gpio_ccm: gpio@1800a000 {
 145                         compatible = "brcm,cygnus-ccm-gpio";
 146                         reg = <0x1800a000 0x50>,
 147                               <0x0301d164 0x20>;
 148                         ngpios = <24>;
 149                         #gpio-cells = <2>;
 150                         gpio-controller;
 151                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 152                         interrupt-controller;
 153                 };
 154
 155                 i2c1: i2c@1800b000 {
 156                         compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 157                         reg = <0x1800b000 0x100>;
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
 161                         clock-frequency = <100000>;
 162                         status = "disabled";
 163                 };
 164
 165                 pcie0: pcie@18012000 {
 166                         compatible = "brcm,iproc-pcie";
 167                         reg = <0x18012000 0x1000>;
 168
 169                         #interrupt-cells = <1>;
 170                         interrupt-map-mask = <0 0 0 0>;
 171                         interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
 172
 173                         linux,pci-domain = <0>;
 174
 175                         bus-range = <0x00 0xff>;
 176
 177                         #address-cells = <3>;
 178                         #size-cells = <2>;
 179                         device_type = "pci";
 180                         ranges = <0x81000000 0 0          0x28000000 0 0x00010000
 181                                   0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
 182
 183                         phys = <&pcie0_phy>;
 184                         phy-names = "pcie-phy";
 185
 186                         status = "disabled";
 187
 188                         msi-parent = <&msi0>;
 189                         msi0: msi@18012000 {
 190                                 compatible = "brcm,iproc-msi";
 191                                 msi-controller;
 192                                 interrupt-parent = <&gic>;
 193                                 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
 194                                              <GIC_SPI 97 IRQ_TYPE_NONE>,
 195                                              <GIC_SPI 98 IRQ_TYPE_NONE>,
 196                                              <GIC_SPI 99 IRQ_TYPE_NONE>;
 197                         };
 198                 };
 199
 200                 pcie1: pcie@18013000 {
 201                         compatible = "brcm,iproc-pcie";
 202                         reg = <0x18013000 0x1000>;
 203
 204                         #interrupt-cells = <1>;
 205                         interrupt-map-mask = <0 0 0 0>;
 206                         interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
 207
 208                         linux,pci-domain = <1>;
 209
 210                         bus-range = <0x00 0xff>;
 211
 212                         #address-cells = <3>;
 213                         #size-cells = <2>;
 214                         device_type = "pci";
 215                         ranges = <0x81000000 0 0          0x48000000 0 0x00010000
 216                                   0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
 217
 218                         phys = <&pcie1_phy>;
 219                         phy-names = "pcie-phy";
 220
 221                         status = "disabled";
 222
 223                         msi-parent = <&msi1>;
 224                         msi1: msi@18013000 {
 225                                 compatible = "brcm,iproc-msi";
 226                                 msi-controller;
 227                                 interrupt-parent = <&gic>;
 228                                 interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
 229                                              <GIC_SPI 103 IRQ_TYPE_NONE>,
 230                                              <GIC_SPI 104 IRQ_TYPE_NONE>,
 231                                              <GIC_SPI 105 IRQ_TYPE_NONE>;
 232                         };
 233                 };
 234
 235                 uart0: serial@18020000 {
 236                         compatible = "snps,dw-apb-uart";
 237                         reg = <0x18020000 0x100>;
 238                         reg-shift = <2>;
 239                         reg-io-width = <4>;
 240                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&axi81_clk>;
 242                         clock-frequency = <100000000>;
 243                         status = "disabled";
 244                 };
 245
 246                 uart1: serial@18021000 {
 247                         compatible = "snps,dw-apb-uart";
 248                         reg = <0x18021000 0x100>;
 249                         reg-shift = <2>;
 250                         reg-io-width = <4>;
 251                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&axi81_clk>;
 253                         clock-frequency = <100000000>;
 254                         status = "disabled";
 255                 };
 256
 257                 uart2: serial@18022000 {
 258                         compatible = "snps,dw-apb-uart";
 259                         reg = <0x18020000 0x100>;
 260                         reg-shift = <2>;
 261                         reg-io-width = <4>;
 262                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 263                         clocks = <&axi81_clk>;
 264                         clock-frequency = <100000000>;
 265                         status = "disabled";
 266                 };
 267
 268                 uart3: serial@18023000 {
 269                         compatible = "snps,dw-apb-uart";
 270                         reg = <0x18023000 0x100>;
 271                         reg-shift = <2>;
 272                         reg-io-width = <4>;
 273                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&axi81_clk>;
 275                         clock-frequency = <100000000>;
 276                         status = "disabled";
 277                 };
 278
 279                 nand: nand@18046000 {
 280                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 281                         reg = <0x18046000 0x600>, <0xf8105408 0x600>,
 282                               <0x18046f00 0x20>;
 283                         reg-names = "nand", "iproc-idm", "iproc-ext";
 284                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 285
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288
 289                         brcm,nand-has-wp;
 290                 };
 291
 292                 gpio_asiu: gpio@180a5000 {
 293                         compatible = "brcm,cygnus-asiu-gpio";
 294                         reg = <0x180a5000 0x668>;
 295                         ngpios = <146>;
 296                         #gpio-cells = <2>;
 297                         gpio-controller;
 298
 299                         interrupt-controller;
 300                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 301                         gpio-ranges = <&pinctrl 0 42 1>,
 302                                         <&pinctrl 1 44 3>,
 303                                         <&pinctrl 4 48 1>,
 304                                         <&pinctrl 5 50 3>,
 305                                         <&pinctrl 8 126 1>,
 306                                         <&pinctrl 9 155 1>,
 307                                         <&pinctrl 10 152 1>,
 308                                         <&pinctrl 11 154 1>,
 309                                         <&pinctrl 12 153 1>,
 310                                         <&pinctrl 13 127 3>,
 311                                         <&pinctrl 16 140 1>,
 312                                         <&pinctrl 17 145 7>,
 313                                         <&pinctrl 24 130 10>,
 314                                         <&pinctrl 34 141 4>,
 315                                         <&pinctrl 38 54 1>,
 316                                         <&pinctrl 39 56 3>,
 317                                         <&pinctrl 42 60 3>,
 318                                         <&pinctrl 45 64 3>,
 319                                         <&pinctrl 48 68 2>,
 320                                         <&pinctrl 50 84 6>,
 321                                         <&pinctrl 56 94 6>,
 322                                         <&pinctrl 62 72 1>,
 323                                         <&pinctrl 63 70 1>,
 324                                         <&pinctrl 64 80 1>,
 325                                         <&pinctrl 65 74 3>,
 326                                         <&pinctrl 68 78 1>,
 327                                         <&pinctrl 69 82 1>,
 328                                         <&pinctrl 70 156 17>,
 329                                         <&pinctrl 87 104 12>,
 330                                         <&pinctrl 99 102 2>,
 331                                         <&pinctrl 101 90 4>,
 332                                         <&pinctrl 105 116 6>,
 333                                         <&pinctrl 111 100 2>,
 334                                         <&pinctrl 113 122 4>,
 335                                         <&pinctrl 123 11 1>,
 336                                         <&pinctrl 124 38 4>,
 337                                         <&pinctrl 128 43 1>,
 338                                         <&pinctrl 129 47 1>,
 339                                         <&pinctrl 130 49 1>,
 340                                         <&pinctrl 131 53 1>,
 341                                         <&pinctrl 132 55 1>,
 342                                         <&pinctrl 133 59 1>,
 343                                         <&pinctrl 134 63 1>,
 344                                         <&pinctrl 135 67 1>,
 345                                         <&pinctrl 136 71 1>,
 346                                         <&pinctrl 137 73 1>,
 347                                         <&pinctrl 138 77 1>,
 348                                         <&pinctrl 139 79 1>,
 349                                         <&pinctrl 140 81 1>,
 350                                         <&pinctrl 141 83 1>,
 351                                         <&pinctrl 142 10 1>;
 352                 };
 353
 354                 ts_adc_syscon: ts_adc_syscon@180a6000 {
 355                         compatible = "brcm,iproc-ts-adc-syscon", "syscon";
 356                         reg = <0x180a6000 0xc30>;
 357                 };
 358
 359                 touchscreen: touchscreen@180a6000 {
 360                         compatible = "brcm,iproc-touchscreen";
 361                         #address-cells = <1>;
 362                         #size-cells = <1>;
 363                         ts_syscon = <&ts_adc_syscon>;
 364                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 365                         clock-names = "tsc_clk";
 366                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 367                         status = "disabled";
 368                 };
 369
 370                 adc: adc@180a6000 {
 371                         compatible = "brcm,iproc-static-adc";
 372                         #io-channel-cells = <1>;
 373                         io-channel-ranges;
 374                         adc-syscon = <&ts_adc_syscon>;
 375                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 376                         clock-names = "tsc_clk";
 377                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 378                         status = "disabled";
 379                 };
 380         };
 381 };