arch/arm/boot/dts/bcm5301x.dtsi

   1 /*
   2  * Broadcom BCM470X / BCM5301X ARM platform code.
   3  * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
   4  * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
   5  *
   6  * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         chipcommonA {
  20                 compatible = "simple-bus";
  21                 ranges = <0x00000000 0x18000000 0x00001000>;
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 uart0: serial@0300 {
  26                         compatible = "ns16550";
  27                         reg = <0x0300 0x100>;
  28                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  29                         clock-frequency = <100000000>;
  30                         status = "disabled";
  31                 };
  32
  33                 uart1: serial@0400 {
  34                         compatible = "ns16550";
  35                         reg = <0x0400 0x100>;
  36                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  37                         clock-frequency = <100000000>;
  38                         status = "disabled";
  39                 };
  40         };
  41
  42         mpcore {
  43                 compatible = "simple-bus";
  44                 ranges = <0x00000000 0x19020000 0x00003000>;
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47
  48                 scu@0000 {
  49                         compatible = "arm,cortex-a9-scu";
  50                         reg = <0x0000 0x100>;
  51                 };
  52
  53                 timer@0200 {
  54                         compatible = "arm,cortex-a9-global-timer";
  55                         reg = <0x0200 0x100>;
  56                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  57                         clocks = <&clk_periph>;
  58                 };
  59
  60                 local-timer@0600 {
  61                         compatible = "arm,cortex-a9-twd-timer";
  62                         reg = <0x0600 0x100>;
  63                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
  64                         clocks = <&clk_periph>;
  65                 };
  66
  67                 gic: interrupt-controller@1000 {
  68                         compatible = "arm,cortex-a9-gic";
  69                         #interrupt-cells = <3>;
  70                         #address-cells = <0>;
  71                         interrupt-controller;
  72                         reg = <0x1000 0x1000>,
  73                               <0x0100 0x100>;
  74                 };
  75
  76                 L2: cache-controller@2000 {
  77                         compatible = "arm,pl310-cache";
  78                         reg = <0x2000 0x1000>;
  79                         cache-unified;
  80                         cache-level = <2>;
  81                 };
  82         };
  83
  84         clocks {
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87
  88                 /* As long as we do not have a real clock driver us this
  89                  * fixed clock */
  90                 clk_periph: periph {
  91                         compatible = "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <400000000>;
  94                 };
  95         };
  96
  97         axi@18000000 {
  98                 compatible = "brcm,bus-axi";
  99                 reg = <0x18000000 0x1000>;
 100                 ranges = <0x00000000 0x18000000 0x00100000>;
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103
 104                 chipcommon: chipcommon@0 {
 105                         reg = <0x00000000 0x1000>;
 106
 107                         gpio-controller;
 108                         #gpio-cells = <2>;
 109                 };
 110         };
 111 };