2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
67 compatible = "arm,cortex-a9-pmu";
68 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci0: sdhci@ab0000 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0000 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci1: sdhci@ab0800 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab0800 0x200>;
85 clocks = <&chip CLKID_SDIO1XIN>;
86 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
90 sdhci2: sdhci@ab1000 {
91 compatible = "mrvl,pxav3-mmc";
92 reg = <0xab1000 0x200>;
93 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&chip CLKID_SDIO1XIN>;
98 l2: l2-cache-controller@ac0000 {
99 compatible = "arm,pl310-cache";
100 reg = <0xac0000 0x1000>;
102 arm,data-latency = <2 2 2>;
103 arm,tag-latency = <2 2 2>;
106 scu: snoop-control-unit@ad0000 {
107 compatible = "arm,cortex-a9-scu";
108 reg = <0xad0000 0x58>;
112 compatible = "arm,cortex-a9-twd-timer";
113 reg = <0xad0600 0x20>;
114 clocks = <&chip CLKID_TWD>;
115 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
118 gic: interrupt-controller@ad1000 {
119 compatible = "arm,cortex-a9-gic";
120 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
121 interrupt-controller;
122 #interrupt-cells = <3>;
125 usb_phy2: phy@a2f400 {
126 compatible = "marvell,berlin2-usb-phy";
127 reg = <0xa2f400 0x128>;
129 resets = <&chip 0x104 14>;
134 compatible = "chipidea,usb2";
135 reg = <0xa30000 0x10000>;
136 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&chip CLKID_USB2>;
139 phy-names = "usb-phy";
143 usb_phy0: phy@b74000 {
144 compatible = "marvell,berlin2-usb-phy";
145 reg = <0xb74000 0x128>;
147 resets = <&chip 0x104 12>;
151 usb_phy1: phy@b78000 {
152 compatible = "marvell,berlin2-usb-phy";
153 reg = <0xb78000 0x128>;
155 resets = <&chip 0x104 13>;
159 eth0: ethernet@b90000 {
160 compatible = "marvell,pxa168-eth";
161 reg = <0xb90000 0x10000>;
162 clocks = <&chip CLKID_GETH0>;
163 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
164 /* set by bootloader */
165 local-mac-address = [00 00 00 00 00 00];
166 #address-cells = <1>;
168 phy-connection-type = "mii";
169 phy-handle = <ðphy0>;
172 ethphy0: ethernet-phy@0 {
178 compatible = "marvell,berlin-cpu-ctrl";
179 reg = <0xdd0000 0x10000>;
183 compatible = "simple-bus";
184 #address-cells = <1>;
187 ranges = <0 0xe80000 0x10000>;
188 interrupt-parent = <&aic>;
191 compatible = "snps,dw-apb-gpio";
192 reg = <0x0400 0x400>;
193 #address-cells = <1>;
197 compatible = "snps,dw-apb-gpio-port";
200 snps,nr-gpios = <32>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
209 compatible = "snps,dw-apb-gpio";
210 reg = <0x0800 0x400>;
211 #address-cells = <1>;
215 compatible = "snps,dw-apb-gpio-port";
218 snps,nr-gpios = <32>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
227 compatible = "snps,dw-apb-gpio";
228 reg = <0x0c00 0x400>;
229 #address-cells = <1>;
233 compatible = "snps,dw-apb-gpio-port";
236 snps,nr-gpios = <32>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
245 compatible = "snps,dw-apb-gpio";
246 reg = <0x1000 0x400>;
247 #address-cells = <1>;
251 compatible = "snps,dw-apb-gpio-port";
254 snps,nr-gpios = <32>;
256 interrupt-controller;
257 #interrupt-cells = <2>;
263 compatible = "snps,designware-i2c";
264 #address-cells = <1>;
266 reg = <0x1400 0x100>;
267 interrupt-parent = <&aic>;
269 clocks = <&chip CLKID_CFG>;
270 pinctrl-0 = <&twsi0_pmux>;
271 pinctrl-names = "default";
276 compatible = "snps,designware-i2c";
277 #address-cells = <1>;
279 reg = <0x1800 0x100>;
280 interrupt-parent = <&aic>;
282 clocks = <&chip CLKID_CFG>;
283 pinctrl-0 = <&twsi1_pmux>;
284 pinctrl-names = "default";
289 compatible = "snps,dw-apb-timer";
291 clocks = <&chip CLKID_CFG>;
292 clock-names = "timer";
297 compatible = "snps,dw-apb-timer";
299 clocks = <&chip CLKID_CFG>;
300 clock-names = "timer";
304 compatible = "snps,dw-apb-timer";
306 clocks = <&chip CLKID_CFG>;
307 clock-names = "timer";
312 compatible = "snps,dw-apb-timer";
314 clocks = <&chip CLKID_CFG>;
315 clock-names = "timer";
320 compatible = "snps,dw-apb-timer";
322 clocks = <&chip CLKID_CFG>;
323 clock-names = "timer";
328 compatible = "snps,dw-apb-timer";
330 clocks = <&chip CLKID_CFG>;
331 clock-names = "timer";
336 compatible = "snps,dw-apb-timer";
338 clocks = <&chip CLKID_CFG>;
339 clock-names = "timer";
344 compatible = "snps,dw-apb-timer";
346 clocks = <&chip CLKID_CFG>;
347 clock-names = "timer";
351 aic: interrupt-controller@3800 {
352 compatible = "snps,dw-apb-ictl";
354 interrupt-controller;
355 #interrupt-cells = <1>;
356 interrupt-parent = <&gic>;
357 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
361 compatible = "snps,dw-apb-gpio";
362 reg = <0x5000 0x400>;
363 #address-cells = <1>;
367 compatible = "snps,dw-apb-gpio-port";
370 snps,nr-gpios = <32>;
376 compatible = "snps,dw-apb-gpio";
377 reg = <0xc000 0x400>;
378 #address-cells = <1>;
382 compatible = "snps,dw-apb-gpio-port";
385 snps,nr-gpios = <32>;
391 chip: chip-control@ea0000 {
392 compatible = "marvell,berlin2q-chip-ctrl";
395 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
397 clock-names = "refclk";
399 twsi0_pmux: twsi0-pmux {
404 twsi1_pmux: twsi1-pmux {
411 compatible = "marvell,berlin2q-ahci", "generic-ahci";
412 reg = <0xe90000 0x1000>;
413 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&chip CLKID_SATA>;
415 #address-cells = <1>;
420 phys = <&sata_phy 0>;
426 phys = <&sata_phy 1>;
431 sata_phy: phy@e900a0 {
432 compatible = "marvell,berlin2q-sata-phy";
433 reg = <0xe900a0 0x200>;
434 clocks = <&chip CLKID_SATA>;
435 #address-cells = <1>;
450 compatible = "chipidea,usb2";
451 reg = <0xed0000 0x10000>;
452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&chip CLKID_USB0>;
455 phy-names = "usb-phy";
460 compatible = "chipidea,usb2";
461 reg = <0xee0000 0x10000>;
462 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&chip CLKID_USB1>;
465 phy-names = "usb-phy";
470 compatible = "simple-bus";
471 #address-cells = <1>;
474 ranges = <0 0xfc0000 0x10000>;
475 interrupt-parent = <&sic>;
478 compatible = "snps,designware-i2c";
479 #address-cells = <1>;
481 reg = <0x7000 0x100>;
482 interrupt-parent = <&sic>;
485 pinctrl-0 = <&twsi2_pmux>;
486 pinctrl-names = "default";
491 compatible = "snps,designware-i2c";
492 #address-cells = <1>;
494 reg = <0x8000 0x100>;
495 interrupt-parent = <&sic>;
498 pinctrl-0 = <&twsi3_pmux>;
499 pinctrl-names = "default";
504 compatible = "snps,dw-apb-uart";
505 reg = <0x9000 0x100>;
506 interrupt-parent = <&sic>;
510 pinctrl-0 = <&uart0_pmux>;
511 pinctrl-names = "default";
516 compatible = "snps,dw-apb-uart";
517 reg = <0xa000 0x100>;
518 interrupt-parent = <&sic>;
522 pinctrl-0 = <&uart1_pmux>;
523 pinctrl-names = "default";
527 sysctrl: pin-controller@d000 {
528 compatible = "marvell,berlin2q-system-ctrl";
529 reg = <0xd000 0x100>;
531 uart0_pmux: uart0-pmux {
536 uart1_pmux: uart1-pmux {
541 twsi2_pmux: twsi2-pmux {
546 twsi3_pmux: twsi3-pmux {
552 sic: interrupt-controller@e000 {
553 compatible = "snps,dw-apb-ictl";
555 interrupt-controller;
556 #interrupt-cells = <1>;
557 interrupt-parent = <&gic>;
558 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;