2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <dt-bindings/clock/berlin2q.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "skeleton.dtsi"
15 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16 compatible = "marvell,berlin2q", "marvell,berlin";
21 enable-method = "marvell,berlin-smp";
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&l2>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&l2>;
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
59 compatible = "simple-bus";
63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>;
66 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>;
69 clocks = <&chip CLKID_SDIO1XIN>;
70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
74 sdhci1: sdhci@ab0800 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab0800 0x200>;
77 clocks = <&chip CLKID_SDIO1XIN>;
78 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
82 sdhci2: sdhci@ab1000 {
83 compatible = "mrvl,pxav3-mmc";
84 reg = <0xab1000 0x200>;
85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&chip CLKID_SDIO1XIN>;
90 l2: l2-cache-controller@ac0000 {
91 compatible = "arm,pl310-cache";
92 reg = <0xac0000 0x1000>;
94 arm,data-latency = <2 2 2>;
95 arm,tag-latency = <2 2 2>;
98 scu: snoop-control-unit@ad0000 {
99 compatible = "arm,cortex-a9-scu";
100 reg = <0xad0000 0x58>;
104 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0xad0600 0x20>;
106 clocks = <&chip CLKID_TWD>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
110 gic: interrupt-controller@ad1000 {
111 compatible = "arm,cortex-a9-gic";
112 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
117 eth0: ethernet@b90000 {
118 compatible = "marvell,pxa168-eth";
119 reg = <0xb90000 0x10000>;
120 clocks = <&chip CLKID_GETH0>;
121 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
122 /* set by bootloader */
123 local-mac-address = [00 00 00 00 00 00];
124 #address-cells = <1>;
126 phy-connection-type = "mii";
127 phy-handle = <ðphy0>;
130 ethphy0: ethernet-phy@0 {
136 compatible = "marvell,berlin-cpu-ctrl";
137 reg = <0xdd0000 0x10000>;
141 compatible = "simple-bus";
142 #address-cells = <1>;
145 ranges = <0 0xe80000 0x10000>;
146 interrupt-parent = <&aic>;
149 compatible = "snps,dw-apb-gpio";
150 reg = <0x0400 0x400>;
151 #address-cells = <1>;
155 compatible = "snps,dw-apb-gpio-port";
158 snps,nr-gpios = <32>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
167 compatible = "snps,dw-apb-gpio";
168 reg = <0x0800 0x400>;
169 #address-cells = <1>;
173 compatible = "snps,dw-apb-gpio-port";
176 snps,nr-gpios = <32>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
185 compatible = "snps,dw-apb-gpio";
186 reg = <0x0c00 0x400>;
187 #address-cells = <1>;
191 compatible = "snps,dw-apb-gpio-port";
194 snps,nr-gpios = <32>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
203 compatible = "snps,dw-apb-gpio";
204 reg = <0x1000 0x400>;
205 #address-cells = <1>;
209 compatible = "snps,dw-apb-gpio-port";
212 snps,nr-gpios = <32>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
221 compatible = "snps,designware-i2c";
222 #address-cells = <1>;
224 reg = <0x1400 0x100>;
225 interrupt-parent = <&aic>;
227 clocks = <&chip CLKID_CFG>;
228 pinctrl-0 = <&twsi0_pmux>;
229 pinctrl-names = "default";
234 compatible = "snps,designware-i2c";
235 #address-cells = <1>;
237 reg = <0x1800 0x100>;
238 interrupt-parent = <&aic>;
240 clocks = <&chip CLKID_CFG>;
241 pinctrl-0 = <&twsi1_pmux>;
242 pinctrl-names = "default";
247 compatible = "snps,dw-apb-timer";
249 clocks = <&chip CLKID_CFG>;
250 clock-names = "timer";
255 compatible = "snps,dw-apb-timer";
257 clocks = <&chip CLKID_CFG>;
258 clock-names = "timer";
262 compatible = "snps,dw-apb-timer";
264 clocks = <&chip CLKID_CFG>;
265 clock-names = "timer";
270 compatible = "snps,dw-apb-timer";
272 clocks = <&chip CLKID_CFG>;
273 clock-names = "timer";
278 compatible = "snps,dw-apb-timer";
280 clocks = <&chip CLKID_CFG>;
281 clock-names = "timer";
286 compatible = "snps,dw-apb-timer";
288 clocks = <&chip CLKID_CFG>;
289 clock-names = "timer";
294 compatible = "snps,dw-apb-timer";
296 clocks = <&chip CLKID_CFG>;
297 clock-names = "timer";
302 compatible = "snps,dw-apb-timer";
304 clocks = <&chip CLKID_CFG>;
305 clock-names = "timer";
309 aic: interrupt-controller@3800 {
310 compatible = "snps,dw-apb-ictl";
312 interrupt-controller;
313 #interrupt-cells = <1>;
314 interrupt-parent = <&gic>;
315 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
319 compatible = "snps,dw-apb-gpio";
320 reg = <0x5000 0x400>;
321 #address-cells = <1>;
325 compatible = "snps,dw-apb-gpio-port";
328 snps,nr-gpios = <32>;
334 compatible = "snps,dw-apb-gpio";
335 reg = <0xc000 0x400>;
336 #address-cells = <1>;
340 compatible = "snps,dw-apb-gpio-port";
343 snps,nr-gpios = <32>;
349 chip: chip-control@ea0000 {
350 compatible = "marvell,berlin2q-chip-ctrl";
353 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
355 clock-names = "refclk";
357 twsi0_pmux: twsi0-pmux {
362 twsi1_pmux: twsi1-pmux {
369 compatible = "marvell,berlin2q-ahci", "generic-ahci";
370 reg = <0xe90000 0x1000>;
371 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&chip CLKID_SATA>;
373 #address-cells = <1>;
378 phys = <&sata_phy 0>;
384 phys = <&sata_phy 1>;
389 sata_phy: phy@e900a0 {
390 compatible = "marvell,berlin2q-sata-phy";
391 reg = <0xe900a0 0x200>;
392 clocks = <&chip CLKID_SATA>;
393 #address-cells = <1>;
408 compatible = "simple-bus";
409 #address-cells = <1>;
412 ranges = <0 0xfc0000 0x10000>;
413 interrupt-parent = <&sic>;
416 compatible = "snps,designware-i2c";
417 #address-cells = <1>;
419 reg = <0x7000 0x100>;
420 interrupt-parent = <&sic>;
423 pinctrl-0 = <&twsi2_pmux>;
424 pinctrl-names = "default";
429 compatible = "snps,designware-i2c";
430 #address-cells = <1>;
432 reg = <0x8000 0x100>;
433 interrupt-parent = <&sic>;
436 pinctrl-0 = <&twsi3_pmux>;
437 pinctrl-names = "default";
442 compatible = "snps,dw-apb-uart";
443 reg = <0x9000 0x100>;
444 interrupt-parent = <&sic>;
448 pinctrl-0 = <&uart0_pmux>;
449 pinctrl-names = "default";
454 compatible = "snps,dw-apb-uart";
455 reg = <0xa000 0x100>;
456 interrupt-parent = <&sic>;
460 pinctrl-0 = <&uart1_pmux>;
461 pinctrl-names = "default";
465 sysctrl: pin-controller@d000 {
466 compatible = "marvell,berlin2q-system-ctrl";
467 reg = <0xd000 0x100>;
469 uart0_pmux: uart0-pmux {
474 uart1_pmux: uart1-pmux {
479 twsi2_pmux: twsi2-pmux {
484 twsi3_pmux: twsi3-pmux {
490 sic: interrupt-controller@e000 {
491 compatible = "snps,dw-apb-ictl";
493 interrupt-controller;
494 #interrupt-cells = <1>;
495 interrupt-parent = <&gic>;
496 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;