arch/arm/boot/dts/berlin2q.dtsi

   1 /*
   2  * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
   3  *
   4  * This file is licensed under the terms of the GNU General Public
   5  * License version 2. This program is licensed "as is" without any
   6  * warranty of any kind, whether express or implied.
   7  */
   8
   9 #include <dt-bindings/clock/berlin2q.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         model = "Marvell Armada 1500 pro (BG2-Q) SoC";
  16         compatible = "marvell,berlin2q", "marvell,berlin";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 enable-method = "marvell,berlin-smp";
  22
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a9";
  25                         device_type = "cpu";
  26                         next-level-cache = <&l2>;
  27                         reg = <0>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "arm,cortex-a9";
  32                         device_type = "cpu";
  33                         next-level-cache = <&l2>;
  34                         reg = <1>;
  35                 };
  36
  37                 cpu@2 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         next-level-cache = <&l2>;
  41                         reg = <2>;
  42                 };
  43
  44                 cpu@3 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         next-level-cache = <&l2>;
  48                         reg = <3>;
  49                 };
  50         };
  51
  52         refclk: oscillator {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 clock-frequency = <25000000>;
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62
  63                 ranges = <0 0xf7000000 0x1000000>;
  64                 interrupt-parent = <&gic>;
  65
  66                 sdhci0: sdhci@ab0000 {
  67                         compatible = "mrvl,pxav3-mmc";
  68                         reg = <0xab0000 0x200>;
  69                         clocks = <&chip CLKID_SDIO1XIN>;
  70                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  71                         status = "disabled";
  72                 };
  73
  74                 sdhci1: sdhci@ab0800 {
  75                         compatible = "mrvl,pxav3-mmc";
  76                         reg = <0xab0800 0x200>;
  77                         clocks = <&chip CLKID_SDIO1XIN>;
  78                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  79                         status = "disabled";
  80                 };
  81
  82                 sdhci2: sdhci@ab1000 {
  83                         compatible = "mrvl,pxav3-mmc";
  84                         reg = <0xab1000 0x200>;
  85                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  86                         clocks = <&chip CLKID_SDIO1XIN>;
  87                         status = "disabled";
  88                 };
  89
  90                 l2: l2-cache-controller@ac0000 {
  91                         compatible = "arm,pl310-cache";
  92                         reg = <0xac0000 0x1000>;
  93                         cache-level = <2>;
  94                         arm,data-latency = <2 2 2>;
  95                         arm,tag-latency = <2 2 2>;
  96                 };
  97
  98                 scu: snoop-control-unit@ad0000 {
  99                         compatible = "arm,cortex-a9-scu";
 100                         reg = <0xad0000 0x58>;
 101                 };
 102
 103                 local-timer@ad0600 {
 104                         compatible = "arm,cortex-a9-twd-timer";
 105                         reg = <0xad0600 0x20>;
 106                         clocks = <&chip CLKID_TWD>;
 107                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
 108                 };
 109
 110                 gic: interrupt-controller@ad1000 {
 111                         compatible = "arm,cortex-a9-gic";
 112                         reg = <0xad1000 0x1000>, <0xad0100 0x100>;
 113                         interrupt-controller;
 114                         #interrupt-cells = <3>;
 115                 };
 116
 117                 eth0: ethernet@b90000 {
 118                         compatible = "marvell,pxa168-eth";
 119                         reg = <0xb90000 0x10000>;
 120                         clocks = <&chip CLKID_GETH0>;
 121                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 122                         /* set by bootloader */
 123                         local-mac-address = [00 00 00 00 00 00];
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         phy-connection-type = "mii";
 127                         phy-handle = <&ethphy0>;
 128                         status = "disabled";
 129
 130                         ethphy0: ethernet-phy@0 {
 131                                 reg = <0>;
 132                         };
 133                 };
 134
 135                 cpu-ctrl@dd0000 {
 136                         compatible = "marvell,berlin-cpu-ctrl";
 137                         reg = <0xdd0000 0x10000>;
 138                 };
 139
 140                 apb@e80000 {
 141                         compatible = "simple-bus";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144
 145                         ranges = <0 0xe80000 0x10000>;
 146                         interrupt-parent = <&aic>;
 147
 148                         gpio0: gpio@0400 {
 149                                 compatible = "snps,dw-apb-gpio";
 150                                 reg = <0x0400 0x400>;
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153
 154                                 porta: gpio-port@0 {
 155                                         compatible = "snps,dw-apb-gpio-port";
 156                                         gpio-controller;
 157                                         #gpio-cells = <2>;
 158                                         snps,nr-gpios = <32>;
 159                                         reg = <0>;
 160                                         interrupt-controller;
 161                                         #interrupt-cells = <2>;
 162                                         interrupts = <0>;
 163                                 };
 164                         };
 165
 166                         gpio1: gpio@0800 {
 167                                 compatible = "snps,dw-apb-gpio";
 168                                 reg = <0x0800 0x400>;
 169                                 #address-cells = <1>;
 170                                 #size-cells = <0>;
 171
 172                                 portb: gpio-port@1 {
 173                                         compatible = "snps,dw-apb-gpio-port";
 174                                         gpio-controller;
 175                                         #gpio-cells = <2>;
 176                                         snps,nr-gpios = <32>;
 177                                         reg = <0>;
 178                                         interrupt-controller;
 179                                         #interrupt-cells = <2>;
 180                                         interrupts = <1>;
 181                                 };
 182                         };
 183
 184                         gpio2: gpio@0c00 {
 185                                 compatible = "snps,dw-apb-gpio";
 186                                 reg = <0x0c00 0x400>;
 187                                 #address-cells = <1>;
 188                                 #size-cells = <0>;
 189
 190                                 portc: gpio-port@2 {
 191                                         compatible = "snps,dw-apb-gpio-port";
 192                                         gpio-controller;
 193                                         #gpio-cells = <2>;
 194                                         snps,nr-gpios = <32>;
 195                                         reg = <0>;
 196                                         interrupt-controller;
 197                                         #interrupt-cells = <2>;
 198                                         interrupts = <2>;
 199                                 };
 200                         };
 201
 202                         gpio3: gpio@1000 {
 203                                 compatible = "snps,dw-apb-gpio";
 204                                 reg = <0x1000 0x400>;
 205                                 #address-cells = <1>;
 206                                 #size-cells = <0>;
 207
 208                                 portd: gpio-port@3 {
 209                                         compatible = "snps,dw-apb-gpio-port";
 210                                         gpio-controller;
 211                                         #gpio-cells = <2>;
 212                                         snps,nr-gpios = <32>;
 213                                         reg = <0>;
 214                                         interrupt-controller;
 215                                         #interrupt-cells = <2>;
 216                                         interrupts = <3>;
 217                                 };
 218                         };
 219
 220                         i2c0: i2c@1400 {
 221                                 compatible = "snps,designware-i2c";
 222                                 #address-cells = <1>;
 223                                 #size-cells = <0>;
 224                                 reg = <0x1400 0x100>;
 225                                 interrupt-parent = <&aic>;
 226                                 interrupts = <4>;
 227                                 clocks = <&chip CLKID_CFG>;
 228                                 pinctrl-0 = <&twsi0_pmux>;
 229                                 pinctrl-names = "default";
 230                                 status = "disabled";
 231                         };
 232
 233                         i2c1: i2c@1800 {
 234                                 compatible = "snps,designware-i2c";
 235                                 #address-cells = <1>;
 236                                 #size-cells = <0>;
 237                                 reg = <0x1800 0x100>;
 238                                 interrupt-parent = <&aic>;
 239                                 interrupts = <5>;
 240                                 clocks = <&chip CLKID_CFG>;
 241                                 pinctrl-0 = <&twsi1_pmux>;
 242                                 pinctrl-names = "default";
 243                                 status = "disabled";
 244                         };
 245
 246                         timer0: timer@2c00 {
 247                                 compatible = "snps,dw-apb-timer";
 248                                 reg = <0x2c00 0x14>;
 249                                 clocks = <&chip CLKID_CFG>;
 250                                 clock-names = "timer";
 251                                 interrupts = <8>;
 252                         };
 253
 254                         timer1: timer@2c14 {
 255                                 compatible = "snps,dw-apb-timer";
 256                                 reg = <0x2c14 0x14>;
 257                                 clocks = <&chip CLKID_CFG>;
 258                                 clock-names = "timer";
 259                         };
 260
 261                         timer2: timer@2c28 {
 262                                 compatible = "snps,dw-apb-timer";
 263                                 reg = <0x2c28 0x14>;
 264                                 clocks = <&chip CLKID_CFG>;
 265                                 clock-names = "timer";
 266                                 status = "disabled";
 267                         };
 268
 269                         timer3: timer@2c3c {
 270                                 compatible = "snps,dw-apb-timer";
 271                                 reg = <0x2c3c 0x14>;
 272                                 clocks = <&chip CLKID_CFG>;
 273                                 clock-names = "timer";
 274                                 status = "disabled";
 275                         };
 276
 277                         timer4: timer@2c50 {
 278                                 compatible = "snps,dw-apb-timer";
 279                                 reg = <0x2c50 0x14>;
 280                                 clocks = <&chip CLKID_CFG>;
 281                                 clock-names = "timer";
 282                                 status = "disabled";
 283                         };
 284
 285                         timer5: timer@2c64 {
 286                                 compatible = "snps,dw-apb-timer";
 287                                 reg = <0x2c64 0x14>;
 288                                 clocks = <&chip CLKID_CFG>;
 289                                 clock-names = "timer";
 290                                 status = "disabled";
 291                         };
 292
 293                         timer6: timer@2c78 {
 294                                 compatible = "snps,dw-apb-timer";
 295                                 reg = <0x2c78 0x14>;
 296                                 clocks = <&chip CLKID_CFG>;
 297                                 clock-names = "timer";
 298                                 status = "disabled";
 299                         };
 300
 301                         timer7: timer@2c8c {
 302                                 compatible = "snps,dw-apb-timer";
 303                                 reg = <0x2c8c 0x14>;
 304                                 clocks = <&chip CLKID_CFG>;
 305                                 clock-names = "timer";
 306                                 status = "disabled";
 307                         };
 308
 309                         aic: interrupt-controller@3800 {
 310                                 compatible = "snps,dw-apb-ictl";
 311                                 reg = <0x3800 0x30>;
 312                                 interrupt-controller;
 313                                 #interrupt-cells = <1>;
 314                                 interrupt-parent = <&gic>;
 315                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 316                         };
 317
 318                         gpio4: gpio@5000 {
 319                                 compatible = "snps,dw-apb-gpio";
 320                                 reg = <0x5000 0x400>;
 321                                 #address-cells = <1>;
 322                                 #size-cells = <0>;
 323
 324                                 porte: gpio-port@4 {
 325                                         compatible = "snps,dw-apb-gpio-port";
 326                                         gpio-controller;
 327                                         #gpio-cells = <2>;
 328                                         snps,nr-gpios = <32>;
 329                                         reg = <0>;
 330                                 };
 331                         };
 332
 333                         gpio5: gpio@c000 {
 334                                 compatible = "snps,dw-apb-gpio";
 335                                 reg = <0xc000 0x400>;
 336                                 #address-cells = <1>;
 337                                 #size-cells = <0>;
 338
 339                                 portf: gpio-port@5 {
 340                                         compatible = "snps,dw-apb-gpio-port";
 341                                         gpio-controller;
 342                                         #gpio-cells = <2>;
 343                                         snps,nr-gpios = <32>;
 344                                         reg = <0>;
 345                                 };
 346                         };
 347                 };
 348
 349                 chip: chip-control@ea0000 {
 350                         compatible = "marvell,berlin2q-chip-ctrl";
 351                         #clock-cells = <1>;
 352                         #reset-cells = <2>;
 353                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
 354                         clocks = <&refclk>;
 355                         clock-names = "refclk";
 356
 357                         twsi0_pmux: twsi0-pmux {
 358                                 groups = "G6";
 359                                 function = "twsi0";
 360                         };
 361
 362                         twsi1_pmux: twsi1-pmux {
 363                                 groups = "G7";
 364                                 function = "twsi1";
 365                         };
 366                 };
 367
 368                 ahci: sata@e90000 {
 369                         compatible = "marvell,berlin2q-ahci", "generic-ahci";
 370                         reg = <0xe90000 0x1000>;
 371                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&chip CLKID_SATA>;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375
 376                         sata0: sata-port@0 {
 377                                 reg = <0>;
 378                                 phys = <&sata_phy 0>;
 379                                 status = "disabled";
 380                         };
 381
 382                         sata1: sata-port@1 {
 383                                 reg = <1>;
 384                                 phys = <&sata_phy 1>;
 385                                 status = "disabled";
 386                         };
 387                 };
 388
 389                 sata_phy: phy@e900a0 {
 390                         compatible = "marvell,berlin2q-sata-phy";
 391                         reg = <0xe900a0 0x200>;
 392                         clocks = <&chip CLKID_SATA>;
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         #phy-cells = <1>;
 396                         status = "disabled";
 397
 398                         sata-phy@0 {
 399                                 reg = <0>;
 400                         };
 401
 402                         sata-phy@1 {
 403                                 reg = <1>;
 404                         };
 405                 };
 406
 407                 apb@fc0000 {
 408                         compatible = "simple-bus";
 409                         #address-cells = <1>;
 410                         #size-cells = <1>;
 411
 412                         ranges = <0 0xfc0000 0x10000>;
 413                         interrupt-parent = <&sic>;
 414
 415                         i2c2: i2c@7000 {
 416                                 compatible = "snps,designware-i2c";
 417                                 #address-cells = <1>;
 418                                 #size-cells = <0>;
 419                                 reg = <0x7000 0x100>;
 420                                 interrupt-parent = <&sic>;
 421                                 interrupts = <6>;
 422                                 clocks = <&refclk>;
 423                                 pinctrl-0 = <&twsi2_pmux>;
 424                                 pinctrl-names = "default";
 425                                 status = "disabled";
 426                         };
 427
 428                         i2c3: i2c@8000 {
 429                                 compatible = "snps,designware-i2c";
 430                                 #address-cells = <1>;
 431                                 #size-cells = <0>;
 432                                 reg = <0x8000 0x100>;
 433                                 interrupt-parent = <&sic>;
 434                                 interrupts = <7>;
 435                                 clocks = <&refclk>;
 436                                 pinctrl-0 = <&twsi3_pmux>;
 437                                 pinctrl-names = "default";
 438                                 status = "disabled";
 439                         };
 440
 441                         uart0: uart@9000 {
 442                                 compatible = "snps,dw-apb-uart";
 443                                 reg = <0x9000 0x100>;
 444                                 interrupt-parent = <&sic>;
 445                                 interrupts = <8>;
 446                                 clocks = <&refclk>;
 447                                 reg-shift = <2>;
 448                                 pinctrl-0 = <&uart0_pmux>;
 449                                 pinctrl-names = "default";
 450                                 status = "disabled";
 451                         };
 452
 453                         uart1: uart@a000 {
 454                                 compatible = "snps,dw-apb-uart";
 455                                 reg = <0xa000 0x100>;
 456                                 interrupt-parent = <&sic>;
 457                                 interrupts = <9>;
 458                                 clocks = <&refclk>;
 459                                 reg-shift = <2>;
 460                                 pinctrl-0 = <&uart1_pmux>;
 461                                 pinctrl-names = "default";
 462                                 status = "disabled";
 463                         };
 464
 465                         sysctrl: pin-controller@d000 {
 466                                 compatible = "marvell,berlin2q-system-ctrl";
 467                                 reg = <0xd000 0x100>;
 468
 469                                 uart0_pmux: uart0-pmux {
 470                                         groups = "GSM12";
 471                                         function = "uart0";
 472                                 };
 473
 474                                 uart1_pmux: uart1-pmux {
 475                                         groups = "GSM14";
 476                                         function = "uart1";
 477                                 };
 478
 479                                 twsi2_pmux: twsi2-pmux {
 480                                         groups = "GSM13";
 481                                         function = "twsi2";
 482                                 };
 483
 484                                 twsi3_pmux: twsi3-pmux {
 485                                         groups = "GSM14";
 486                                         function = "twsi3";
 487                                 };
 488                         };
 489
 490                         sic: interrupt-controller@e000 {
 491                                 compatible = "snps,dw-apb-ictl";
 492                                 reg = <0xe000 0x30>;
 493                                 interrupt-controller;
 494                                 #interrupt-cells = <1>;
 495                                 interrupt-parent = <&gic>;
 496                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 497                         };
 498                 };
 499         };
 500 };