arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         compatible = "ti,dra7xx";
  20         interrupt-parent = <&gic>;
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         timer {
  37                 compatible = "arm,armv7-timer";
  38                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  39                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  40                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  41                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  42         };
  43
  44         gic: interrupt-controller@48211000 {
  45                 compatible = "arm,cortex-a15-gic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48                 reg = <0x48211000 0x1000>,
  49                       <0x48212000 0x1000>,
  50                       <0x48214000 0x2000>,
  51                       <0x48216000 0x2000>;
  52                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  53         };
  54
  55         /*
  56          * The soc node represents the soc top level view. It is used for IPs
  57          * that are not memory mapped in the MPU view or for the MPU itself.
  58          */
  59         soc {
  60                 compatible = "ti,omap-infra";
  61                 mpu {
  62                         compatible = "ti,omap5-mpu";
  63                         ti,hwmods = "mpu";
  64                 };
  65         };
  66
  67         /*
  68          * XXX: Use a flat representation of the SOC interconnect.
  69          * The real OMAP interconnect network is quite complex.
  70          * Since it will not bring real advantage to represent that in DT for
  71          * the moment, just use a fake OCP bus entry to represent the whole bus
  72          * hierarchy.
  73          */
  74         ocp {
  75                 compatible = "ti,dra7-l3-noc", "simple-bus";
  76                 #address-cells = <1>;
  77                 #size-cells = <1>;
  78                 ranges;
  79                 ti,hwmods = "l3_main_1", "l3_main_2";
  80                 reg = <0x44000000 0x1000000>,
  81                       <0x45000000 0x1000>;
  82                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  84
  85                 prm: prm@4ae06000 {
  86                         compatible = "ti,dra7-prm";
  87                         reg = <0x4ae06000 0x3000>;
  88
  89                         prm_clocks: clocks {
  90                                 #address-cells = <1>;
  91                                 #size-cells = <0>;
  92                         };
  93
  94                         prm_clockdomains: clockdomains {
  95                         };
  96                 };
  97
  98                 cm_core_aon: cm_core_aon@4a005000 {
  99                         compatible = "ti,dra7-cm-core-aon";
 100                         reg = <0x4a005000 0x2000>;
 101
 102                         cm_core_aon_clocks: clocks {
 103                                 #address-cells = <1>;
 104                                 #size-cells = <0>;
 105                         };
 106
 107                         cm_core_aon_clockdomains: clockdomains {
 108                         };
 109                 };
 110
 111                 cm_core: cm_core@4a008000 {
 112                         compatible = "ti,dra7-cm-core";
 113                         reg = <0x4a008000 0x3000>;
 114
 115                         cm_core_clocks: clocks {
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118                         };
 119
 120                         cm_core_clockdomains: clockdomains {
 121                         };
 122                 };
 123
 124                 counter32k: counter@4ae04000 {
 125                         compatible = "ti,omap-counter32k";
 126                         reg = <0x4ae04000 0x40>;
 127                         ti,hwmods = "counter_32k";
 128                 };
 129
 130                 dra7_ctrl_general: tisyscon@4a002e00 {
 131                         compatible = "syscon";
 132                         reg = <0x4a002e00 0x7c>;
 133                 };
 134
 135                 pbias_regulator: pbias_regulator {
 136                         compatible = "ti,pbias-omap";
 137                         reg = <0 0x4>;
 138                         syscon = <&dra7_ctrl_general>;
 139                         pbias_mmc_reg: pbias_mmc_omap5 {
 140                                 regulator-name = "pbias_mmc_omap5";
 141                                 regulator-min-microvolt = <1800000>;
 142                                 regulator-max-microvolt = <3000000>;
 143                         };
 144                 };
 145
 146                 dra7_pmx_core: pinmux@4a003400 {
 147                         compatible = "pinctrl-single";
 148                         reg = <0x4a003400 0x0464>;
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         pinctrl-single,register-width = <32>;
 152                         pinctrl-single,function-mask = <0x3fffffff>;
 153                 };
 154
 155                 sdma: dma-controller@4a056000 {
 156                         compatible = "ti,omap4430-sdma";
 157                         reg = <0x4a056000 0x1000>;
 158                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 159                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 161                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 162                         #dma-cells = <1>;
 163                         #dma-channels = <32>;
 164                         #dma-requests = <127>;
 165                 };
 166
 167                 gpio1: gpio@4ae10000 {
 168                         compatible = "ti,omap4-gpio";
 169                         reg = <0x4ae10000 0x200>;
 170                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 171                         ti,hwmods = "gpio1";
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                         interrupt-controller;
 175                         #interrupt-cells = <1>;
 176                 };
 177
 178                 gpio2: gpio@48055000 {
 179                         compatible = "ti,omap4-gpio";
 180                         reg = <0x48055000 0x200>;
 181                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 182                         ti,hwmods = "gpio2";
 183                         gpio-controller;
 184                         #gpio-cells = <2>;
 185                         interrupt-controller;
 186                         #interrupt-cells = <1>;
 187                 };
 188
 189                 gpio3: gpio@48057000 {
 190                         compatible = "ti,omap4-gpio";
 191                         reg = <0x48057000 0x200>;
 192                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 193                         ti,hwmods = "gpio3";
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                         interrupt-controller;
 197                         #interrupt-cells = <1>;
 198                 };
 199
 200                 gpio4: gpio@48059000 {
 201                         compatible = "ti,omap4-gpio";
 202                         reg = <0x48059000 0x200>;
 203                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 204                         ti,hwmods = "gpio4";
 205                         gpio-controller;
 206                         #gpio-cells = <2>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <1>;
 209                 };
 210
 211                 gpio5: gpio@4805b000 {
 212                         compatible = "ti,omap4-gpio";
 213                         reg = <0x4805b000 0x200>;
 214                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 215                         ti,hwmods = "gpio5";
 216                         gpio-controller;
 217                         #gpio-cells = <2>;
 218                         interrupt-controller;
 219                         #interrupt-cells = <1>;
 220                 };
 221
 222                 gpio6: gpio@4805d000 {
 223                         compatible = "ti,omap4-gpio";
 224                         reg = <0x4805d000 0x200>;
 225                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 226                         ti,hwmods = "gpio6";
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229                         interrupt-controller;
 230                         #interrupt-cells = <1>;
 231                 };
 232
 233                 gpio7: gpio@48051000 {
 234                         compatible = "ti,omap4-gpio";
 235                         reg = <0x48051000 0x200>;
 236                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 237                         ti,hwmods = "gpio7";
 238                         gpio-controller;
 239                         #gpio-cells = <2>;
 240                         interrupt-controller;
 241                         #interrupt-cells = <1>;
 242                 };
 243
 244                 gpio8: gpio@48053000 {
 245                         compatible = "ti,omap4-gpio";
 246                         reg = <0x48053000 0x200>;
 247                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 248                         ti,hwmods = "gpio8";
 249                         gpio-controller;
 250                         #gpio-cells = <2>;
 251                         interrupt-controller;
 252                         #interrupt-cells = <1>;
 253                 };
 254
 255                 uart1: serial@4806a000 {
 256                         compatible = "ti,omap4-uart";
 257                         reg = <0x4806a000 0x100>;
 258                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 259                         ti,hwmods = "uart1";
 260                         clock-frequency = <48000000>;
 261                         status = "disabled";
 262                 };
 263
 264                 uart2: serial@4806c000 {
 265                         compatible = "ti,omap4-uart";
 266                         reg = <0x4806c000 0x100>;
 267                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 268                         ti,hwmods = "uart2";
 269                         clock-frequency = <48000000>;
 270                         status = "disabled";
 271                 };
 272
 273                 uart3: serial@48020000 {
 274                         compatible = "ti,omap4-uart";
 275                         reg = <0x48020000 0x100>;
 276                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 277                         ti,hwmods = "uart3";
 278                         clock-frequency = <48000000>;
 279                         status = "disabled";
 280                 };
 281
 282                 uart4: serial@4806e000 {
 283                         compatible = "ti,omap4-uart";
 284                         reg = <0x4806e000 0x100>;
 285                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 286                         ti,hwmods = "uart4";
 287                         clock-frequency = <48000000>;
 288                         status = "disabled";
 289                 };
 290
 291                 uart5: serial@48066000 {
 292                         compatible = "ti,omap4-uart";
 293                         reg = <0x48066000 0x100>;
 294                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 295                         ti,hwmods = "uart5";
 296                         clock-frequency = <48000000>;
 297                         status = "disabled";
 298                 };
 299
 300                 uart6: serial@48068000 {
 301                         compatible = "ti,omap4-uart";
 302                         reg = <0x48068000 0x100>;
 303                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 304                         ti,hwmods = "uart6";
 305                         clock-frequency = <48000000>;
 306                         status = "disabled";
 307                 };
 308
 309                 uart7: serial@48420000 {
 310                         compatible = "ti,omap4-uart";
 311                         reg = <0x48420000 0x100>;
 312                         ti,hwmods = "uart7";
 313                         clock-frequency = <48000000>;
 314                         status = "disabled";
 315                 };
 316
 317                 uart8: serial@48422000 {
 318                         compatible = "ti,omap4-uart";
 319                         reg = <0x48422000 0x100>;
 320                         ti,hwmods = "uart8";
 321                         clock-frequency = <48000000>;
 322                         status = "disabled";
 323                 };
 324
 325                 uart9: serial@48424000 {
 326                         compatible = "ti,omap4-uart";
 327                         reg = <0x48424000 0x100>;
 328                         ti,hwmods = "uart9";
 329                         clock-frequency = <48000000>;
 330                         status = "disabled";
 331                 };
 332
 333                 uart10: serial@4ae2b000 {
 334                         compatible = "ti,omap4-uart";
 335                         reg = <0x4ae2b000 0x100>;
 336                         ti,hwmods = "uart10";
 337                         clock-frequency = <48000000>;
 338                         status = "disabled";
 339                 };
 340
 341                 mailbox1: mailbox@4a0f4000 {
 342                         compatible = "ti,omap4-mailbox";
 343                         reg = <0x4a0f4000 0x200>;
 344                         ti,hwmods = "mailbox1";
 345                         ti,mbox-num-users = <3>;
 346                         ti,mbox-num-fifos = <8>;
 347                         status = "disabled";
 348                 };
 349
 350                 mailbox2: mailbox@4883a000 {
 351                         compatible = "ti,omap4-mailbox";
 352                         reg = <0x4883a000 0x200>;
 353                         ti,hwmods = "mailbox2";
 354                         ti,mbox-num-users = <4>;
 355                         ti,mbox-num-fifos = <12>;
 356                         status = "disabled";
 357                 };
 358
 359                 mailbox3: mailbox@4883c000 {
 360                         compatible = "ti,omap4-mailbox";
 361                         reg = <0x4883c000 0x200>;
 362                         ti,hwmods = "mailbox3";
 363                         ti,mbox-num-users = <4>;
 364                         ti,mbox-num-fifos = <12>;
 365                         status = "disabled";
 366                 };
 367
 368                 mailbox4: mailbox@4883e000 {
 369                         compatible = "ti,omap4-mailbox";
 370                         reg = <0x4883e000 0x200>;
 371                         ti,hwmods = "mailbox4";
 372                         ti,mbox-num-users = <4>;
 373                         ti,mbox-num-fifos = <12>;
 374                         status = "disabled";
 375                 };
 376
 377                 mailbox5: mailbox@48840000 {
 378                         compatible = "ti,omap4-mailbox";
 379                         reg = <0x48840000 0x200>;
 380                         ti,hwmods = "mailbox5";
 381                         ti,mbox-num-users = <4>;
 382                         ti,mbox-num-fifos = <12>;
 383                         status = "disabled";
 384                 };
 385
 386                 mailbox6: mailbox@48842000 {
 387                         compatible = "ti,omap4-mailbox";
 388                         reg = <0x48842000 0x200>;
 389                         ti,hwmods = "mailbox6";
 390                         ti,mbox-num-users = <4>;
 391                         ti,mbox-num-fifos = <12>;
 392                         status = "disabled";
 393                 };
 394
 395                 mailbox7: mailbox@48844000 {
 396                         compatible = "ti,omap4-mailbox";
 397                         reg = <0x48844000 0x200>;
 398                         ti,hwmods = "mailbox7";
 399                         ti,mbox-num-users = <4>;
 400                         ti,mbox-num-fifos = <12>;
 401                         status = "disabled";
 402                 };
 403
 404                 mailbox8: mailbox@48846000 {
 405                         compatible = "ti,omap4-mailbox";
 406                         reg = <0x48846000 0x200>;
 407                         ti,hwmods = "mailbox8";
 408                         ti,mbox-num-users = <4>;
 409                         ti,mbox-num-fifos = <12>;
 410                         status = "disabled";
 411                 };
 412
 413                 mailbox9: mailbox@4885e000 {
 414                         compatible = "ti,omap4-mailbox";
 415                         reg = <0x4885e000 0x200>;
 416                         ti,hwmods = "mailbox9";
 417                         ti,mbox-num-users = <4>;
 418                         ti,mbox-num-fifos = <12>;
 419                         status = "disabled";
 420                 };
 421
 422                 mailbox10: mailbox@48860000 {
 423                         compatible = "ti,omap4-mailbox";
 424                         reg = <0x48860000 0x200>;
 425                         ti,hwmods = "mailbox10";
 426                         ti,mbox-num-users = <4>;
 427                         ti,mbox-num-fifos = <12>;
 428                         status = "disabled";
 429                 };
 430
 431                 mailbox11: mailbox@48862000 {
 432                         compatible = "ti,omap4-mailbox";
 433                         reg = <0x48862000 0x200>;
 434                         ti,hwmods = "mailbox11";
 435                         ti,mbox-num-users = <4>;
 436                         ti,mbox-num-fifos = <12>;
 437                         status = "disabled";
 438                 };
 439
 440                 mailbox12: mailbox@48864000 {
 441                         compatible = "ti,omap4-mailbox";
 442                         reg = <0x48864000 0x200>;
 443                         ti,hwmods = "mailbox12";
 444                         ti,mbox-num-users = <4>;
 445                         ti,mbox-num-fifos = <12>;
 446                         status = "disabled";
 447                 };
 448
 449                 mailbox13: mailbox@48802000 {
 450                         compatible = "ti,omap4-mailbox";
 451                         reg = <0x48802000 0x200>;
 452                         ti,hwmods = "mailbox13";
 453                         ti,mbox-num-users = <4>;
 454                         ti,mbox-num-fifos = <12>;
 455                         status = "disabled";
 456                 };
 457
 458                 timer1: timer@4ae18000 {
 459                         compatible = "ti,omap5430-timer";
 460                         reg = <0x4ae18000 0x80>;
 461                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 462                         ti,hwmods = "timer1";
 463                         ti,timer-alwon;
 464                 };
 465
 466                 timer2: timer@48032000 {
 467                         compatible = "ti,omap5430-timer";
 468                         reg = <0x48032000 0x80>;
 469                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "timer2";
 471                 };
 472
 473                 timer3: timer@48034000 {
 474                         compatible = "ti,omap5430-timer";
 475                         reg = <0x48034000 0x80>;
 476                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 477                         ti,hwmods = "timer3";
 478                 };
 479
 480                 timer4: timer@48036000 {
 481                         compatible = "ti,omap5430-timer";
 482                         reg = <0x48036000 0x80>;
 483                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 484                         ti,hwmods = "timer4";
 485                 };
 486
 487                 timer5: timer@48820000 {
 488                         compatible = "ti,omap5430-timer";
 489                         reg = <0x48820000 0x80>;
 490                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 491                         ti,hwmods = "timer5";
 492                         ti,timer-dsp;
 493                 };
 494
 495                 timer6: timer@48822000 {
 496                         compatible = "ti,omap5430-timer";
 497                         reg = <0x48822000 0x80>;
 498                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 499                         ti,hwmods = "timer6";
 500                         ti,timer-dsp;
 501                         ti,timer-pwm;
 502                 };
 503
 504                 timer7: timer@48824000 {
 505                         compatible = "ti,omap5430-timer";
 506                         reg = <0x48824000 0x80>;
 507                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 508                         ti,hwmods = "timer7";
 509                         ti,timer-dsp;
 510                 };
 511
 512                 timer8: timer@48826000 {
 513                         compatible = "ti,omap5430-timer";
 514                         reg = <0x48826000 0x80>;
 515                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 516                         ti,hwmods = "timer8";
 517                         ti,timer-dsp;
 518                         ti,timer-pwm;
 519                 };
 520
 521                 timer9: timer@4803e000 {
 522                         compatible = "ti,omap5430-timer";
 523                         reg = <0x4803e000 0x80>;
 524                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 525                         ti,hwmods = "timer9";
 526                 };
 527
 528                 timer10: timer@48086000 {
 529                         compatible = "ti,omap5430-timer";
 530                         reg = <0x48086000 0x80>;
 531                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 532                         ti,hwmods = "timer10";
 533                 };
 534
 535                 timer11: timer@48088000 {
 536                         compatible = "ti,omap5430-timer";
 537                         reg = <0x48088000 0x80>;
 538                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "timer11";
 540                         ti,timer-pwm;
 541                 };
 542
 543                 timer13: timer@48828000 {
 544                         compatible = "ti,omap5430-timer";
 545                         reg = <0x48828000 0x80>;
 546                         ti,hwmods = "timer13";
 547                         status = "disabled";
 548                 };
 549
 550                 timer14: timer@4882a000 {
 551                         compatible = "ti,omap5430-timer";
 552                         reg = <0x4882a000 0x80>;
 553                         ti,hwmods = "timer14";
 554                         status = "disabled";
 555                 };
 556
 557                 timer15: timer@4882c000 {
 558                         compatible = "ti,omap5430-timer";
 559                         reg = <0x4882c000 0x80>;
 560                         ti,hwmods = "timer15";
 561                         status = "disabled";
 562                 };
 563
 564                 timer16: timer@4882e000 {
 565                         compatible = "ti,omap5430-timer";
 566                         reg = <0x4882e000 0x80>;
 567                         ti,hwmods = "timer16";
 568                         status = "disabled";
 569                 };
 570
 571                 wdt2: wdt@4ae14000 {
 572                         compatible = "ti,omap4-wdt";
 573                         reg = <0x4ae14000 0x80>;
 574                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "wd_timer2";
 576                 };
 577
 578                 hwspinlock: spinlock@4a0f6000 {
 579                         compatible = "ti,omap4-hwspinlock";
 580                         reg = <0x4a0f6000 0x1000>;
 581                         ti,hwmods = "spinlock";
 582                         #hwlock-cells = <1>;
 583                 };
 584
 585                 dmm@4e000000 {
 586                         compatible = "ti,omap5-dmm";
 587                         reg = <0x4e000000 0x800>;
 588                         interrupts = <0 113 0x4>;
 589                         ti,hwmods = "dmm";
 590                 };
 591
 592                 i2c1: i2c@48070000 {
 593                         compatible = "ti,omap4-i2c";
 594                         reg = <0x48070000 0x100>;
 595                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         ti,hwmods = "i2c1";
 599                         status = "disabled";
 600                 };
 601
 602                 i2c2: i2c@48072000 {
 603                         compatible = "ti,omap4-i2c";
 604                         reg = <0x48072000 0x100>;
 605                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         ti,hwmods = "i2c2";
 609                         status = "disabled";
 610                 };
 611
 612                 i2c3: i2c@48060000 {
 613                         compatible = "ti,omap4-i2c";
 614                         reg = <0x48060000 0x100>;
 615                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         ti,hwmods = "i2c3";
 619                         status = "disabled";
 620                 };
 621
 622                 i2c4: i2c@4807a000 {
 623                         compatible = "ti,omap4-i2c";
 624                         reg = <0x4807a000 0x100>;
 625                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                         ti,hwmods = "i2c4";
 629                         status = "disabled";
 630                 };
 631
 632                 i2c5: i2c@4807c000 {
 633                         compatible = "ti,omap4-i2c";
 634                         reg = <0x4807c000 0x100>;
 635                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                         ti,hwmods = "i2c5";
 639                         status = "disabled";
 640                 };
 641
 642                 mmc1: mmc@4809c000 {
 643                         compatible = "ti,omap4-hsmmc";
 644                         reg = <0x4809c000 0x400>;
 645                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 646                         ti,hwmods = "mmc1";
 647                         ti,dual-volt;
 648                         ti,needs-special-reset;
 649                         dmas = <&sdma 61>, <&sdma 62>;
 650                         dma-names = "tx", "rx";
 651                         status = "disabled";
 652                         pbias-supply = <&pbias_mmc_reg>;
 653                 };
 654
 655                 mmc2: mmc@480b4000 {
 656                         compatible = "ti,omap4-hsmmc";
 657                         reg = <0x480b4000 0x400>;
 658                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 659                         ti,hwmods = "mmc2";
 660                         ti,needs-special-reset;
 661                         dmas = <&sdma 47>, <&sdma 48>;
 662                         dma-names = "tx", "rx";
 663                         status = "disabled";
 664                 };
 665
 666                 mmc3: mmc@480ad000 {
 667                         compatible = "ti,omap4-hsmmc";
 668                         reg = <0x480ad000 0x400>;
 669                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 670                         ti,hwmods = "mmc3";
 671                         ti,needs-special-reset;
 672                         dmas = <&sdma 77>, <&sdma 78>;
 673                         dma-names = "tx", "rx";
 674                         status = "disabled";
 675                 };
 676
 677                 mmc4: mmc@480d1000 {
 678                         compatible = "ti,omap4-hsmmc";
 679                         reg = <0x480d1000 0x400>;
 680                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 681                         ti,hwmods = "mmc4";
 682                         ti,needs-special-reset;
 683                         dmas = <&sdma 57>, <&sdma 58>;
 684                         dma-names = "tx", "rx";
 685                         status = "disabled";
 686                 };
 687
 688                 abb_mpu: regulator-abb-mpu {
 689                         compatible = "ti,abb-v3";
 690                         regulator-name = "abb_mpu";
 691                         #address-cells = <0>;
 692                         #size-cells = <0>;
 693                         clocks = <&sys_clkin1>;
 694                         ti,settling-time = <50>;
 695                         ti,clock-cycles = <16>;
 696
 697                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 698                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 699                               <0x4ae0c158 0x4>;
 700                         reg-names = "setup-address", "control-address",
 701                                     "int-address", "efuse-address",
 702                                     "ldo-address";
 703                         ti,tranxdone-status-mask = <0x80>;
 704                         /* LDOVBBMPU_FBB_MUX_CTRL */
 705                         ti,ldovbb-override-mask = <0x400>;
 706                         /* LDOVBBMPU_FBB_VSET_OUT */
 707                         ti,ldovbb-vset-mask = <0x1F>;
 708
 709                         /*
 710                          * NOTE: only FBB mode used but actual vset will
 711                          * determine final biasing
 712                          */
 713                         ti,abb_info = <
 714                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 715                         1060000         0       0x0     0 0x02000000 0x01F00000
 716                         1160000         0       0x4     0 0x02000000 0x01F00000
 717                         1210000         0       0x8     0 0x02000000 0x01F00000
 718                         >;
 719                 };
 720
 721                 abb_ivahd: regulator-abb-ivahd {
 722                         compatible = "ti,abb-v3";
 723                         regulator-name = "abb_ivahd";
 724                         #address-cells = <0>;
 725                         #size-cells = <0>;
 726                         clocks = <&sys_clkin1>;
 727                         ti,settling-time = <50>;
 728                         ti,clock-cycles = <16>;
 729
 730                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 731                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 732                               <0x4a002470 0x4>;
 733                         reg-names = "setup-address", "control-address",
 734                                     "int-address", "efuse-address",
 735                                     "ldo-address";
 736                         ti,tranxdone-status-mask = <0x40000000>;
 737                         /* LDOVBBIVA_FBB_MUX_CTRL */
 738                         ti,ldovbb-override-mask = <0x400>;
 739                         /* LDOVBBIVA_FBB_VSET_OUT */
 740                         ti,ldovbb-vset-mask = <0x1F>;
 741
 742                         /*
 743                          * NOTE: only FBB mode used but actual vset will
 744                          * determine final biasing
 745                          */
 746                         ti,abb_info = <
 747                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 748                         1055000         0       0x0     0 0x02000000 0x01F00000
 749                         1150000         0       0x4     0 0x02000000 0x01F00000
 750                         1250000         0       0x8     0 0x02000000 0x01F00000
 751                         >;
 752                 };
 753
 754                 abb_dspeve: regulator-abb-dspeve {
 755                         compatible = "ti,abb-v3";
 756                         regulator-name = "abb_dspeve";
 757                         #address-cells = <0>;
 758                         #size-cells = <0>;
 759                         clocks = <&sys_clkin1>;
 760                         ti,settling-time = <50>;
 761                         ti,clock-cycles = <16>;
 762
 763                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 764                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 765                               <0x4a00246c 0x4>;
 766                         reg-names = "setup-address", "control-address",
 767                                     "int-address", "efuse-address",
 768                                     "ldo-address";
 769                         ti,tranxdone-status-mask = <0x20000000>;
 770                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 771                         ti,ldovbb-override-mask = <0x400>;
 772                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 773                         ti,ldovbb-vset-mask = <0x1F>;
 774
 775                         /*
 776                          * NOTE: only FBB mode used but actual vset will
 777                          * determine final biasing
 778                          */
 779                         ti,abb_info = <
 780                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 781                         1055000         0       0x0     0 0x02000000 0x01F00000
 782                         1150000         0       0x4     0 0x02000000 0x01F00000
 783                         1250000         0       0x8     0 0x02000000 0x01F00000
 784                         >;
 785                 };
 786
 787                 abb_gpu: regulator-abb-gpu {
 788                         compatible = "ti,abb-v3";
 789                         regulator-name = "abb_gpu";
 790                         #address-cells = <0>;
 791                         #size-cells = <0>;
 792                         clocks = <&sys_clkin1>;
 793                         ti,settling-time = <50>;
 794                         ti,clock-cycles = <16>;
 795
 796                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 797                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 798                               <0x4ae0c154 0x4>;
 799                         reg-names = "setup-address", "control-address",
 800                                     "int-address", "efuse-address",
 801                                     "ldo-address";
 802                         ti,tranxdone-status-mask = <0x10000000>;
 803                         /* LDOVBBGPU_FBB_MUX_CTRL */
 804                         ti,ldovbb-override-mask = <0x400>;
 805                         /* LDOVBBGPU_FBB_VSET_OUT */
 806                         ti,ldovbb-vset-mask = <0x1F>;
 807
 808                         /*
 809                          * NOTE: only FBB mode used but actual vset will
 810                          * determine final biasing
 811                          */
 812                         ti,abb_info = <
 813                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 814                         1090000         0       0x0     0 0x02000000 0x01F00000
 815                         1210000         0       0x4     0 0x02000000 0x01F00000
 816                         1280000         0       0x8     0 0x02000000 0x01F00000
 817                         >;
 818                 };
 819
 820                 mcspi1: spi@48098000 {
 821                         compatible = "ti,omap4-mcspi";
 822                         reg = <0x48098000 0x200>;
 823                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 824                         #address-cells = <1>;
 825                         #size-cells = <0>;
 826                         ti,hwmods = "mcspi1";
 827                         ti,spi-num-cs = <4>;
 828                         dmas = <&sdma 35>,
 829                                <&sdma 36>,
 830                                <&sdma 37>,
 831                                <&sdma 38>,
 832                                <&sdma 39>,
 833                                <&sdma 40>,
 834                                <&sdma 41>,
 835                                <&sdma 42>;
 836                         dma-names = "tx0", "rx0", "tx1", "rx1",
 837                                     "tx2", "rx2", "tx3", "rx3";
 838                         status = "disabled";
 839                 };
 840
 841                 mcspi2: spi@4809a000 {
 842                         compatible = "ti,omap4-mcspi";
 843                         reg = <0x4809a000 0x200>;
 844                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 845                         #address-cells = <1>;
 846                         #size-cells = <0>;
 847                         ti,hwmods = "mcspi2";
 848                         ti,spi-num-cs = <2>;
 849                         dmas = <&sdma 43>,
 850                                <&sdma 44>,
 851                                <&sdma 45>,
 852                                <&sdma 46>;
 853                         dma-names = "tx0", "rx0", "tx1", "rx1";
 854                         status = "disabled";
 855                 };
 856
 857                 mcspi3: spi@480b8000 {
 858                         compatible = "ti,omap4-mcspi";
 859                         reg = <0x480b8000 0x200>;
 860                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 861                         #address-cells = <1>;
 862                         #size-cells = <0>;
 863                         ti,hwmods = "mcspi3";
 864                         ti,spi-num-cs = <2>;
 865                         dmas = <&sdma 15>, <&sdma 16>;
 866                         dma-names = "tx0", "rx0";
 867                         status = "disabled";
 868                 };
 869
 870                 mcspi4: spi@480ba000 {
 871                         compatible = "ti,omap4-mcspi";
 872                         reg = <0x480ba000 0x200>;
 873                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 874                         #address-cells = <1>;
 875                         #size-cells = <0>;
 876                         ti,hwmods = "mcspi4";
 877                         ti,spi-num-cs = <1>;
 878                         dmas = <&sdma 70>, <&sdma 71>;
 879                         dma-names = "tx0", "rx0";
 880                         status = "disabled";
 881                 };
 882
 883                 qspi: qspi@4b300000 {
 884                         compatible = "ti,dra7xxx-qspi";
 885                         reg = <0x4b300000 0x100>;
 886                         reg-names = "qspi_base";
 887                         #address-cells = <1>;
 888                         #size-cells = <0>;
 889                         ti,hwmods = "qspi";
 890                         clocks = <&qspi_gfclk_div>;
 891                         clock-names = "fck";
 892                         num-cs = <4>;
 893                         status = "disabled";
 894                 };
 895
 896                 omap_control_sata: control-phy@4a002374 {
 897                         compatible = "ti,control-phy-pipe3";
 898                         reg = <0x4a002374 0x4>;
 899                         reg-names = "power";
 900                         clocks = <&sys_clkin1>;
 901                         clock-names = "sysclk";
 902                 };
 903
 904                 /* OCP2SCP3 */
 905                 ocp2scp@4a090000 {
 906                         compatible = "ti,omap-ocp2scp";
 907                         #address-cells = <1>;
 908                         #size-cells = <1>;
 909                         ranges;
 910                         reg = <0x4a090000 0x20>;
 911                         ti,hwmods = "ocp2scp3";
 912                         sata_phy: phy@4A096000 {
 913                                 compatible = "ti,phy-pipe3-sata";
 914                                 reg = <0x4A096000 0x80>, /* phy_rx */
 915                                       <0x4A096400 0x64>, /* phy_tx */
 916                                       <0x4A096800 0x40>; /* pll_ctrl */
 917                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 918                                 ctrl-module = <&omap_control_sata>;
 919                                 clocks = <&sys_clkin1>;
 920                                 clock-names = "sysclk";
 921                                 #phy-cells = <0>;
 922                         };
 923                 };
 924
 925                 sata: sata@4a141100 {
 926                         compatible = "snps,dwc-ahci";
 927                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 928                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 929                         phys = <&sata_phy>;
 930                         phy-names = "sata-phy";
 931                         clocks = <&sata_ref_clk>;
 932                         ti,hwmods = "sata";
 933                 };
 934
 935                 omap_control_usb2phy1: control-phy@4a002300 {
 936                         compatible = "ti,control-phy-usb2";
 937                         reg = <0x4a002300 0x4>;
 938                         reg-names = "power";
 939                 };
 940
 941                 omap_control_usb3phy1: control-phy@4a002370 {
 942                         compatible = "ti,control-phy-pipe3";
 943                         reg = <0x4a002370 0x4>;
 944                         reg-names = "power";
 945                 };
 946
 947                 omap_control_usb2phy2: control-phy@0x4a002e74 {
 948                         compatible = "ti,control-phy-usb2-dra7";
 949                         reg = <0x4a002e74 0x4>;
 950                         reg-names = "power";
 951                 };
 952
 953                 /* OCP2SCP1 */
 954                 ocp2scp@4a080000 {
 955                         compatible = "ti,omap-ocp2scp";
 956                         #address-cells = <1>;
 957                         #size-cells = <1>;
 958                         ranges;
 959                         reg = <0x4a080000 0x20>;
 960                         ti,hwmods = "ocp2scp1";
 961
 962                         usb2_phy1: phy@4a084000 {
 963                                 compatible = "ti,omap-usb2";
 964                                 reg = <0x4a084000 0x400>;
 965                                 ctrl-module = <&omap_control_usb2phy1>;
 966                                 clocks = <&usb_phy1_always_on_clk32k>,
 967                                          <&usb_otg_ss1_refclk960m>;
 968                                 clock-names =   "wkupclk",
 969                                                 "refclk";
 970                                 #phy-cells = <0>;
 971                         };
 972
 973                         usb2_phy2: phy@4a085000 {
 974                                 compatible = "ti,omap-usb2";
 975                                 reg = <0x4a085000 0x400>;
 976                                 ctrl-module = <&omap_control_usb2phy2>;
 977                                 clocks = <&usb_phy2_always_on_clk32k>,
 978                                          <&usb_otg_ss2_refclk960m>;
 979                                 clock-names =   "wkupclk",
 980                                                 "refclk";
 981                                 #phy-cells = <0>;
 982                         };
 983
 984                         usb3_phy1: phy@4a084400 {
 985                                 compatible = "ti,omap-usb3";
 986                                 reg = <0x4a084400 0x80>,
 987                                       <0x4a084800 0x64>,
 988                                       <0x4a084c00 0x40>;
 989                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 990                                 ctrl-module = <&omap_control_usb3phy1>;
 991                                 clocks = <&usb_phy3_always_on_clk32k>,
 992                                          <&sys_clkin1>,
 993                                          <&usb_otg_ss1_refclk960m>;
 994                                 clock-names =   "wkupclk",
 995                                                 "sysclk",
 996                                                 "refclk";
 997                                 #phy-cells = <0>;
 998                         };
 999                 };
1000
1001                 omap_dwc3_1@48880000 {
1002                         compatible = "ti,dwc3";
1003                         ti,hwmods = "usb_otg_ss1";
1004                         reg = <0x48880000 0x10000>;
1005                         interrupts = <0 77 4>;
1006                         #address-cells = <1>;
1007                         #size-cells = <1>;
1008                         utmi-mode = <2>;
1009                         ranges;
1010                         usb1: usb@48890000 {
1011                                 compatible = "snps,dwc3";
1012                                 reg = <0x48890000 0x17000>;
1013                                 interrupts = <0 76 4>;
1014                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1015                                 phy-names = "usb2-phy", "usb3-phy";
1016                                 tx-fifo-resize;
1017                                 maximum-speed = "super-speed";
1018                                 dr_mode = "otg";
1019                         };
1020                 };
1021
1022                 omap_dwc3_2@488c0000 {
1023                         compatible = "ti,dwc3";
1024                         ti,hwmods = "usb_otg_ss2";
1025                         reg = <0x488c0000 0x10000>;
1026                         interrupts = <0 92 4>;
1027                         #address-cells = <1>;
1028                         #size-cells = <1>;
1029                         utmi-mode = <2>;
1030                         ranges;
1031                         usb2: usb@488d0000 {
1032                                 compatible = "snps,dwc3";
1033                                 reg = <0x488d0000 0x17000>;
1034                                 interrupts = <0 78 4>;
1035                                 phys = <&usb2_phy2>;
1036                                 phy-names = "usb2-phy";
1037                                 tx-fifo-resize;
1038                                 maximum-speed = "high-speed";
1039                                 dr_mode = "otg";
1040                         };
1041                 };
1042
1043                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1044                 omap_dwc3_3@48900000 {
1045                         compatible = "ti,dwc3";
1046                         ti,hwmods = "usb_otg_ss3";
1047                         reg = <0x48900000 0x10000>;
1048                 /*      interrupts = <0 TBD 4>; */
1049                         #address-cells = <1>;
1050                         #size-cells = <1>;
1051                         utmi-mode = <2>;
1052                         ranges;
1053                         status = "disabled";
1054                         usb3: usb@48910000 {
1055                                 compatible = "snps,dwc3";
1056                                 reg = <0x48910000 0x17000>;
1057                 /*              interrupts = <0 93 4>; */
1058                                 tx-fifo-resize;
1059                                 maximum-speed = "high-speed";
1060                                 dr_mode = "otg";
1061                         };
1062                 };
1063
1064                 omap_dwc3_4@48940000 {
1065                         compatible = "ti,dwc3";
1066                         ti,hwmods = "usb_otg_ss4";
1067                         reg = <0x48940000 0x10000>;
1068                 /*      interrupts = <0 TBD 4>; */
1069                         #address-cells = <1>;
1070                         #size-cells = <1>;
1071                         utmi-mode = <2>;
1072                         ranges;
1073                         status = "disabled";
1074                         usb4: usb@48950000 {
1075                                 compatible = "snps,dwc3";
1076                                 reg = <0x48950000 0x17000>;
1077                 /*              interrupts = <0 TBD 4>; */
1078                                 tx-fifo-resize;
1079                                 maximum-speed = "high-speed";
1080                                 dr_mode = "otg";
1081                         };
1082                 };
1083
1084                 elm: elm@48078000 {
1085                         compatible = "ti,am3352-elm";
1086                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1087                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1088                         ti,hwmods = "elm";
1089                         status = "disabled";
1090                 };
1091
1092                 gpmc: gpmc@50000000 {
1093                         compatible = "ti,am3352-gpmc";
1094                         ti,hwmods = "gpmc";
1095                         reg = <0x50000000 0x37c>;      /* device IO registers */
1096                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1097                         gpmc,num-cs = <8>;
1098                         gpmc,num-waitpins = <2>;
1099                         #address-cells = <2>;
1100                         #size-cells = <1>;
1101                         status = "disabled";
1102                 };
1103
1104                 atl: atl@4843c000 {
1105                         compatible = "ti,dra7-atl";
1106                         reg = <0x4843c000 0x3ff>;
1107                         ti,hwmods = "atl";
1108                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1109                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1110                         clocks = <&atl_gfclk_mux>;
1111                         clock-names = "fck";
1112                         status = "disabled";
1113                 };
1114         };
1115 };
1116
1117 /include/ "dra7xx-clocks.dtsi"