2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
15 #define MAX_SOURCES 400
21 compatible = "ti,dra7xx";
22 interrupt-parent = <&crossbar_mpu>;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
59 #interrupt-cells = <3>;
60 reg = <0x48211000 0x1000>,
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 #interrupt-cells = <3>;
72 reg = <0x48281000 0x1000>;
73 interrupt-parent = <&gic>;
77 * The soc node represents the soc top level view. It is used for IPs
78 * that are not memory mapped in the MPU view or for the MPU itself.
81 compatible = "ti,omap-infra";
83 compatible = "ti,omap5-mpu";
89 * XXX: Use a flat representation of the SOC interconnect.
90 * The real OMAP interconnect network is quite complex.
91 * Since it will not bring real advantage to represent that in DT for
92 * the moment, just use a fake OCP bus entry to represent the whole bus
96 compatible = "ti,dra7-l3-noc", "simple-bus";
100 ti,hwmods = "l3_main_1", "l3_main_2";
101 reg = <0x44000000 0x1000000>,
103 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
104 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106 l4_cfg: l4@4a000000 {
107 compatible = "ti,dra7-l4-cfg", "simple-bus";
108 #address-cells = <1>;
110 ranges = <0 0x4a000000 0x22c000>;
113 compatible = "ti,dra7-scm-core", "simple-bus";
114 reg = <0x2000 0x2000>;
115 #address-cells = <1>;
117 ranges = <0 0x2000 0x2000>;
119 scm_conf: scm_conf@0 {
120 compatible = "syscon", "simple-bus";
122 #address-cells = <1>;
124 ranges = <0 0x0 0x1400>;
126 pbias_regulator: pbias_regulator {
127 compatible = "ti,pbias-dra7", "ti,pbias-omap";
129 syscon = <&scm_conf>;
130 pbias_mmc_reg: pbias_mmc_omap5 {
131 regulator-name = "pbias_mmc_omap5";
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <3000000>;
137 scm_conf_clocks: clocks {
138 #address-cells = <1>;
143 dra7_pmx_core: pinmux@1400 {
144 compatible = "ti,dra7-padconf",
146 reg = <0x1400 0x0468>;
147 #address-cells = <1>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <32>;
152 pinctrl-single,function-mask = <0x3fffffff>;
155 scm_conf1: scm_conf@1c04 {
156 compatible = "syscon";
157 reg = <0x1c04 0x0020>;
160 scm_conf_pcie: scm_conf@1c24 {
161 compatible = "syscon";
162 reg = <0x1c24 0x0024>;
166 cm_core_aon: cm_core_aon@5000 {
167 compatible = "ti,dra7-cm-core-aon";
168 reg = <0x5000 0x2000>;
170 cm_core_aon_clocks: clocks {
171 #address-cells = <1>;
175 cm_core_aon_clockdomains: clockdomains {
179 cm_core: cm_core@8000 {
180 compatible = "ti,dra7-cm-core";
181 reg = <0x8000 0x3000>;
183 cm_core_clocks: clocks {
184 #address-cells = <1>;
188 cm_core_clockdomains: clockdomains {
193 l4_wkup: l4@4ae00000 {
194 compatible = "ti,dra7-l4-wkup", "simple-bus";
195 #address-cells = <1>;
197 ranges = <0 0x4ae00000 0x3f000>;
199 counter32k: counter@4000 {
200 compatible = "ti,omap-counter32k";
202 ti,hwmods = "counter_32k";
206 compatible = "ti,dra7-prm";
207 reg = <0x6000 0x3000>;
208 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
215 prm_clockdomains: clockdomains {
221 compatible = "simple-bus";
223 #address-cells = <1>;
224 ranges = <0x51000000 0x51000000 0x3000
225 0x0 0x20000000 0x10000000>;
226 pcie1: pcie@51000000 {
227 compatible = "ti,dra7-pcie";
228 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
229 reg-names = "rc_dbics", "ti_conf", "config";
230 interrupts = <0 232 0x4>, <0 233 0x4>;
231 #address-cells = <3>;
234 ranges = <0x81000000 0 0 0x03000 0 0x00010000
235 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
236 #interrupt-cells = <1>;
240 phy-names = "pcie-phy0";
241 interrupt-map-mask = <0 0 0 7>;
242 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
243 <0 0 0 2 &pcie1_intc 2>,
244 <0 0 0 3 &pcie1_intc 3>,
245 <0 0 0 4 &pcie1_intc 4>;
246 pcie1_intc: interrupt-controller {
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <1>;
255 compatible = "simple-bus";
257 #address-cells = <1>;
258 ranges = <0x51800000 0x51800000 0x3000
259 0x0 0x30000000 0x10000000>;
262 compatible = "ti,dra7-pcie";
263 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
264 reg-names = "rc_dbics", "ti_conf", "config";
265 interrupts = <0 355 0x4>, <0 356 0x4>;
266 #address-cells = <3>;
269 ranges = <0x81000000 0 0 0x03000 0 0x00010000
270 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
271 #interrupt-cells = <1>;
275 phy-names = "pcie-phy0";
276 interrupt-map-mask = <0 0 0 7>;
277 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
278 <0 0 0 2 &pcie2_intc 2>,
279 <0 0 0 3 &pcie2_intc 3>,
280 <0 0 0 4 &pcie2_intc 4>;
281 pcie2_intc: interrupt-controller {
282 interrupt-controller;
283 #address-cells = <0>;
284 #interrupt-cells = <1>;
289 bandgap: bandgap@4a0021e0 {
290 reg = <0x4a0021e0 0xc
296 compatible = "ti,dra752-bandgap";
297 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
298 #thermal-sensor-cells = <1>;
301 dsp1_system: dsp_system@40d00000 {
302 compatible = "syscon";
303 reg = <0x40d00000 0x100>;
306 sdma: dma-controller@4a056000 {
307 compatible = "ti,omap4430-sdma";
308 reg = <0x4a056000 0x1000>;
309 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
315 dma-requests = <127>;
318 sdma_xbar: dma-router@4a002b78 {
319 compatible = "ti,dra7-dma-crossbar";
320 reg = <0x4a002b78 0xfc>;
322 dma-requests = <205>;
323 ti,dma-safe-map = <0>;
324 dma-masters = <&sdma>;
327 gpio1: gpio@4ae10000 {
328 compatible = "ti,omap4-gpio";
329 reg = <0x4ae10000 0x200>;
330 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
338 gpio2: gpio@48055000 {
339 compatible = "ti,omap4-gpio";
340 reg = <0x48055000 0x200>;
341 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
349 gpio3: gpio@48057000 {
350 compatible = "ti,omap4-gpio";
351 reg = <0x48057000 0x200>;
352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 gpio4: gpio@48059000 {
361 compatible = "ti,omap4-gpio";
362 reg = <0x48059000 0x200>;
363 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
371 gpio5: gpio@4805b000 {
372 compatible = "ti,omap4-gpio";
373 reg = <0x4805b000 0x200>;
374 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
382 gpio6: gpio@4805d000 {
383 compatible = "ti,omap4-gpio";
384 reg = <0x4805d000 0x200>;
385 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
393 gpio7: gpio@48051000 {
394 compatible = "ti,omap4-gpio";
395 reg = <0x48051000 0x200>;
396 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
404 gpio8: gpio@48053000 {
405 compatible = "ti,omap4-gpio";
406 reg = <0x48053000 0x200>;
407 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-controller;
412 #interrupt-cells = <2>;
415 uart1: serial@4806a000 {
416 compatible = "ti,dra742-uart", "ti,omap4-uart";
417 reg = <0x4806a000 0x100>;
418 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
420 clock-frequency = <48000000>;
422 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
423 dma-names = "tx", "rx";
426 uart2: serial@4806c000 {
427 compatible = "ti,dra742-uart", "ti,omap4-uart";
428 reg = <0x4806c000 0x100>;
429 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
431 clock-frequency = <48000000>;
433 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
434 dma-names = "tx", "rx";
437 uart3: serial@48020000 {
438 compatible = "ti,dra742-uart", "ti,omap4-uart";
439 reg = <0x48020000 0x100>;
440 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
442 clock-frequency = <48000000>;
444 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
445 dma-names = "tx", "rx";
448 uart4: serial@4806e000 {
449 compatible = "ti,dra742-uart", "ti,omap4-uart";
450 reg = <0x4806e000 0x100>;
451 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <48000000>;
455 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
456 dma-names = "tx", "rx";
459 uart5: serial@48066000 {
460 compatible = "ti,dra742-uart", "ti,omap4-uart";
461 reg = <0x48066000 0x100>;
462 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
464 clock-frequency = <48000000>;
466 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
467 dma-names = "tx", "rx";
470 uart6: serial@48068000 {
471 compatible = "ti,dra742-uart", "ti,omap4-uart";
472 reg = <0x48068000 0x100>;
473 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
475 clock-frequency = <48000000>;
477 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
478 dma-names = "tx", "rx";
481 uart7: serial@48420000 {
482 compatible = "ti,dra742-uart", "ti,omap4-uart";
483 reg = <0x48420000 0x100>;
484 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
486 clock-frequency = <48000000>;
490 uart8: serial@48422000 {
491 compatible = "ti,dra742-uart", "ti,omap4-uart";
492 reg = <0x48422000 0x100>;
493 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
495 clock-frequency = <48000000>;
499 uart9: serial@48424000 {
500 compatible = "ti,dra742-uart", "ti,omap4-uart";
501 reg = <0x48424000 0x100>;
502 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
504 clock-frequency = <48000000>;
508 uart10: serial@4ae2b000 {
509 compatible = "ti,dra742-uart", "ti,omap4-uart";
510 reg = <0x4ae2b000 0x100>;
511 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
512 ti,hwmods = "uart10";
513 clock-frequency = <48000000>;
517 mailbox1: mailbox@4a0f4000 {
518 compatible = "ti,omap4-mailbox";
519 reg = <0x4a0f4000 0x200>;
520 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "mailbox1";
525 ti,mbox-num-users = <3>;
526 ti,mbox-num-fifos = <8>;
530 mailbox2: mailbox@4883a000 {
531 compatible = "ti,omap4-mailbox";
532 reg = <0x4883a000 0x200>;
533 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
537 ti,hwmods = "mailbox2";
539 ti,mbox-num-users = <4>;
540 ti,mbox-num-fifos = <12>;
544 mailbox3: mailbox@4883c000 {
545 compatible = "ti,omap4-mailbox";
546 reg = <0x4883c000 0x200>;
547 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "mailbox3";
553 ti,mbox-num-users = <4>;
554 ti,mbox-num-fifos = <12>;
558 mailbox4: mailbox@4883e000 {
559 compatible = "ti,omap4-mailbox";
560 reg = <0x4883e000 0x200>;
561 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "mailbox4";
567 ti,mbox-num-users = <4>;
568 ti,mbox-num-fifos = <12>;
572 mailbox5: mailbox@48840000 {
573 compatible = "ti,omap4-mailbox";
574 reg = <0x48840000 0x200>;
575 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
579 ti,hwmods = "mailbox5";
581 ti,mbox-num-users = <4>;
582 ti,mbox-num-fifos = <12>;
586 mailbox6: mailbox@48842000 {
587 compatible = "ti,omap4-mailbox";
588 reg = <0x48842000 0x200>;
589 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
593 ti,hwmods = "mailbox6";
595 ti,mbox-num-users = <4>;
596 ti,mbox-num-fifos = <12>;
600 mailbox7: mailbox@48844000 {
601 compatible = "ti,omap4-mailbox";
602 reg = <0x48844000 0x200>;
603 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
607 ti,hwmods = "mailbox7";
609 ti,mbox-num-users = <4>;
610 ti,mbox-num-fifos = <12>;
614 mailbox8: mailbox@48846000 {
615 compatible = "ti,omap4-mailbox";
616 reg = <0x48846000 0x200>;
617 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
621 ti,hwmods = "mailbox8";
623 ti,mbox-num-users = <4>;
624 ti,mbox-num-fifos = <12>;
628 mailbox9: mailbox@4885e000 {
629 compatible = "ti,omap4-mailbox";
630 reg = <0x4885e000 0x200>;
631 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
635 ti,hwmods = "mailbox9";
637 ti,mbox-num-users = <4>;
638 ti,mbox-num-fifos = <12>;
642 mailbox10: mailbox@48860000 {
643 compatible = "ti,omap4-mailbox";
644 reg = <0x48860000 0x200>;
645 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "mailbox10";
651 ti,mbox-num-users = <4>;
652 ti,mbox-num-fifos = <12>;
656 mailbox11: mailbox@48862000 {
657 compatible = "ti,omap4-mailbox";
658 reg = <0x48862000 0x200>;
659 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "mailbox11";
665 ti,mbox-num-users = <4>;
666 ti,mbox-num-fifos = <12>;
670 mailbox12: mailbox@48864000 {
671 compatible = "ti,omap4-mailbox";
672 reg = <0x48864000 0x200>;
673 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
677 ti,hwmods = "mailbox12";
679 ti,mbox-num-users = <4>;
680 ti,mbox-num-fifos = <12>;
684 mailbox13: mailbox@48802000 {
685 compatible = "ti,omap4-mailbox";
686 reg = <0x48802000 0x200>;
687 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
691 ti,hwmods = "mailbox13";
693 ti,mbox-num-users = <4>;
694 ti,mbox-num-fifos = <12>;
698 timer1: timer@4ae18000 {
699 compatible = "ti,omap5430-timer";
700 reg = <0x4ae18000 0x80>;
701 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
702 ti,hwmods = "timer1";
706 timer2: timer@48032000 {
707 compatible = "ti,omap5430-timer";
708 reg = <0x48032000 0x80>;
709 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
710 ti,hwmods = "timer2";
713 timer3: timer@48034000 {
714 compatible = "ti,omap5430-timer";
715 reg = <0x48034000 0x80>;
716 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
717 ti,hwmods = "timer3";
720 timer4: timer@48036000 {
721 compatible = "ti,omap5430-timer";
722 reg = <0x48036000 0x80>;
723 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
724 ti,hwmods = "timer4";
727 timer5: timer@48820000 {
728 compatible = "ti,omap5430-timer";
729 reg = <0x48820000 0x80>;
730 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
731 ti,hwmods = "timer5";
734 timer6: timer@48822000 {
735 compatible = "ti,omap5430-timer";
736 reg = <0x48822000 0x80>;
737 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "timer6";
741 timer7: timer@48824000 {
742 compatible = "ti,omap5430-timer";
743 reg = <0x48824000 0x80>;
744 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
745 ti,hwmods = "timer7";
748 timer8: timer@48826000 {
749 compatible = "ti,omap5430-timer";
750 reg = <0x48826000 0x80>;
751 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "timer8";
755 timer9: timer@4803e000 {
756 compatible = "ti,omap5430-timer";
757 reg = <0x4803e000 0x80>;
758 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
759 ti,hwmods = "timer9";
762 timer10: timer@48086000 {
763 compatible = "ti,omap5430-timer";
764 reg = <0x48086000 0x80>;
765 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
766 ti,hwmods = "timer10";
769 timer11: timer@48088000 {
770 compatible = "ti,omap5430-timer";
771 reg = <0x48088000 0x80>;
772 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
773 ti,hwmods = "timer11";
776 timer13: timer@48828000 {
777 compatible = "ti,omap5430-timer";
778 reg = <0x48828000 0x80>;
779 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "timer13";
784 timer14: timer@4882a000 {
785 compatible = "ti,omap5430-timer";
786 reg = <0x4882a000 0x80>;
787 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
788 ti,hwmods = "timer14";
792 timer15: timer@4882c000 {
793 compatible = "ti,omap5430-timer";
794 reg = <0x4882c000 0x80>;
795 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
796 ti,hwmods = "timer15";
800 timer16: timer@4882e000 {
801 compatible = "ti,omap5430-timer";
802 reg = <0x4882e000 0x80>;
803 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
804 ti,hwmods = "timer16";
809 compatible = "ti,omap3-wdt";
810 reg = <0x4ae14000 0x80>;
811 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
812 ti,hwmods = "wd_timer2";
815 hwspinlock: spinlock@4a0f6000 {
816 compatible = "ti,omap4-hwspinlock";
817 reg = <0x4a0f6000 0x1000>;
818 ti,hwmods = "spinlock";
823 compatible = "ti,omap5-dmm";
824 reg = <0x4e000000 0x800>;
825 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
830 compatible = "ti,omap4-i2c";
831 reg = <0x48070000 0x100>;
832 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
833 #address-cells = <1>;
840 compatible = "ti,omap4-i2c";
841 reg = <0x48072000 0x100>;
842 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
843 #address-cells = <1>;
850 compatible = "ti,omap4-i2c";
851 reg = <0x48060000 0x100>;
852 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
853 #address-cells = <1>;
860 compatible = "ti,omap4-i2c";
861 reg = <0x4807a000 0x100>;
862 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
863 #address-cells = <1>;
870 compatible = "ti,omap4-i2c";
871 reg = <0x4807c000 0x100>;
872 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
873 #address-cells = <1>;
880 compatible = "ti,omap4-hsmmc";
881 reg = <0x4809c000 0x400>;
882 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
885 ti,needs-special-reset;
886 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
887 dma-names = "tx", "rx";
889 pbias-supply = <&pbias_mmc_reg>;
893 compatible = "ti,omap4-hsmmc";
894 reg = <0x480b4000 0x400>;
895 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
897 ti,needs-special-reset;
898 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
899 dma-names = "tx", "rx";
904 compatible = "ti,omap4-hsmmc";
905 reg = <0x480ad000 0x400>;
906 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
908 ti,needs-special-reset;
909 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
910 dma-names = "tx", "rx";
915 compatible = "ti,omap4-hsmmc";
916 reg = <0x480d1000 0x400>;
917 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
919 ti,needs-special-reset;
920 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
921 dma-names = "tx", "rx";
925 mmu0_dsp1: mmu@40d01000 {
926 compatible = "ti,dra7-dsp-iommu";
927 reg = <0x40d01000 0x100>;
928 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
929 ti,hwmods = "mmu0_dsp1";
931 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
935 mmu1_dsp1: mmu@40d02000 {
936 compatible = "ti,dra7-dsp-iommu";
937 reg = <0x40d02000 0x100>;
938 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
939 ti,hwmods = "mmu1_dsp1";
941 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
945 mmu_ipu1: mmu@58882000 {
946 compatible = "ti,dra7-iommu";
947 reg = <0x58882000 0x100>;
948 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
949 ti,hwmods = "mmu_ipu1";
951 ti,iommu-bus-err-back;
955 mmu_ipu2: mmu@55082000 {
956 compatible = "ti,dra7-iommu";
957 reg = <0x55082000 0x100>;
958 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
959 ti,hwmods = "mmu_ipu2";
961 ti,iommu-bus-err-back;
965 abb_mpu: regulator-abb-mpu {
966 compatible = "ti,abb-v3";
967 regulator-name = "abb_mpu";
968 #address-cells = <0>;
970 clocks = <&sys_clkin1>;
971 ti,settling-time = <50>;
972 ti,clock-cycles = <16>;
974 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
975 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
977 reg-names = "setup-address", "control-address",
978 "int-address", "efuse-address",
980 ti,tranxdone-status-mask = <0x80>;
981 /* LDOVBBMPU_FBB_MUX_CTRL */
982 ti,ldovbb-override-mask = <0x400>;
983 /* LDOVBBMPU_FBB_VSET_OUT */
984 ti,ldovbb-vset-mask = <0x1F>;
987 * NOTE: only FBB mode used but actual vset will
988 * determine final biasing
991 /*uV ABB efuse rbb_m fbb_m vset_m*/
992 1060000 0 0x0 0 0x02000000 0x01F00000
993 1160000 0 0x4 0 0x02000000 0x01F00000
994 1210000 0 0x8 0 0x02000000 0x01F00000
998 abb_ivahd: regulator-abb-ivahd {
999 compatible = "ti,abb-v3";
1000 regulator-name = "abb_ivahd";
1001 #address-cells = <0>;
1003 clocks = <&sys_clkin1>;
1004 ti,settling-time = <50>;
1005 ti,clock-cycles = <16>;
1007 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1008 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1010 reg-names = "setup-address", "control-address",
1011 "int-address", "efuse-address",
1013 ti,tranxdone-status-mask = <0x40000000>;
1014 /* LDOVBBIVA_FBB_MUX_CTRL */
1015 ti,ldovbb-override-mask = <0x400>;
1016 /* LDOVBBIVA_FBB_VSET_OUT */
1017 ti,ldovbb-vset-mask = <0x1F>;
1020 * NOTE: only FBB mode used but actual vset will
1021 * determine final biasing
1024 /*uV ABB efuse rbb_m fbb_m vset_m*/
1025 1055000 0 0x0 0 0x02000000 0x01F00000
1026 1150000 0 0x4 0 0x02000000 0x01F00000
1027 1250000 0 0x8 0 0x02000000 0x01F00000
1031 abb_dspeve: regulator-abb-dspeve {
1032 compatible = "ti,abb-v3";
1033 regulator-name = "abb_dspeve";
1034 #address-cells = <0>;
1036 clocks = <&sys_clkin1>;
1037 ti,settling-time = <50>;
1038 ti,clock-cycles = <16>;
1040 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1041 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1043 reg-names = "setup-address", "control-address",
1044 "int-address", "efuse-address",
1046 ti,tranxdone-status-mask = <0x20000000>;
1047 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1048 ti,ldovbb-override-mask = <0x400>;
1049 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1050 ti,ldovbb-vset-mask = <0x1F>;
1053 * NOTE: only FBB mode used but actual vset will
1054 * determine final biasing
1057 /*uV ABB efuse rbb_m fbb_m vset_m*/
1058 1055000 0 0x0 0 0x02000000 0x01F00000
1059 1150000 0 0x4 0 0x02000000 0x01F00000
1060 1250000 0 0x8 0 0x02000000 0x01F00000
1064 abb_gpu: regulator-abb-gpu {
1065 compatible = "ti,abb-v3";
1066 regulator-name = "abb_gpu";
1067 #address-cells = <0>;
1069 clocks = <&sys_clkin1>;
1070 ti,settling-time = <50>;
1071 ti,clock-cycles = <16>;
1073 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1074 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1076 reg-names = "setup-address", "control-address",
1077 "int-address", "efuse-address",
1079 ti,tranxdone-status-mask = <0x10000000>;
1080 /* LDOVBBGPU_FBB_MUX_CTRL */
1081 ti,ldovbb-override-mask = <0x400>;
1082 /* LDOVBBGPU_FBB_VSET_OUT */
1083 ti,ldovbb-vset-mask = <0x1F>;
1086 * NOTE: only FBB mode used but actual vset will
1087 * determine final biasing
1090 /*uV ABB efuse rbb_m fbb_m vset_m*/
1091 1090000 0 0x0 0 0x02000000 0x01F00000
1092 1210000 0 0x4 0 0x02000000 0x01F00000
1093 1280000 0 0x8 0 0x02000000 0x01F00000
1097 mcspi1: spi@48098000 {
1098 compatible = "ti,omap4-mcspi";
1099 reg = <0x48098000 0x200>;
1100 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1101 #address-cells = <1>;
1103 ti,hwmods = "mcspi1";
1104 ti,spi-num-cs = <4>;
1105 dmas = <&sdma_xbar 35>,
1113 dma-names = "tx0", "rx0", "tx1", "rx1",
1114 "tx2", "rx2", "tx3", "rx3";
1115 status = "disabled";
1118 mcspi2: spi@4809a000 {
1119 compatible = "ti,omap4-mcspi";
1120 reg = <0x4809a000 0x200>;
1121 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1122 #address-cells = <1>;
1124 ti,hwmods = "mcspi2";
1125 ti,spi-num-cs = <2>;
1126 dmas = <&sdma_xbar 43>,
1130 dma-names = "tx0", "rx0", "tx1", "rx1";
1131 status = "disabled";
1134 mcspi3: spi@480b8000 {
1135 compatible = "ti,omap4-mcspi";
1136 reg = <0x480b8000 0x200>;
1137 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1138 #address-cells = <1>;
1140 ti,hwmods = "mcspi3";
1141 ti,spi-num-cs = <2>;
1142 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1143 dma-names = "tx0", "rx0";
1144 status = "disabled";
1147 mcspi4: spi@480ba000 {
1148 compatible = "ti,omap4-mcspi";
1149 reg = <0x480ba000 0x200>;
1150 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cells = <1>;
1153 ti,hwmods = "mcspi4";
1154 ti,spi-num-cs = <1>;
1155 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1156 dma-names = "tx0", "rx0";
1157 status = "disabled";
1160 qspi: qspi@4b300000 {
1161 compatible = "ti,dra7xxx-qspi";
1162 reg = <0x4b300000 0x100>,
1163 <0x5c000000 0x4000000>;
1164 reg-names = "qspi_base", "qspi_mmap";
1165 syscon-chipselects = <&scm_conf 0x558>;
1166 #address-cells = <1>;
1169 clocks = <&qspi_gfclk_div>;
1170 clock-names = "fck";
1172 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1173 status = "disabled";
1176 omap_control_sata: control-phy@4a002374 {
1177 compatible = "ti,control-phy-pipe3";
1178 reg = <0x4a002374 0x4>;
1179 reg-names = "power";
1180 clocks = <&sys_clkin1>;
1181 clock-names = "sysclk";
1186 compatible = "ti,omap-ocp2scp";
1187 #address-cells = <1>;
1190 reg = <0x4a090000 0x20>;
1191 ti,hwmods = "ocp2scp3";
1192 sata_phy: phy@4A096000 {
1193 compatible = "ti,phy-pipe3-sata";
1194 reg = <0x4A096000 0x80>, /* phy_rx */
1195 <0x4A096400 0x64>, /* phy_tx */
1196 <0x4A096800 0x40>; /* pll_ctrl */
1197 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1198 ctrl-module = <&omap_control_sata>;
1199 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1200 clock-names = "sysclk", "refclk";
1201 syscon-pllreset = <&scm_conf 0x3fc>;
1205 pcie1_phy: pciephy@4a094000 {
1206 compatible = "ti,phy-pipe3-pcie";
1207 reg = <0x4a094000 0x80>, /* phy_rx */
1208 <0x4a094400 0x64>; /* phy_tx */
1209 reg-names = "phy_rx", "phy_tx";
1210 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1211 syscon-pcs = <&scm_conf_pcie 0x10>;
1212 clocks = <&dpll_pcie_ref_ck>,
1213 <&dpll_pcie_ref_m2ldo_ck>,
1214 <&optfclk_pciephy1_32khz>,
1215 <&optfclk_pciephy1_clk>,
1216 <&optfclk_pciephy1_div_clk>,
1217 <&optfclk_pciephy_div>,
1219 clock-names = "dpll_ref", "dpll_ref_m2",
1220 "wkupclk", "refclk",
1221 "div-clk", "phy-div", "sysclk";
1225 pcie2_phy: pciephy@4a095000 {
1226 compatible = "ti,phy-pipe3-pcie";
1227 reg = <0x4a095000 0x80>, /* phy_rx */
1228 <0x4a095400 0x64>; /* phy_tx */
1229 reg-names = "phy_rx", "phy_tx";
1230 syscon-phy-power = <&scm_conf_pcie 0x20>;
1231 syscon-pcs = <&scm_conf_pcie 0x10>;
1232 clocks = <&dpll_pcie_ref_ck>,
1233 <&dpll_pcie_ref_m2ldo_ck>,
1234 <&optfclk_pciephy2_32khz>,
1235 <&optfclk_pciephy2_clk>,
1236 <&optfclk_pciephy2_div_clk>,
1237 <&optfclk_pciephy_div>,
1239 clock-names = "dpll_ref", "dpll_ref_m2",
1240 "wkupclk", "refclk",
1241 "div-clk", "phy-div", "sysclk";
1243 status = "disabled";
1247 sata: sata@4a141100 {
1248 compatible = "snps,dwc-ahci";
1249 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1250 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1252 phy-names = "sata-phy";
1253 clocks = <&sata_ref_clk>;
1258 compatible = "ti,am3352-rtc";
1259 reg = <0x48838000 0x100>;
1260 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1262 ti,hwmods = "rtcss";
1263 clocks = <&sys_32k_ck>;
1266 omap_control_usb2phy1: control-phy@4a002300 {
1267 compatible = "ti,control-phy-usb2";
1268 reg = <0x4a002300 0x4>;
1269 reg-names = "power";
1272 omap_control_usb3phy1: control-phy@4a002370 {
1273 compatible = "ti,control-phy-pipe3";
1274 reg = <0x4a002370 0x4>;
1275 reg-names = "power";
1278 omap_control_usb2phy2: control-phy@0x4a002e74 {
1279 compatible = "ti,control-phy-usb2-dra7";
1280 reg = <0x4a002e74 0x4>;
1281 reg-names = "power";
1286 compatible = "ti,omap-ocp2scp";
1287 #address-cells = <1>;
1290 reg = <0x4a080000 0x20>;
1291 ti,hwmods = "ocp2scp1";
1293 usb2_phy1: phy@4a084000 {
1294 compatible = "ti,omap-usb2";
1295 reg = <0x4a084000 0x400>;
1296 ctrl-module = <&omap_control_usb2phy1>;
1297 clocks = <&usb_phy1_always_on_clk32k>,
1298 <&usb_otg_ss1_refclk960m>;
1299 clock-names = "wkupclk",
1304 usb2_phy2: phy@4a085000 {
1305 compatible = "ti,dra7x-usb2-phy2",
1307 reg = <0x4a085000 0x400>;
1308 ctrl-module = <&omap_control_usb2phy2>;
1309 clocks = <&usb_phy2_always_on_clk32k>,
1310 <&usb_otg_ss2_refclk960m>;
1311 clock-names = "wkupclk",
1316 usb3_phy1: phy@4a084400 {
1317 compatible = "ti,omap-usb3";
1318 reg = <0x4a084400 0x80>,
1321 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1322 ctrl-module = <&omap_control_usb3phy1>;
1323 clocks = <&usb_phy3_always_on_clk32k>,
1325 <&usb_otg_ss1_refclk960m>;
1326 clock-names = "wkupclk",
1333 omap_dwc3_1: omap_dwc3_1@48880000 {
1334 compatible = "ti,dwc3";
1335 ti,hwmods = "usb_otg_ss1";
1336 reg = <0x48880000 0x10000>;
1337 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1338 #address-cells = <1>;
1342 usb1: usb@48890000 {
1343 compatible = "snps,dwc3";
1344 reg = <0x48890000 0x17000>;
1345 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1348 interrupt-names = "peripheral",
1351 phys = <&usb2_phy1>, <&usb3_phy1>;
1352 phy-names = "usb2-phy", "usb3-phy";
1354 maximum-speed = "super-speed";
1356 snps,dis_u3_susphy_quirk;
1357 snps,dis_u2_susphy_quirk;
1361 omap_dwc3_2: omap_dwc3_2@488c0000 {
1362 compatible = "ti,dwc3";
1363 ti,hwmods = "usb_otg_ss2";
1364 reg = <0x488c0000 0x10000>;
1365 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1366 #address-cells = <1>;
1370 usb2: usb@488d0000 {
1371 compatible = "snps,dwc3";
1372 reg = <0x488d0000 0x17000>;
1373 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1376 interrupt-names = "peripheral",
1379 phys = <&usb2_phy2>;
1380 phy-names = "usb2-phy";
1382 maximum-speed = "high-speed";
1384 snps,dis_u3_susphy_quirk;
1385 snps,dis_u2_susphy_quirk;
1389 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1390 omap_dwc3_3: omap_dwc3_3@48900000 {
1391 compatible = "ti,dwc3";
1392 ti,hwmods = "usb_otg_ss3";
1393 reg = <0x48900000 0x10000>;
1394 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1395 #address-cells = <1>;
1399 status = "disabled";
1400 usb3: usb@48910000 {
1401 compatible = "snps,dwc3";
1402 reg = <0x48910000 0x17000>;
1403 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1406 interrupt-names = "peripheral",
1410 maximum-speed = "high-speed";
1412 snps,dis_u3_susphy_quirk;
1413 snps,dis_u2_susphy_quirk;
1418 compatible = "ti,am3352-elm";
1419 reg = <0x48078000 0xfc0>; /* device IO registers */
1420 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1422 status = "disabled";
1425 gpmc: gpmc@50000000 {
1426 compatible = "ti,am3352-gpmc";
1428 reg = <0x50000000 0x37c>; /* device IO registers */
1429 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1431 gpmc,num-waitpins = <2>;
1432 #address-cells = <2>;
1434 status = "disabled";
1438 compatible = "ti,dra7-atl";
1439 reg = <0x4843c000 0x3ff>;
1441 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1442 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1443 clocks = <&atl_gfclk_mux>;
1444 clock-names = "fck";
1445 status = "disabled";
1448 mcasp3: mcasp@48468000 {
1449 compatible = "ti,dra7-mcasp-audio";
1450 ti,hwmods = "mcasp3";
1451 reg = <0x48468000 0x2000>;
1453 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1455 interrupt-names = "tx", "rx";
1456 dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
1457 dma-names = "tx", "rx";
1458 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1459 clock-names = "fck", "ahclkx";
1460 status = "disabled";
1463 crossbar_mpu: crossbar@4a002a48 {
1464 compatible = "ti,irq-crossbar";
1465 reg = <0x4a002a48 0x130>;
1466 interrupt-controller;
1467 interrupt-parent = <&wakeupgen>;
1468 #interrupt-cells = <3>;
1469 ti,max-irqs = <160>;
1470 ti,max-crossbar-sources = <MAX_SOURCES>;
1472 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1473 ti,irqs-skip = <10 133 139 140>;
1474 ti,irqs-safe-map = <0>;
1477 mac: ethernet@48484000 {
1478 compatible = "ti,dra7-cpsw","ti,cpsw";
1480 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1481 clock-names = "fck", "cpts";
1482 cpdma_channels = <8>;
1483 ale_entries = <1024>;
1484 bd_ram_size = <0x2000>;
1487 mac_control = <0x20>;
1490 cpts_clock_mult = <0x80000000>;
1491 cpts_clock_shift = <29>;
1492 reg = <0x48484000 0x1000
1494 #address-cells = <1>;
1502 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1507 syscon = <&scm_conf>;
1508 status = "disabled";
1510 davinci_mdio: mdio@48485000 {
1511 compatible = "ti,davinci_mdio";
1512 #address-cells = <1>;
1514 ti,hwmods = "davinci_mdio";
1515 bus_freq = <1000000>;
1516 reg = <0x48485000 0x100>;
1519 cpsw_emac0: slave@48480200 {
1520 /* Filled in by U-Boot */
1521 mac-address = [ 00 00 00 00 00 00 ];
1524 cpsw_emac1: slave@48480300 {
1525 /* Filled in by U-Boot */
1526 mac-address = [ 00 00 00 00 00 00 ];
1529 phy_sel: cpsw-phy-sel@4a002554 {
1530 compatible = "ti,dra7xx-cpsw-phy-sel";
1531 reg= <0x4a002554 0x4>;
1532 reg-names = "gmii-sel";
1536 dcan1: can@481cc000 {
1537 compatible = "ti,dra7-d_can";
1538 ti,hwmods = "dcan1";
1539 reg = <0x4ae3c000 0x2000>;
1540 syscon-raminit = <&scm_conf 0x558 0>;
1541 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1542 clocks = <&dcan1_sys_clk_mux>;
1543 status = "disabled";
1546 dcan2: can@481d0000 {
1547 compatible = "ti,dra7-d_can";
1548 ti,hwmods = "dcan2";
1549 reg = <0x48480000 0x2000>;
1550 syscon-raminit = <&scm_conf 0x558 1>;
1551 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1552 clocks = <&sys_clkin1>;
1553 status = "disabled";
1557 compatible = "ti,dra7-dss";
1558 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1559 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1560 status = "disabled";
1561 ti,hwmods = "dss_core";
1562 /* CTRL_CORE_DSS_PLL_CONTROL */
1563 syscon-pll-ctrl = <&scm_conf 0x538>;
1564 #address-cells = <1>;
1569 compatible = "ti,dra7-dispc";
1570 reg = <0x58001000 0x1000>;
1571 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1572 ti,hwmods = "dss_dispc";
1573 clocks = <&dss_dss_clk>;
1574 clock-names = "fck";
1575 /* CTRL_CORE_SMA_SW_1 */
1576 syscon-pol = <&scm_conf 0x534>;
1579 hdmi: encoder@58060000 {
1580 compatible = "ti,dra7-hdmi";
1581 reg = <0x58040000 0x200>,
1584 <0x58060000 0x19000>;
1585 reg-names = "wp", "pll", "phy", "core";
1586 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1587 status = "disabled";
1588 ti,hwmods = "dss_hdmi";
1589 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1590 clock-names = "fck", "sys_clk";
1595 thermal_zones: thermal-zones {
1596 #include "omap4-cpu-thermal.dtsi"
1597 #include "omap5-gpu-thermal.dtsi"
1598 #include "omap5-core-thermal.dtsi"
1604 polling-delay = <500>; /* milliseconds */
1607 /include/ "dra7xx-clocks.dtsi"