arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16
  17 / {
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         compatible = "ti,dra7xx";
  22         interrupt-parent = <&crossbar_mpu>;
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_emac0;
  41                 ethernet1 = &cpsw_emac1;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44                 spi0 = &qspi;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv7-timer";
  49                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  53                 interrupt-parent = <&gic>;
  54         };
  55
  56         gic: interrupt-controller@48211000 {
  57                 compatible = "arm,cortex-a15-gic";
  58                 interrupt-controller;
  59                 #interrupt-cells = <3>;
  60                 reg = <0x0 0x48211000 0x0 0x1000>,
  61                       <0x0 0x48212000 0x0 0x1000>,
  62                       <0x0 0x48214000 0x0 0x2000>,
  63                       <0x0 0x48216000 0x0 0x2000>;
  64                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  65                 interrupt-parent = <&gic>;
  66         };
  67
  68         wakeupgen: interrupt-controller@48281000 {
  69                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  70                 interrupt-controller;
  71                 #interrupt-cells = <3>;
  72                 reg = <0x0 0x48281000 0x0 0x1000>;
  73                 interrupt-parent = <&gic>;
  74         };
  75
  76         /*
  77          * The soc node represents the soc top level view. It is used for IPs
  78          * that are not memory mapped in the MPU view or for the MPU itself.
  79          */
  80         soc {
  81                 compatible = "ti,omap-infra";
  82                 mpu {
  83                         compatible = "ti,omap5-mpu";
  84                         ti,hwmods = "mpu";
  85                 };
  86         };
  87
  88         /*
  89          * XXX: Use a flat representation of the SOC interconnect.
  90          * The real OMAP interconnect network is quite complex.
  91          * Since it will not bring real advantage to represent that in DT for
  92          * the moment, just use a fake OCP bus entry to represent the whole bus
  93          * hierarchy.
  94          */
  95         ocp {
  96                 compatible = "ti,dra7-l3-noc", "simple-bus";
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges = <0x0 0x0 0x0 0xc0000000>;
 100                 ti,hwmods = "l3_main_1", "l3_main_2";
 101                 reg = <0x0 0x44000000 0x0 0x1000000>,
 102                       <0x0 0x45000000 0x0 0x1000>;
 103                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 104                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 105
 106                 l4_cfg: l4@4a000000 {
 107                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 108                         #address-cells = <1>;
 109                         #size-cells = <1>;
 110                         ranges = <0 0x4a000000 0x22c000>;
 111
 112                         scm: scm@2000 {
 113                                 compatible = "ti,dra7-scm-core", "simple-bus";
 114                                 reg = <0x2000 0x2000>;
 115                                 #address-cells = <1>;
 116                                 #size-cells = <1>;
 117                                 ranges = <0 0x2000 0x2000>;
 118
 119                                 scm_conf: scm_conf@0 {
 120                                         compatible = "syscon", "simple-bus";
 121                                         reg = <0x0 0x1400>;
 122                                         #address-cells = <1>;
 123                                         #size-cells = <1>;
 124                                         ranges = <0 0x0 0x1400>;
 125
 126                                         pbias_regulator: pbias_regulator@e00 {
 127                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 128                                                 reg = <0xe00 0x4>;
 129                                                 syscon = <&scm_conf>;
 130                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 131                                                         regulator-name = "pbias_mmc_omap5";
 132                                                         regulator-min-microvolt = <1800000>;
 133                                                         regulator-max-microvolt = <3000000>;
 134                                                 };
 135                                         };
 136
 137                                         scm_conf_clocks: clocks {
 138                                                 #address-cells = <1>;
 139                                                 #size-cells = <0>;
 140                                         };
 141                                 };
 142
 143                                 dra7_pmx_core: pinmux@1400 {
 144                                         compatible = "ti,dra7-padconf",
 145                                                      "pinctrl-single";
 146                                         reg = <0x1400 0x0468>;
 147                                         #address-cells = <1>;
 148                                         #size-cells = <0>;
 149                                         #interrupt-cells = <1>;
 150                                         interrupt-controller;
 151                                         pinctrl-single,register-width = <32>;
 152                                         pinctrl-single,function-mask = <0x3fffffff>;
 153                                 };
 154
 155                                 scm_conf1: scm_conf@1c04 {
 156                                         compatible = "syscon";
 157                                         reg = <0x1c04 0x0020>;
 158                                 };
 159
 160                                 scm_conf_pcie: scm_conf@1c24 {
 161                                         compatible = "syscon";
 162                                         reg = <0x1c24 0x0024>;
 163                                 };
 164
 165                                 sdma_xbar: dma-router@b78 {
 166                                         compatible = "ti,dra7-dma-crossbar";
 167                                         reg = <0xb78 0xfc>;
 168                                         #dma-cells = <1>;
 169                                         dma-requests = <205>;
 170                                         ti,dma-safe-map = <0>;
 171                                         dma-masters = <&sdma>;
 172                                 };
 173
 174                                 edma_xbar: dma-router@c78 {
 175                                         compatible = "ti,dra7-dma-crossbar";
 176                                         reg = <0xc78 0x7c>;
 177                                         #dma-cells = <2>;
 178                                         dma-requests = <204>;
 179                                         ti,dma-safe-map = <0>;
 180                                         dma-masters = <&edma>;
 181                                 };
 182                         };
 183
 184                         cm_core_aon: cm_core_aon@5000 {
 185                                 compatible = "ti,dra7-cm-core-aon";
 186                                 reg = <0x5000 0x2000>;
 187
 188                                 cm_core_aon_clocks: clocks {
 189                                         #address-cells = <1>;
 190                                         #size-cells = <0>;
 191                                 };
 192
 193                                 cm_core_aon_clockdomains: clockdomains {
 194                                 };
 195                         };
 196
 197                         cm_core: cm_core@8000 {
 198                                 compatible = "ti,dra7-cm-core";
 199                                 reg = <0x8000 0x3000>;
 200
 201                                 cm_core_clocks: clocks {
 202                                         #address-cells = <1>;
 203                                         #size-cells = <0>;
 204                                 };
 205
 206                                 cm_core_clockdomains: clockdomains {
 207                                 };
 208                         };
 209                 };
 210
 211                 l4_wkup: l4@4ae00000 {
 212                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 213                         #address-cells = <1>;
 214                         #size-cells = <1>;
 215                         ranges = <0 0x4ae00000 0x3f000>;
 216
 217                         counter32k: counter@4000 {
 218                                 compatible = "ti,omap-counter32k";
 219                                 reg = <0x4000 0x40>;
 220                                 ti,hwmods = "counter_32k";
 221                         };
 222
 223                         prm: prm@6000 {
 224                                 compatible = "ti,dra7-prm";
 225                                 reg = <0x6000 0x3000>;
 226                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 227
 228                                 prm_clocks: clocks {
 229                                         #address-cells = <1>;
 230                                         #size-cells = <0>;
 231                                 };
 232
 233                                 prm_clockdomains: clockdomains {
 234                                 };
 235                         };
 236                 };
 237
 238                 axi@0 {
 239                         compatible = "simple-bus";
 240                         #size-cells = <1>;
 241                         #address-cells = <1>;
 242                         ranges = <0x51000000 0x51000000 0x3000
 243                                   0x0        0x20000000 0x10000000>;
 244                         pcie1: pcie@51000000 {
 245                                 compatible = "ti,dra7-pcie";
 246                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 247                                 reg-names = "rc_dbics", "ti_conf", "config";
 248                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 249                                 #address-cells = <3>;
 250                                 #size-cells = <2>;
 251                                 device_type = "pci";
 252                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 253                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 254                                 #interrupt-cells = <1>;
 255                                 num-lanes = <1>;
 256                                 ti,hwmods = "pcie1";
 257                                 phys = <&pcie1_phy>;
 258                                 phy-names = "pcie-phy0";
 259                                 interrupt-map-mask = <0 0 0 7>;
 260                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 261                                                 <0 0 0 2 &pcie1_intc 2>,
 262                                                 <0 0 0 3 &pcie1_intc 3>,
 263                                                 <0 0 0 4 &pcie1_intc 4>;
 264                                 pcie1_intc: interrupt-controller {
 265                                         interrupt-controller;
 266                                         #address-cells = <0>;
 267                                         #interrupt-cells = <1>;
 268                                 };
 269                         };
 270                 };
 271
 272                 axi@1 {
 273                         compatible = "simple-bus";
 274                         #size-cells = <1>;
 275                         #address-cells = <1>;
 276                         ranges = <0x51800000 0x51800000 0x3000
 277                                   0x0        0x30000000 0x10000000>;
 278                         status = "disabled";
 279                         pcie@51000000 {
 280                                 compatible = "ti,dra7-pcie";
 281                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 282                                 reg-names = "rc_dbics", "ti_conf", "config";
 283                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 284                                 #address-cells = <3>;
 285                                 #size-cells = <2>;
 286                                 device_type = "pci";
 287                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 288                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 289                                 #interrupt-cells = <1>;
 290                                 num-lanes = <1>;
 291                                 ti,hwmods = "pcie2";
 292                                 phys = <&pcie2_phy>;
 293                                 phy-names = "pcie-phy0";
 294                                 interrupt-map-mask = <0 0 0 7>;
 295                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 296                                                 <0 0 0 2 &pcie2_intc 2>,
 297                                                 <0 0 0 3 &pcie2_intc 3>,
 298                                                 <0 0 0 4 &pcie2_intc 4>;
 299                                 pcie2_intc: interrupt-controller {
 300                                         interrupt-controller;
 301                                         #address-cells = <0>;
 302                                         #interrupt-cells = <1>;
 303                                 };
 304                         };
 305                 };
 306
 307                 ocmcram1: ocmcram@40300000 {
 308                         compatible = "mmio-sram";
 309                         reg = <0x40300000 0x80000>;
 310                         ranges = <0x0 0x40300000 0x80000>;
 311                         #address-cells = <1>;
 312                         #size-cells = <1>;
 313                         /*
 314                          * This is a placeholder for an optional reserved
 315                          * region for use by secure software. The size
 316                          * of this region is not known until runtime so it
 317                          * is set as zero to either be updated to reserve
 318                          * space or left unchanged to leave all SRAM for use.
 319                          * On HS parts that that require the reserved region
 320                          * either the bootloader can update the size to
 321                          * the required amount or the node can be overridden
 322                          * from the board dts file for the secure platform.
 323                          */
 324                         sram-hs@0 {
 325                                 compatible = "ti,secure-ram";
 326                                 reg = <0x0 0x0>;
 327                         };
 328                 };
 329
 330                 /*
 331                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 332                  * DRA7xx and AM57xx variants. Confirm availability in
 333                  * the data manual for the exact part number in use
 334                  * before enabling these nodes in the board dts file.
 335                  */
 336                 ocmcram2: ocmcram@40400000 {
 337                         status = "disabled";
 338                         compatible = "mmio-sram";
 339                         reg = <0x40400000 0x100000>;
 340                         ranges = <0x0 0x40400000 0x100000>;
 341                         #address-cells = <1>;
 342                         #size-cells = <1>;
 343                 };
 344
 345                 ocmcram3: ocmcram@40500000 {
 346                         status = "disabled";
 347                         compatible = "mmio-sram";
 348                         reg = <0x40500000 0x100000>;
 349                         ranges = <0x0 0x40500000 0x100000>;
 350                         #address-cells = <1>;
 351                         #size-cells = <1>;
 352                 };
 353
 354                 bandgap: bandgap@4a0021e0 {
 355                         reg = <0x4a0021e0 0xc
 356                                 0x4a00232c 0xc
 357                                 0x4a002380 0x2c
 358                                 0x4a0023C0 0x3c
 359                                 0x4a002564 0x8
 360                                 0x4a002574 0x50>;
 361                                 compatible = "ti,dra752-bandgap";
 362                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 363                                 #thermal-sensor-cells = <1>;
 364                 };
 365
 366                 dsp1_system: dsp_system@40d00000 {
 367                         compatible = "syscon";
 368                         reg = <0x40d00000 0x100>;
 369                 };
 370
 371                 sdma: dma-controller@4a056000 {
 372                         compatible = "ti,omap4430-sdma";
 373                         reg = <0x4a056000 0x1000>;
 374                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 375                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 376                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 377                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 378                         #dma-cells = <1>;
 379                         dma-channels = <32>;
 380                         dma-requests = <127>;
 381                 };
 382
 383                 edma: edma@43300000 {
 384                         compatible = "ti,edma3-tpcc";
 385                         ti,hwmods = "tpcc";
 386                         reg = <0x43300000 0x100000>;
 387                         reg-names = "edma3_cc";
 388                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 391                         interrupt-names = "edma3_ccint", "emda3_mperr",
 392                                           "edma3_ccerrint";
 393                         dma-requests = <64>;
 394                         #dma-cells = <2>;
 395
 396                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 397
 398                         /*
 399                          * memcpy is disabled, can be enabled with:
 400                          * ti,edma-memcpy-channels = <20 21>;
 401                          * for example. Note that these channels need to be
 402                          * masked in the xbar as well.
 403                          */
 404                 };
 405
 406                 edma_tptc0: tptc@43400000 {
 407                         compatible = "ti,edma3-tptc";
 408                         ti,hwmods = "tptc0";
 409                         reg =   <0x43400000 0x100000>;
 410                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 411                         interrupt-names = "edma3_tcerrint";
 412                 };
 413
 414                 edma_tptc1: tptc@43500000 {
 415                         compatible = "ti,edma3-tptc";
 416                         ti,hwmods = "tptc1";
 417                         reg =   <0x43500000 0x100000>;
 418                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 419                         interrupt-names = "edma3_tcerrint";
 420                 };
 421
 422                 gpio1: gpio@4ae10000 {
 423                         compatible = "ti,omap4-gpio";
 424                         reg = <0x4ae10000 0x200>;
 425                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 426                         ti,hwmods = "gpio1";
 427                         gpio-controller;
 428                         #gpio-cells = <2>;
 429                         interrupt-controller;
 430                         #interrupt-cells = <2>;
 431                 };
 432
 433                 gpio2: gpio@48055000 {
 434                         compatible = "ti,omap4-gpio";
 435                         reg = <0x48055000 0x200>;
 436                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 437                         ti,hwmods = "gpio2";
 438                         gpio-controller;
 439                         #gpio-cells = <2>;
 440                         interrupt-controller;
 441                         #interrupt-cells = <2>;
 442                 };
 443
 444                 gpio3: gpio@48057000 {
 445                         compatible = "ti,omap4-gpio";
 446                         reg = <0x48057000 0x200>;
 447                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 448                         ti,hwmods = "gpio3";
 449                         gpio-controller;
 450                         #gpio-cells = <2>;
 451                         interrupt-controller;
 452                         #interrupt-cells = <2>;
 453                 };
 454
 455                 gpio4: gpio@48059000 {
 456                         compatible = "ti,omap4-gpio";
 457                         reg = <0x48059000 0x200>;
 458                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 459                         ti,hwmods = "gpio4";
 460                         gpio-controller;
 461                         #gpio-cells = <2>;
 462                         interrupt-controller;
 463                         #interrupt-cells = <2>;
 464                 };
 465
 466                 gpio5: gpio@4805b000 {
 467                         compatible = "ti,omap4-gpio";
 468                         reg = <0x4805b000 0x200>;
 469                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "gpio5";
 471                         gpio-controller;
 472                         #gpio-cells = <2>;
 473                         interrupt-controller;
 474                         #interrupt-cells = <2>;
 475                 };
 476
 477                 gpio6: gpio@4805d000 {
 478                         compatible = "ti,omap4-gpio";
 479                         reg = <0x4805d000 0x200>;
 480                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 481                         ti,hwmods = "gpio6";
 482                         gpio-controller;
 483                         #gpio-cells = <2>;
 484                         interrupt-controller;
 485                         #interrupt-cells = <2>;
 486                 };
 487
 488                 gpio7: gpio@48051000 {
 489                         compatible = "ti,omap4-gpio";
 490                         reg = <0x48051000 0x200>;
 491                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 492                         ti,hwmods = "gpio7";
 493                         gpio-controller;
 494                         #gpio-cells = <2>;
 495                         interrupt-controller;
 496                         #interrupt-cells = <2>;
 497                 };
 498
 499                 gpio8: gpio@48053000 {
 500                         compatible = "ti,omap4-gpio";
 501                         reg = <0x48053000 0x200>;
 502                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 503                         ti,hwmods = "gpio8";
 504                         gpio-controller;
 505                         #gpio-cells = <2>;
 506                         interrupt-controller;
 507                         #interrupt-cells = <2>;
 508                 };
 509
 510                 uart1: serial@4806a000 {
 511                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 512                         reg = <0x4806a000 0x100>;
 513                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 514                         ti,hwmods = "uart1";
 515                         clock-frequency = <48000000>;
 516                         status = "disabled";
 517                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 518                         dma-names = "tx", "rx";
 519                 };
 520
 521                 uart2: serial@4806c000 {
 522                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 523                         reg = <0x4806c000 0x100>;
 524                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 525                         ti,hwmods = "uart2";
 526                         clock-frequency = <48000000>;
 527                         status = "disabled";
 528                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 529                         dma-names = "tx", "rx";
 530                 };
 531
 532                 uart3: serial@48020000 {
 533                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 534                         reg = <0x48020000 0x100>;
 535                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "uart3";
 537                         clock-frequency = <48000000>;
 538                         status = "disabled";
 539                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 540                         dma-names = "tx", "rx";
 541                 };
 542
 543                 uart4: serial@4806e000 {
 544                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 545                         reg = <0x4806e000 0x100>;
 546                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 547                         ti,hwmods = "uart4";
 548                         clock-frequency = <48000000>;
 549                         status = "disabled";
 550                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 551                         dma-names = "tx", "rx";
 552                 };
 553
 554                 uart5: serial@48066000 {
 555                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 556                         reg = <0x48066000 0x100>;
 557                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 558                         ti,hwmods = "uart5";
 559                         clock-frequency = <48000000>;
 560                         status = "disabled";
 561                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 562                         dma-names = "tx", "rx";
 563                 };
 564
 565                 uart6: serial@48068000 {
 566                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 567                         reg = <0x48068000 0x100>;
 568                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "uart6";
 570                         clock-frequency = <48000000>;
 571                         status = "disabled";
 572                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 573                         dma-names = "tx", "rx";
 574                 };
 575
 576                 uart7: serial@48420000 {
 577                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 578                         reg = <0x48420000 0x100>;
 579                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 580                         ti,hwmods = "uart7";
 581                         clock-frequency = <48000000>;
 582                         status = "disabled";
 583                 };
 584
 585                 uart8: serial@48422000 {
 586                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 587                         reg = <0x48422000 0x100>;
 588                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 589                         ti,hwmods = "uart8";
 590                         clock-frequency = <48000000>;
 591                         status = "disabled";
 592                 };
 593
 594                 uart9: serial@48424000 {
 595                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 596                         reg = <0x48424000 0x100>;
 597                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 598                         ti,hwmods = "uart9";
 599                         clock-frequency = <48000000>;
 600                         status = "disabled";
 601                 };
 602
 603                 uart10: serial@4ae2b000 {
 604                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 605                         reg = <0x4ae2b000 0x100>;
 606                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 607                         ti,hwmods = "uart10";
 608                         clock-frequency = <48000000>;
 609                         status = "disabled";
 610                 };
 611
 612                 mailbox1: mailbox@4a0f4000 {
 613                         compatible = "ti,omap4-mailbox";
 614                         reg = <0x4a0f4000 0x200>;
 615                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 618                         ti,hwmods = "mailbox1";
 619                         #mbox-cells = <1>;
 620                         ti,mbox-num-users = <3>;
 621                         ti,mbox-num-fifos = <8>;
 622                         status = "disabled";
 623                 };
 624
 625                 mailbox2: mailbox@4883a000 {
 626                         compatible = "ti,omap4-mailbox";
 627                         reg = <0x4883a000 0x200>;
 628                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "mailbox2";
 633                         #mbox-cells = <1>;
 634                         ti,mbox-num-users = <4>;
 635                         ti,mbox-num-fifos = <12>;
 636                         status = "disabled";
 637                 };
 638
 639                 mailbox3: mailbox@4883c000 {
 640                         compatible = "ti,omap4-mailbox";
 641                         reg = <0x4883c000 0x200>;
 642                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 643                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 644                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 646                         ti,hwmods = "mailbox3";
 647                         #mbox-cells = <1>;
 648                         ti,mbox-num-users = <4>;
 649                         ti,mbox-num-fifos = <12>;
 650                         status = "disabled";
 651                 };
 652
 653                 mailbox4: mailbox@4883e000 {
 654                         compatible = "ti,omap4-mailbox";
 655                         reg = <0x4883e000 0x200>;
 656                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 657                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 658                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 660                         ti,hwmods = "mailbox4";
 661                         #mbox-cells = <1>;
 662                         ti,mbox-num-users = <4>;
 663                         ti,mbox-num-fifos = <12>;
 664                         status = "disabled";
 665                 };
 666
 667                 mailbox5: mailbox@48840000 {
 668                         compatible = "ti,omap4-mailbox";
 669                         reg = <0x48840000 0x200>;
 670                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 674                         ti,hwmods = "mailbox5";
 675                         #mbox-cells = <1>;
 676                         ti,mbox-num-users = <4>;
 677                         ti,mbox-num-fifos = <12>;
 678                         status = "disabled";
 679                 };
 680
 681                 mailbox6: mailbox@48842000 {
 682                         compatible = "ti,omap4-mailbox";
 683                         reg = <0x48842000 0x200>;
 684                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 688                         ti,hwmods = "mailbox6";
 689                         #mbox-cells = <1>;
 690                         ti,mbox-num-users = <4>;
 691                         ti,mbox-num-fifos = <12>;
 692                         status = "disabled";
 693                 };
 694
 695                 mailbox7: mailbox@48844000 {
 696                         compatible = "ti,omap4-mailbox";
 697                         reg = <0x48844000 0x200>;
 698                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 702                         ti,hwmods = "mailbox7";
 703                         #mbox-cells = <1>;
 704                         ti,mbox-num-users = <4>;
 705                         ti,mbox-num-fifos = <12>;
 706                         status = "disabled";
 707                 };
 708
 709                 mailbox8: mailbox@48846000 {
 710                         compatible = "ti,omap4-mailbox";
 711                         reg = <0x48846000 0x200>;
 712                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 716                         ti,hwmods = "mailbox8";
 717                         #mbox-cells = <1>;
 718                         ti,mbox-num-users = <4>;
 719                         ti,mbox-num-fifos = <12>;
 720                         status = "disabled";
 721                 };
 722
 723                 mailbox9: mailbox@4885e000 {
 724                         compatible = "ti,omap4-mailbox";
 725                         reg = <0x4885e000 0x200>;
 726                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 730                         ti,hwmods = "mailbox9";
 731                         #mbox-cells = <1>;
 732                         ti,mbox-num-users = <4>;
 733                         ti,mbox-num-fifos = <12>;
 734                         status = "disabled";
 735                 };
 736
 737                 mailbox10: mailbox@48860000 {
 738                         compatible = "ti,omap4-mailbox";
 739                         reg = <0x48860000 0x200>;
 740                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 744                         ti,hwmods = "mailbox10";
 745                         #mbox-cells = <1>;
 746                         ti,mbox-num-users = <4>;
 747                         ti,mbox-num-fifos = <12>;
 748                         status = "disabled";
 749                 };
 750
 751                 mailbox11: mailbox@48862000 {
 752                         compatible = "ti,omap4-mailbox";
 753                         reg = <0x48862000 0x200>;
 754                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 758                         ti,hwmods = "mailbox11";
 759                         #mbox-cells = <1>;
 760                         ti,mbox-num-users = <4>;
 761                         ti,mbox-num-fifos = <12>;
 762                         status = "disabled";
 763                 };
 764
 765                 mailbox12: mailbox@48864000 {
 766                         compatible = "ti,omap4-mailbox";
 767                         reg = <0x48864000 0x200>;
 768                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 769                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 770                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 771                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 772                         ti,hwmods = "mailbox12";
 773                         #mbox-cells = <1>;
 774                         ti,mbox-num-users = <4>;
 775                         ti,mbox-num-fifos = <12>;
 776                         status = "disabled";
 777                 };
 778
 779                 mailbox13: mailbox@48802000 {
 780                         compatible = "ti,omap4-mailbox";
 781                         reg = <0x48802000 0x200>;
 782                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 783                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 784                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 786                         ti,hwmods = "mailbox13";
 787                         #mbox-cells = <1>;
 788                         ti,mbox-num-users = <4>;
 789                         ti,mbox-num-fifos = <12>;
 790                         status = "disabled";
 791                 };
 792
 793                 timer1: timer@4ae18000 {
 794                         compatible = "ti,omap5430-timer";
 795                         reg = <0x4ae18000 0x80>;
 796                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 797                         ti,hwmods = "timer1";
 798                         ti,timer-alwon;
 799                 };
 800
 801                 timer2: timer@48032000 {
 802                         compatible = "ti,omap5430-timer";
 803                         reg = <0x48032000 0x80>;
 804                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 805                         ti,hwmods = "timer2";
 806                 };
 807
 808                 timer3: timer@48034000 {
 809                         compatible = "ti,omap5430-timer";
 810                         reg = <0x48034000 0x80>;
 811                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 812                         ti,hwmods = "timer3";
 813                 };
 814
 815                 timer4: timer@48036000 {
 816                         compatible = "ti,omap5430-timer";
 817                         reg = <0x48036000 0x80>;
 818                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 819                         ti,hwmods = "timer4";
 820                 };
 821
 822                 timer5: timer@48820000 {
 823                         compatible = "ti,omap5430-timer";
 824                         reg = <0x48820000 0x80>;
 825                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 826                         ti,hwmods = "timer5";
 827                 };
 828
 829                 timer6: timer@48822000 {
 830                         compatible = "ti,omap5430-timer";
 831                         reg = <0x48822000 0x80>;
 832                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 833                         ti,hwmods = "timer6";
 834                 };
 835
 836                 timer7: timer@48824000 {
 837                         compatible = "ti,omap5430-timer";
 838                         reg = <0x48824000 0x80>;
 839                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 840                         ti,hwmods = "timer7";
 841                 };
 842
 843                 timer8: timer@48826000 {
 844                         compatible = "ti,omap5430-timer";
 845                         reg = <0x48826000 0x80>;
 846                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 847                         ti,hwmods = "timer8";
 848                 };
 849
 850                 timer9: timer@4803e000 {
 851                         compatible = "ti,omap5430-timer";
 852                         reg = <0x4803e000 0x80>;
 853                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 854                         ti,hwmods = "timer9";
 855                 };
 856
 857                 timer10: timer@48086000 {
 858                         compatible = "ti,omap5430-timer";
 859                         reg = <0x48086000 0x80>;
 860                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 861                         ti,hwmods = "timer10";
 862                 };
 863
 864                 timer11: timer@48088000 {
 865                         compatible = "ti,omap5430-timer";
 866                         reg = <0x48088000 0x80>;
 867                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 868                         ti,hwmods = "timer11";
 869                 };
 870
 871                 timer12: timer@4ae20000 {
 872                         compatible = "ti,omap5430-timer";
 873                         reg = <0x4ae20000 0x80>;
 874                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 875                         ti,hwmods = "timer12";
 876                         ti,timer-alwon;
 877                         ti,timer-secure;
 878                 };
 879
 880                 timer13: timer@48828000 {
 881                         compatible = "ti,omap5430-timer";
 882                         reg = <0x48828000 0x80>;
 883                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 884                         ti,hwmods = "timer13";
 885                 };
 886
 887                 timer14: timer@4882a000 {
 888                         compatible = "ti,omap5430-timer";
 889                         reg = <0x4882a000 0x80>;
 890                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 891                         ti,hwmods = "timer14";
 892                 };
 893
 894                 timer15: timer@4882c000 {
 895                         compatible = "ti,omap5430-timer";
 896                         reg = <0x4882c000 0x80>;
 897                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 898                         ti,hwmods = "timer15";
 899                 };
 900
 901                 timer16: timer@4882e000 {
 902                         compatible = "ti,omap5430-timer";
 903                         reg = <0x4882e000 0x80>;
 904                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 905                         ti,hwmods = "timer16";
 906                 };
 907
 908                 wdt2: wdt@4ae14000 {
 909                         compatible = "ti,omap3-wdt";
 910                         reg = <0x4ae14000 0x80>;
 911                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 912                         ti,hwmods = "wd_timer2";
 913                 };
 914
 915                 hwspinlock: spinlock@4a0f6000 {
 916                         compatible = "ti,omap4-hwspinlock";
 917                         reg = <0x4a0f6000 0x1000>;
 918                         ti,hwmods = "spinlock";
 919                         #hwlock-cells = <1>;
 920                 };
 921
 922                 dmm@4e000000 {
 923                         compatible = "ti,omap5-dmm";
 924                         reg = <0x4e000000 0x800>;
 925                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 926                         ti,hwmods = "dmm";
 927                 };
 928
 929                 i2c1: i2c@48070000 {
 930                         compatible = "ti,omap4-i2c";
 931                         reg = <0x48070000 0x100>;
 932                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 933                         #address-cells = <1>;
 934                         #size-cells = <0>;
 935                         ti,hwmods = "i2c1";
 936                         status = "disabled";
 937                 };
 938
 939                 i2c2: i2c@48072000 {
 940                         compatible = "ti,omap4-i2c";
 941                         reg = <0x48072000 0x100>;
 942                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 943                         #address-cells = <1>;
 944                         #size-cells = <0>;
 945                         ti,hwmods = "i2c2";
 946                         status = "disabled";
 947                 };
 948
 949                 i2c3: i2c@48060000 {
 950                         compatible = "ti,omap4-i2c";
 951                         reg = <0x48060000 0x100>;
 952                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 953                         #address-cells = <1>;
 954                         #size-cells = <0>;
 955                         ti,hwmods = "i2c3";
 956                         status = "disabled";
 957                 };
 958
 959                 i2c4: i2c@4807a000 {
 960                         compatible = "ti,omap4-i2c";
 961                         reg = <0x4807a000 0x100>;
 962                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 963                         #address-cells = <1>;
 964                         #size-cells = <0>;
 965                         ti,hwmods = "i2c4";
 966                         status = "disabled";
 967                 };
 968
 969                 i2c5: i2c@4807c000 {
 970                         compatible = "ti,omap4-i2c";
 971                         reg = <0x4807c000 0x100>;
 972                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 973                         #address-cells = <1>;
 974                         #size-cells = <0>;
 975                         ti,hwmods = "i2c5";
 976                         status = "disabled";
 977                 };
 978
 979                 mmc1: mmc@4809c000 {
 980                         compatible = "ti,omap4-hsmmc";
 981                         reg = <0x4809c000 0x400>;
 982                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 983                         ti,hwmods = "mmc1";
 984                         ti,dual-volt;
 985                         ti,needs-special-reset;
 986                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
 987                         dma-names = "tx", "rx";
 988                         status = "disabled";
 989                         pbias-supply = <&pbias_mmc_reg>;
 990                 };
 991
 992                 mmc2: mmc@480b4000 {
 993                         compatible = "ti,omap4-hsmmc";
 994                         reg = <0x480b4000 0x400>;
 995                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 996                         ti,hwmods = "mmc2";
 997                         ti,needs-special-reset;
 998                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
 999                         dma-names = "tx", "rx";
1000                         status = "disabled";
1001                 };
1002
1003                 mmc3: mmc@480ad000 {
1004                         compatible = "ti,omap4-hsmmc";
1005                         reg = <0x480ad000 0x400>;
1006                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1007                         ti,hwmods = "mmc3";
1008                         ti,needs-special-reset;
1009                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1010                         dma-names = "tx", "rx";
1011                         status = "disabled";
1012                 };
1013
1014                 mmc4: mmc@480d1000 {
1015                         compatible = "ti,omap4-hsmmc";
1016                         reg = <0x480d1000 0x400>;
1017                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1018                         ti,hwmods = "mmc4";
1019                         ti,needs-special-reset;
1020                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1021                         dma-names = "tx", "rx";
1022                         status = "disabled";
1023                 };
1024
1025                 mmu0_dsp1: mmu@40d01000 {
1026                         compatible = "ti,dra7-dsp-iommu";
1027                         reg = <0x40d01000 0x100>;
1028                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1029                         ti,hwmods = "mmu0_dsp1";
1030                         #iommu-cells = <0>;
1031                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1032                         status = "disabled";
1033                 };
1034
1035                 mmu1_dsp1: mmu@40d02000 {
1036                         compatible = "ti,dra7-dsp-iommu";
1037                         reg = <0x40d02000 0x100>;
1038                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1039                         ti,hwmods = "mmu1_dsp1";
1040                         #iommu-cells = <0>;
1041                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1042                         status = "disabled";
1043                 };
1044
1045                 mmu_ipu1: mmu@58882000 {
1046                         compatible = "ti,dra7-iommu";
1047                         reg = <0x58882000 0x100>;
1048                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1049                         ti,hwmods = "mmu_ipu1";
1050                         #iommu-cells = <0>;
1051                         ti,iommu-bus-err-back;
1052                         status = "disabled";
1053                 };
1054
1055                 mmu_ipu2: mmu@55082000 {
1056                         compatible = "ti,dra7-iommu";
1057                         reg = <0x55082000 0x100>;
1058                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1059                         ti,hwmods = "mmu_ipu2";
1060                         #iommu-cells = <0>;
1061                         ti,iommu-bus-err-back;
1062                         status = "disabled";
1063                 };
1064
1065                 abb_mpu: regulator-abb-mpu {
1066                         compatible = "ti,abb-v3";
1067                         regulator-name = "abb_mpu";
1068                         #address-cells = <0>;
1069                         #size-cells = <0>;
1070                         clocks = <&sys_clkin1>;
1071                         ti,settling-time = <50>;
1072                         ti,clock-cycles = <16>;
1073
1074                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1075                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1076                               <0x4ae0c158 0x4>;
1077                         reg-names = "setup-address", "control-address",
1078                                     "int-address", "efuse-address",
1079                                     "ldo-address";
1080                         ti,tranxdone-status-mask = <0x80>;
1081                         /* LDOVBBMPU_FBB_MUX_CTRL */
1082                         ti,ldovbb-override-mask = <0x400>;
1083                         /* LDOVBBMPU_FBB_VSET_OUT */
1084                         ti,ldovbb-vset-mask = <0x1F>;
1085
1086                         /*
1087                          * NOTE: only FBB mode used but actual vset will
1088                          * determine final biasing
1089                          */
1090                         ti,abb_info = <
1091                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1092                         1060000         0       0x0     0 0x02000000 0x01F00000
1093                         1160000         0       0x4     0 0x02000000 0x01F00000
1094                         1210000         0       0x8     0 0x02000000 0x01F00000
1095                         >;
1096                 };
1097
1098                 abb_ivahd: regulator-abb-ivahd {
1099                         compatible = "ti,abb-v3";
1100                         regulator-name = "abb_ivahd";
1101                         #address-cells = <0>;
1102                         #size-cells = <0>;
1103                         clocks = <&sys_clkin1>;
1104                         ti,settling-time = <50>;
1105                         ti,clock-cycles = <16>;
1106
1107                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1108                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1109                               <0x4a002470 0x4>;
1110                         reg-names = "setup-address", "control-address",
1111                                     "int-address", "efuse-address",
1112                                     "ldo-address";
1113                         ti,tranxdone-status-mask = <0x40000000>;
1114                         /* LDOVBBIVA_FBB_MUX_CTRL */
1115                         ti,ldovbb-override-mask = <0x400>;
1116                         /* LDOVBBIVA_FBB_VSET_OUT */
1117                         ti,ldovbb-vset-mask = <0x1F>;
1118
1119                         /*
1120                          * NOTE: only FBB mode used but actual vset will
1121                          * determine final biasing
1122                          */
1123                         ti,abb_info = <
1124                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1125                         1055000         0       0x0     0 0x02000000 0x01F00000
1126                         1150000         0       0x4     0 0x02000000 0x01F00000
1127                         1250000         0       0x8     0 0x02000000 0x01F00000
1128                         >;
1129                 };
1130
1131                 abb_dspeve: regulator-abb-dspeve {
1132                         compatible = "ti,abb-v3";
1133                         regulator-name = "abb_dspeve";
1134                         #address-cells = <0>;
1135                         #size-cells = <0>;
1136                         clocks = <&sys_clkin1>;
1137                         ti,settling-time = <50>;
1138                         ti,clock-cycles = <16>;
1139
1140                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1141                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1142                               <0x4a00246c 0x4>;
1143                         reg-names = "setup-address", "control-address",
1144                                     "int-address", "efuse-address",
1145                                     "ldo-address";
1146                         ti,tranxdone-status-mask = <0x20000000>;
1147                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1148                         ti,ldovbb-override-mask = <0x400>;
1149                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1150                         ti,ldovbb-vset-mask = <0x1F>;
1151
1152                         /*
1153                          * NOTE: only FBB mode used but actual vset will
1154                          * determine final biasing
1155                          */
1156                         ti,abb_info = <
1157                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1158                         1055000         0       0x0     0 0x02000000 0x01F00000
1159                         1150000         0       0x4     0 0x02000000 0x01F00000
1160                         1250000         0       0x8     0 0x02000000 0x01F00000
1161                         >;
1162                 };
1163
1164                 abb_gpu: regulator-abb-gpu {
1165                         compatible = "ti,abb-v3";
1166                         regulator-name = "abb_gpu";
1167                         #address-cells = <0>;
1168                         #size-cells = <0>;
1169                         clocks = <&sys_clkin1>;
1170                         ti,settling-time = <50>;
1171                         ti,clock-cycles = <16>;
1172
1173                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1174                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1175                               <0x4ae0c154 0x4>;
1176                         reg-names = "setup-address", "control-address",
1177                                     "int-address", "efuse-address",
1178                                     "ldo-address";
1179                         ti,tranxdone-status-mask = <0x10000000>;
1180                         /* LDOVBBGPU_FBB_MUX_CTRL */
1181                         ti,ldovbb-override-mask = <0x400>;
1182                         /* LDOVBBGPU_FBB_VSET_OUT */
1183                         ti,ldovbb-vset-mask = <0x1F>;
1184
1185                         /*
1186                          * NOTE: only FBB mode used but actual vset will
1187                          * determine final biasing
1188                          */
1189                         ti,abb_info = <
1190                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1191                         1090000         0       0x0     0 0x02000000 0x01F00000
1192                         1210000         0       0x4     0 0x02000000 0x01F00000
1193                         1280000         0       0x8     0 0x02000000 0x01F00000
1194                         >;
1195                 };
1196
1197                 mcspi1: spi@48098000 {
1198                         compatible = "ti,omap4-mcspi";
1199                         reg = <0x48098000 0x200>;
1200                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203                         ti,hwmods = "mcspi1";
1204                         ti,spi-num-cs = <4>;
1205                         dmas = <&sdma_xbar 35>,
1206                                <&sdma_xbar 36>,
1207                                <&sdma_xbar 37>,
1208                                <&sdma_xbar 38>,
1209                                <&sdma_xbar 39>,
1210                                <&sdma_xbar 40>,
1211                                <&sdma_xbar 41>,
1212                                <&sdma_xbar 42>;
1213                         dma-names = "tx0", "rx0", "tx1", "rx1",
1214                                     "tx2", "rx2", "tx3", "rx3";
1215                         status = "disabled";
1216                 };
1217
1218                 mcspi2: spi@4809a000 {
1219                         compatible = "ti,omap4-mcspi";
1220                         reg = <0x4809a000 0x200>;
1221                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1222                         #address-cells = <1>;
1223                         #size-cells = <0>;
1224                         ti,hwmods = "mcspi2";
1225                         ti,spi-num-cs = <2>;
1226                         dmas = <&sdma_xbar 43>,
1227                                <&sdma_xbar 44>,
1228                                <&sdma_xbar 45>,
1229                                <&sdma_xbar 46>;
1230                         dma-names = "tx0", "rx0", "tx1", "rx1";
1231                         status = "disabled";
1232                 };
1233
1234                 mcspi3: spi@480b8000 {
1235                         compatible = "ti,omap4-mcspi";
1236                         reg = <0x480b8000 0x200>;
1237                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1238                         #address-cells = <1>;
1239                         #size-cells = <0>;
1240                         ti,hwmods = "mcspi3";
1241                         ti,spi-num-cs = <2>;
1242                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1243                         dma-names = "tx0", "rx0";
1244                         status = "disabled";
1245                 };
1246
1247                 mcspi4: spi@480ba000 {
1248                         compatible = "ti,omap4-mcspi";
1249                         reg = <0x480ba000 0x200>;
1250                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1251                         #address-cells = <1>;
1252                         #size-cells = <0>;
1253                         ti,hwmods = "mcspi4";
1254                         ti,spi-num-cs = <1>;
1255                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1256                         dma-names = "tx0", "rx0";
1257                         status = "disabled";
1258                 };
1259
1260                 qspi: qspi@4b300000 {
1261                         compatible = "ti,dra7xxx-qspi";
1262                         reg = <0x4b300000 0x100>,
1263                               <0x5c000000 0x4000000>;
1264                         reg-names = "qspi_base", "qspi_mmap";
1265                         syscon-chipselects = <&scm_conf 0x558>;
1266                         #address-cells = <1>;
1267                         #size-cells = <0>;
1268                         ti,hwmods = "qspi";
1269                         clocks = <&qspi_gfclk_div>;
1270                         clock-names = "fck";
1271                         num-cs = <4>;
1272                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1273                         status = "disabled";
1274                 };
1275
1276                 /* OCP2SCP3 */
1277                 ocp2scp@4a090000 {
1278                         compatible = "ti,omap-ocp2scp";
1279                         #address-cells = <1>;
1280                         #size-cells = <1>;
1281                         ranges;
1282                         reg = <0x4a090000 0x20>;
1283                         ti,hwmods = "ocp2scp3";
1284                         sata_phy: phy@4A096000 {
1285                                 compatible = "ti,phy-pipe3-sata";
1286                                 reg = <0x4A096000 0x80>, /* phy_rx */
1287                                       <0x4A096400 0x64>, /* phy_tx */
1288                                       <0x4A096800 0x40>; /* pll_ctrl */
1289                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1290                                 syscon-phy-power = <&scm_conf 0x374>;
1291                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1292                                 clock-names = "sysclk", "refclk";
1293                                 syscon-pllreset = <&scm_conf 0x3fc>;
1294                                 #phy-cells = <0>;
1295                         };
1296
1297                         pcie1_phy: pciephy@4a094000 {
1298                                 compatible = "ti,phy-pipe3-pcie";
1299                                 reg = <0x4a094000 0x80>, /* phy_rx */
1300                                       <0x4a094400 0x64>; /* phy_tx */
1301                                 reg-names = "phy_rx", "phy_tx";
1302                                 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1303                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1304                                 clocks = <&dpll_pcie_ref_ck>,
1305                                          <&dpll_pcie_ref_m2ldo_ck>,
1306                                          <&optfclk_pciephy1_32khz>,
1307                                          <&optfclk_pciephy1_clk>,
1308                                          <&optfclk_pciephy1_div_clk>,
1309                                          <&optfclk_pciephy_div>,
1310                                          <&sys_clkin1>;
1311                                 clock-names = "dpll_ref", "dpll_ref_m2",
1312                                               "wkupclk", "refclk",
1313                                               "div-clk", "phy-div", "sysclk";
1314                                 #phy-cells = <0>;
1315                         };
1316
1317                         pcie2_phy: pciephy@4a095000 {
1318                                 compatible = "ti,phy-pipe3-pcie";
1319                                 reg = <0x4a095000 0x80>, /* phy_rx */
1320                                       <0x4a095400 0x64>; /* phy_tx */
1321                                 reg-names = "phy_rx", "phy_tx";
1322                                 syscon-phy-power = <&scm_conf_pcie 0x20>;
1323                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1324                                 clocks = <&dpll_pcie_ref_ck>,
1325                                          <&dpll_pcie_ref_m2ldo_ck>,
1326                                          <&optfclk_pciephy2_32khz>,
1327                                          <&optfclk_pciephy2_clk>,
1328                                          <&optfclk_pciephy2_div_clk>,
1329                                          <&optfclk_pciephy_div>,
1330                                          <&sys_clkin1>;
1331                                 clock-names = "dpll_ref", "dpll_ref_m2",
1332                                               "wkupclk", "refclk",
1333                                               "div-clk", "phy-div", "sysclk";
1334                                 #phy-cells = <0>;
1335                                 status = "disabled";
1336                         };
1337                 };
1338
1339                 sata: sata@4a141100 {
1340                         compatible = "snps,dwc-ahci";
1341                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1342                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1343                         phys = <&sata_phy>;
1344                         phy-names = "sata-phy";
1345                         clocks = <&sata_ref_clk>;
1346                         ti,hwmods = "sata";
1347                 };
1348
1349                 rtc: rtc@48838000 {
1350                         compatible = "ti,am3352-rtc";
1351                         reg = <0x48838000 0x100>;
1352                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1353                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1354                         ti,hwmods = "rtcss";
1355                         clocks = <&sys_32k_ck>;
1356                 };
1357
1358                 /* OCP2SCP1 */
1359                 ocp2scp@4a080000 {
1360                         compatible = "ti,omap-ocp2scp";
1361                         #address-cells = <1>;
1362                         #size-cells = <1>;
1363                         ranges;
1364                         reg = <0x4a080000 0x20>;
1365                         ti,hwmods = "ocp2scp1";
1366
1367                         usb2_phy1: phy@4a084000 {
1368                                 compatible = "ti,omap-usb2";
1369                                 reg = <0x4a084000 0x400>;
1370                                 syscon-phy-power = <&scm_conf 0x300>;
1371                                 clocks = <&usb_phy1_always_on_clk32k>,
1372                                          <&usb_otg_ss1_refclk960m>;
1373                                 clock-names =   "wkupclk",
1374                                                 "refclk";
1375                                 #phy-cells = <0>;
1376                         };
1377
1378                         usb2_phy2: phy@4a085000 {
1379                                 compatible = "ti,dra7x-usb2-phy2",
1380                                              "ti,omap-usb2";
1381                                 reg = <0x4a085000 0x400>;
1382                                 syscon-phy-power = <&scm_conf 0xe74>;
1383                                 clocks = <&usb_phy2_always_on_clk32k>,
1384                                          <&usb_otg_ss2_refclk960m>;
1385                                 clock-names =   "wkupclk",
1386                                                 "refclk";
1387                                 #phy-cells = <0>;
1388                         };
1389
1390                         usb3_phy1: phy@4a084400 {
1391                                 compatible = "ti,omap-usb3";
1392                                 reg = <0x4a084400 0x80>,
1393                                       <0x4a084800 0x64>,
1394                                       <0x4a084c00 0x40>;
1395                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1396                                 syscon-phy-power = <&scm_conf 0x370>;
1397                                 clocks = <&usb_phy3_always_on_clk32k>,
1398                                          <&sys_clkin1>,
1399                                          <&usb_otg_ss1_refclk960m>;
1400                                 clock-names =   "wkupclk",
1401                                                 "sysclk",
1402                                                 "refclk";
1403                                 #phy-cells = <0>;
1404                         };
1405                 };
1406
1407                 omap_dwc3_1: omap_dwc3_1@48880000 {
1408                         compatible = "ti,dwc3";
1409                         ti,hwmods = "usb_otg_ss1";
1410                         reg = <0x48880000 0x10000>;
1411                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1412                         #address-cells = <1>;
1413                         #size-cells = <1>;
1414                         utmi-mode = <2>;
1415                         ranges;
1416                         usb1: usb@48890000 {
1417                                 compatible = "snps,dwc3";
1418                                 reg = <0x48890000 0x17000>;
1419                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1420                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1421                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1422                                 interrupt-names = "peripheral",
1423                                                   "host",
1424                                                   "otg";
1425                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1426                                 phy-names = "usb2-phy", "usb3-phy";
1427                                 maximum-speed = "super-speed";
1428                                 dr_mode = "otg";
1429                                 snps,dis_u3_susphy_quirk;
1430                                 snps,dis_u2_susphy_quirk;
1431                         };
1432                 };
1433
1434                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1435                         compatible = "ti,dwc3";
1436                         ti,hwmods = "usb_otg_ss2";
1437                         reg = <0x488c0000 0x10000>;
1438                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1439                         #address-cells = <1>;
1440                         #size-cells = <1>;
1441                         utmi-mode = <2>;
1442                         ranges;
1443                         usb2: usb@488d0000 {
1444                                 compatible = "snps,dwc3";
1445                                 reg = <0x488d0000 0x17000>;
1446                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1447                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1448                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1449                                 interrupt-names = "peripheral",
1450                                                   "host",
1451                                                   "otg";
1452                                 phys = <&usb2_phy2>;
1453                                 phy-names = "usb2-phy";
1454                                 maximum-speed = "high-speed";
1455                                 dr_mode = "otg";
1456                                 snps,dis_u3_susphy_quirk;
1457                                 snps,dis_u2_susphy_quirk;
1458                         };
1459                 };
1460
1461                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1462                 omap_dwc3_3: omap_dwc3_3@48900000 {
1463                         compatible = "ti,dwc3";
1464                         ti,hwmods = "usb_otg_ss3";
1465                         reg = <0x48900000 0x10000>;
1466                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1467                         #address-cells = <1>;
1468                         #size-cells = <1>;
1469                         utmi-mode = <2>;
1470                         ranges;
1471                         status = "disabled";
1472                         usb3: usb@48910000 {
1473                                 compatible = "snps,dwc3";
1474                                 reg = <0x48910000 0x17000>;
1475                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1476                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1477                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1478                                 interrupt-names = "peripheral",
1479                                                   "host",
1480                                                   "otg";
1481                                 maximum-speed = "high-speed";
1482                                 dr_mode = "otg";
1483                                 snps,dis_u3_susphy_quirk;
1484                                 snps,dis_u2_susphy_quirk;
1485                         };
1486                 };
1487
1488                 elm: elm@48078000 {
1489                         compatible = "ti,am3352-elm";
1490                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1491                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1492                         ti,hwmods = "elm";
1493                         status = "disabled";
1494                 };
1495
1496                 gpmc: gpmc@50000000 {
1497                         compatible = "ti,am3352-gpmc";
1498                         ti,hwmods = "gpmc";
1499                         reg = <0x50000000 0x37c>;      /* device IO registers */
1500                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1501                         gpmc,num-cs = <8>;
1502                         gpmc,num-waitpins = <2>;
1503                         #address-cells = <2>;
1504                         #size-cells = <1>;
1505                         interrupt-controller;
1506                         #interrupt-cells = <2>;
1507                         gpio-controller;
1508                         #gpio-cells = <2>;
1509                         status = "disabled";
1510                 };
1511
1512                 atl: atl@4843c000 {
1513                         compatible = "ti,dra7-atl";
1514                         reg = <0x4843c000 0x3ff>;
1515                         ti,hwmods = "atl";
1516                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1517                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1518                         clocks = <&atl_gfclk_mux>;
1519                         clock-names = "fck";
1520                         status = "disabled";
1521                 };
1522
1523                 mcasp1: mcasp@48460000 {
1524                         compatible = "ti,dra7-mcasp-audio";
1525                         ti,hwmods = "mcasp1";
1526                         reg = <0x48460000 0x2000>,
1527                               <0x45800000 0x1000>;
1528                         reg-names = "mpu","dat";
1529                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1530                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1531                         interrupt-names = "tx", "rx";
1532                         dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1533                         dma-names = "tx", "rx";
1534                         clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1535                                  <&mcasp1_ahclkr_mux>;
1536                         clock-names = "fck", "ahclkx", "ahclkr";
1537                         status = "disabled";
1538                 };
1539
1540                 mcasp2: mcasp@48464000 {
1541                         compatible = "ti,dra7-mcasp-audio";
1542                         ti,hwmods = "mcasp2";
1543                         reg = <0x48464000 0x2000>,
1544                               <0x45c00000 0x1000>;
1545                         reg-names = "mpu","dat";
1546                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1547                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1548                         interrupt-names = "tx", "rx";
1549                         dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1550                         dma-names = "tx", "rx";
1551                         clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1552                                  <&mcasp2_ahclkr_mux>;
1553                         clock-names = "fck", "ahclkx", "ahclkr";
1554                         status = "disabled";
1555                 };
1556
1557                 mcasp3: mcasp@48468000 {
1558                         compatible = "ti,dra7-mcasp-audio";
1559                         ti,hwmods = "mcasp3";
1560                         reg = <0x48468000 0x2000>,
1561                               <0x46000000 0x1000>;
1562                         reg-names = "mpu","dat";
1563                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1564                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1565                         interrupt-names = "tx", "rx";
1566                         dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1567                         dma-names = "tx", "rx";
1568                         clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1569                         clock-names = "fck", "ahclkx";
1570                         status = "disabled";
1571                 };
1572
1573                 mcasp4: mcasp@4846c000 {
1574                         compatible = "ti,dra7-mcasp-audio";
1575                         ti,hwmods = "mcasp4";
1576                         reg = <0x4846c000 0x2000>,
1577                               <0x48436000 0x1000>;
1578                         reg-names = "mpu","dat";
1579                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1580                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1581                         interrupt-names = "tx", "rx";
1582                         dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1583                         dma-names = "tx", "rx";
1584                         clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1585                         clock-names = "fck", "ahclkx";
1586                         status = "disabled";
1587                 };
1588
1589                 mcasp5: mcasp@48470000 {
1590                         compatible = "ti,dra7-mcasp-audio";
1591                         ti,hwmods = "mcasp5";
1592                         reg = <0x48470000 0x2000>,
1593                               <0x4843a000 0x1000>;
1594                         reg-names = "mpu","dat";
1595                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1596                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1597                         interrupt-names = "tx", "rx";
1598                         dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1599                         dma-names = "tx", "rx";
1600                         clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1601                         clock-names = "fck", "ahclkx";
1602                         status = "disabled";
1603                 };
1604
1605                 mcasp6: mcasp@48474000 {
1606                         compatible = "ti,dra7-mcasp-audio";
1607                         ti,hwmods = "mcasp6";
1608                         reg = <0x48474000 0x2000>,
1609                               <0x4844c000 0x1000>;
1610                         reg-names = "mpu","dat";
1611                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1612                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1613                         interrupt-names = "tx", "rx";
1614                         dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1615                         dma-names = "tx", "rx";
1616                         clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1617                         clock-names = "fck", "ahclkx";
1618                         status = "disabled";
1619                 };
1620
1621                 mcasp7: mcasp@48478000 {
1622                         compatible = "ti,dra7-mcasp-audio";
1623                         ti,hwmods = "mcasp7";
1624                         reg = <0x48478000 0x2000>,
1625                               <0x48450000 0x1000>;
1626                         reg-names = "mpu","dat";
1627                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1628                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1629                         interrupt-names = "tx", "rx";
1630                         dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1631                         dma-names = "tx", "rx";
1632                         clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1633                         clock-names = "fck", "ahclkx";
1634                         status = "disabled";
1635                 };
1636
1637                 mcasp8: mcasp@4847c000 {
1638                         compatible = "ti,dra7-mcasp-audio";
1639                         ti,hwmods = "mcasp8";
1640                         reg = <0x4847c000 0x2000>,
1641                               <0x48454000 0x1000>;
1642                         reg-names = "mpu","dat";
1643                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1644                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1645                         interrupt-names = "tx", "rx";
1646                         dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1647                         dma-names = "tx", "rx";
1648                         clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1649                         clock-names = "fck", "ahclkx";
1650                         status = "disabled";
1651                 };
1652
1653                 crossbar_mpu: crossbar@4a002a48 {
1654                         compatible = "ti,irq-crossbar";
1655                         reg = <0x4a002a48 0x130>;
1656                         interrupt-controller;
1657                         interrupt-parent = <&wakeupgen>;
1658                         #interrupt-cells = <3>;
1659                         ti,max-irqs = <160>;
1660                         ti,max-crossbar-sources = <MAX_SOURCES>;
1661                         ti,reg-size = <2>;
1662                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1663                         ti,irqs-skip = <10 133 139 140>;
1664                         ti,irqs-safe-map = <0>;
1665                 };
1666
1667                 mac: ethernet@48484000 {
1668                         compatible = "ti,dra7-cpsw","ti,cpsw";
1669                         ti,hwmods = "gmac";
1670                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1671                         clock-names = "fck", "cpts";
1672                         cpdma_channels = <8>;
1673                         ale_entries = <1024>;
1674                         bd_ram_size = <0x2000>;
1675                         no_bd_ram = <0>;
1676                         rx_descs = <64>;
1677                         mac_control = <0x20>;
1678                         slaves = <2>;
1679                         active_slave = <0>;
1680                         cpts_clock_mult = <0x80000000>;
1681                         cpts_clock_shift = <29>;
1682                         reg = <0x48484000 0x1000
1683                                0x48485200 0x2E00>;
1684                         #address-cells = <1>;
1685                         #size-cells = <1>;
1686
1687                         /*
1688                          * Do not allow gating of cpsw clock as workaround
1689                          * for errata i877. Keeping internal clock disabled
1690                          * causes the device switching characteristics
1691                          * to degrade over time and eventually fail to meet
1692                          * the data manual delay time/skew specs.
1693                          */
1694                         ti,no-idle;
1695
1696                         /*
1697                          * rx_thresh_pend
1698                          * rx_pend
1699                          * tx_pend
1700                          * misc_pend
1701                          */
1702                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1703                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1704                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1705                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1706                         ranges;
1707                         syscon = <&scm_conf>;
1708                         status = "disabled";
1709
1710                         davinci_mdio: mdio@48485000 {
1711                                 compatible = "ti,davinci_mdio";
1712                                 #address-cells = <1>;
1713                                 #size-cells = <0>;
1714                                 ti,hwmods = "davinci_mdio";
1715                                 bus_freq = <1000000>;
1716                                 reg = <0x48485000 0x100>;
1717                         };
1718
1719                         cpsw_emac0: slave@48480200 {
1720                                 /* Filled in by U-Boot */
1721                                 mac-address = [ 00 00 00 00 00 00 ];
1722                         };
1723
1724                         cpsw_emac1: slave@48480300 {
1725                                 /* Filled in by U-Boot */
1726                                 mac-address = [ 00 00 00 00 00 00 ];
1727                         };
1728
1729                         phy_sel: cpsw-phy-sel@4a002554 {
1730                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1731                                 reg= <0x4a002554 0x4>;
1732                                 reg-names = "gmii-sel";
1733                         };
1734                 };
1735
1736                 dcan1: can@481cc000 {
1737                         compatible = "ti,dra7-d_can";
1738                         ti,hwmods = "dcan1";
1739                         reg = <0x4ae3c000 0x2000>;
1740                         syscon-raminit = <&scm_conf 0x558 0>;
1741                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1742                         clocks = <&dcan1_sys_clk_mux>;
1743                         status = "disabled";
1744                 };
1745
1746                 dcan2: can@481d0000 {
1747                         compatible = "ti,dra7-d_can";
1748                         ti,hwmods = "dcan2";
1749                         reg = <0x48480000 0x2000>;
1750                         syscon-raminit = <&scm_conf 0x558 1>;
1751                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1752                         clocks = <&sys_clkin1>;
1753                         status = "disabled";
1754                 };
1755
1756                 dss: dss@58000000 {
1757                         compatible = "ti,dra7-dss";
1758                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1759                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1760                         status = "disabled";
1761                         ti,hwmods = "dss_core";
1762                         /* CTRL_CORE_DSS_PLL_CONTROL */
1763                         syscon-pll-ctrl = <&scm_conf 0x538>;
1764                         #address-cells = <1>;
1765                         #size-cells = <1>;
1766                         ranges;
1767
1768                         dispc@58001000 {
1769                                 compatible = "ti,dra7-dispc";
1770                                 reg = <0x58001000 0x1000>;
1771                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1772                                 ti,hwmods = "dss_dispc";
1773                                 clocks = <&dss_dss_clk>;
1774                                 clock-names = "fck";
1775                                 /* CTRL_CORE_SMA_SW_1 */
1776                                 syscon-pol = <&scm_conf 0x534>;
1777                         };
1778
1779                         hdmi: encoder@58060000 {
1780                                 compatible = "ti,dra7-hdmi";
1781                                 reg = <0x58040000 0x200>,
1782                                       <0x58040200 0x80>,
1783                                       <0x58040300 0x80>,
1784                                       <0x58060000 0x19000>;
1785                                 reg-names = "wp", "pll", "phy", "core";
1786                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1787                                 status = "disabled";
1788                                 ti,hwmods = "dss_hdmi";
1789                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1790                                 clock-names = "fck", "sys_clk";
1791                         };
1792                 };
1793
1794                 epwmss0: epwmss@4843e000 {
1795                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1796                         reg = <0x4843e000 0x30>;
1797                         ti,hwmods = "epwmss0";
1798                         #address-cells = <1>;
1799                         #size-cells = <1>;
1800                         status = "disabled";
1801                         ranges;
1802
1803                         ehrpwm0: pwm@4843e200 {
1804                                 compatible = "ti,dra746-ehrpwm",
1805                                              "ti,am3352-ehrpwm";
1806                                 #pwm-cells = <3>;
1807                                 reg = <0x4843e200 0x80>;
1808                                 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1809                                 clock-names = "tbclk", "fck";
1810                                 status = "disabled";
1811                         };
1812
1813                         ecap0: ecap@4843e100 {
1814                                 compatible = "ti,dra746-ecap",
1815                                              "ti,am3352-ecap";
1816                                 #pwm-cells = <3>;
1817                                 reg = <0x4843e100 0x80>;
1818                                 clocks = <&l4_root_clk_div>;
1819                                 clock-names = "fck";
1820                                 status = "disabled";
1821                         };
1822                 };
1823
1824                 epwmss1: epwmss@48440000 {
1825                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1826                         reg = <0x48440000 0x30>;
1827                         ti,hwmods = "epwmss1";
1828                         #address-cells = <1>;
1829                         #size-cells = <1>;
1830                         status = "disabled";
1831                         ranges;
1832
1833                         ehrpwm1: pwm@48440200 {
1834                                 compatible = "ti,dra746-ehrpwm",
1835                                              "ti,am3352-ehrpwm";
1836                                 #pwm-cells = <3>;
1837                                 reg = <0x48440200 0x80>;
1838                                 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1839                                 clock-names = "tbclk", "fck";
1840                                 status = "disabled";
1841                         };
1842
1843                         ecap1: ecap@48440100 {
1844                                 compatible = "ti,dra746-ecap",
1845                                              "ti,am3352-ecap";
1846                                 #pwm-cells = <3>;
1847                                 reg = <0x48440100 0x80>;
1848                                 clocks = <&l4_root_clk_div>;
1849                                 clock-names = "fck";
1850                                 status = "disabled";
1851                         };
1852                 };
1853
1854                 epwmss2: epwmss@48442000 {
1855                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1856                         reg = <0x48442000 0x30>;
1857                         ti,hwmods = "epwmss2";
1858                         #address-cells = <1>;
1859                         #size-cells = <1>;
1860                         status = "disabled";
1861                         ranges;
1862
1863                         ehrpwm2: pwm@48442200 {
1864                                 compatible = "ti,dra746-ehrpwm",
1865                                              "ti,am3352-ehrpwm";
1866                                 #pwm-cells = <3>;
1867                                 reg = <0x48442200 0x80>;
1868                                 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1869                                 clock-names = "tbclk", "fck";
1870                                 status = "disabled";
1871                         };
1872
1873                         ecap2: ecap@48442100 {
1874                                 compatible = "ti,dra746-ecap",
1875                                              "ti,am3352-ecap";
1876                                 #pwm-cells = <3>;
1877                                 reg = <0x48442100 0x80>;
1878                                 clocks = <&l4_root_clk_div>;
1879                                 clock-names = "fck";
1880                                 status = "disabled";
1881                         };
1882                 };
1883         };
1884
1885         thermal_zones: thermal-zones {
1886                 #include "omap4-cpu-thermal.dtsi"
1887                 #include "omap5-gpu-thermal.dtsi"
1888                 #include "omap5-core-thermal.dtsi"
1889                 #include "dra7-dspeve-thermal.dtsi"
1890                 #include "dra7-iva-thermal.dtsi"
1891         };
1892
1893 };
1894
1895 &cpu_thermal {
1896         polling-delay = <500>; /* milliseconds */
1897 };
1898
1899 /include/ "dra7xx-clocks.dtsi"