arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 i2c4 = &i2c5;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37         };
  38
  39         timer {
  40                 compatible = "arm,armv7-timer";
  41                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  42                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  43                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  44                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  45         };
  46
  47         gic: interrupt-controller@48211000 {
  48                 compatible = "arm,cortex-a15-gic";
  49                 interrupt-controller;
  50                 #interrupt-cells = <3>;
  51                 arm,routable-irqs = <192>;
  52                 reg = <0x48211000 0x1000>,
  53                       <0x48212000 0x1000>,
  54                       <0x48214000 0x2000>,
  55                       <0x48216000 0x2000>;
  56                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  57         };
  58
  59         /*
  60          * The soc node represents the soc top level view. It is used for IPs
  61          * that are not memory mapped in the MPU view or for the MPU itself.
  62          */
  63         soc {
  64                 compatible = "ti,omap-infra";
  65                 mpu {
  66                         compatible = "ti,omap5-mpu";
  67                         ti,hwmods = "mpu";
  68                 };
  69         };
  70
  71         /*
  72          * XXX: Use a flat representation of the SOC interconnect.
  73          * The real OMAP interconnect network is quite complex.
  74          * Since it will not bring real advantage to represent that in DT for
  75          * the moment, just use a fake OCP bus entry to represent the whole bus
  76          * hierarchy.
  77          */
  78         ocp {
  79                 compatible = "ti,dra7-l3-noc", "simple-bus";
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges;
  83                 ti,hwmods = "l3_main_1", "l3_main_2";
  84                 reg = <0x44000000 0x1000000>,
  85                       <0x45000000 0x1000>;
  86                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
  88
  89                 prm: prm@4ae06000 {
  90                         compatible = "ti,dra7-prm";
  91                         reg = <0x4ae06000 0x3000>;
  92
  93                         prm_clocks: clocks {
  94                                 #address-cells = <1>;
  95                                 #size-cells = <0>;
  96                         };
  97
  98                         prm_clockdomains: clockdomains {
  99                         };
 100                 };
 101
 102                 cm_core_aon: cm_core_aon@4a005000 {
 103                         compatible = "ti,dra7-cm-core-aon";
 104                         reg = <0x4a005000 0x2000>;
 105
 106                         cm_core_aon_clocks: clocks {
 107                                 #address-cells = <1>;
 108                                 #size-cells = <0>;
 109                         };
 110
 111                         cm_core_aon_clockdomains: clockdomains {
 112                         };
 113                 };
 114
 115                 cm_core: cm_core@4a008000 {
 116                         compatible = "ti,dra7-cm-core";
 117                         reg = <0x4a008000 0x3000>;
 118
 119                         cm_core_clocks: clocks {
 120                                 #address-cells = <1>;
 121                                 #size-cells = <0>;
 122                         };
 123
 124                         cm_core_clockdomains: clockdomains {
 125                         };
 126                 };
 127
 128                 counter32k: counter@4ae04000 {
 129                         compatible = "ti,omap-counter32k";
 130                         reg = <0x4ae04000 0x40>;
 131                         ti,hwmods = "counter_32k";
 132                 };
 133
 134                 dra7_ctrl_general: tisyscon@4a002e00 {
 135                         compatible = "syscon";
 136                         reg = <0x4a002e00 0x7c>;
 137                 };
 138
 139                 pbias_regulator: pbias_regulator {
 140                         compatible = "ti,pbias-omap";
 141                         reg = <0 0x4>;
 142                         syscon = <&dra7_ctrl_general>;
 143                         pbias_mmc_reg: pbias_mmc_omap5 {
 144                                 regulator-name = "pbias_mmc_omap5";
 145                                 regulator-min-microvolt = <1800000>;
 146                                 regulator-max-microvolt = <3000000>;
 147                         };
 148                 };
 149
 150                 dra7_pmx_core: pinmux@4a003400 {
 151                         compatible = "pinctrl-single";
 152                         reg = <0x4a003400 0x0464>;
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         pinctrl-single,register-width = <32>;
 156                         pinctrl-single,function-mask = <0x3fffffff>;
 157                 };
 158
 159                 sdma: dma-controller@4a056000 {
 160                         compatible = "ti,omap4430-sdma";
 161                         reg = <0x4a056000 0x1000>;
 162                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 163                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 165                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 166                         #dma-cells = <1>;
 167                         #dma-channels = <32>;
 168                         #dma-requests = <127>;
 169                 };
 170
 171                 gpio1: gpio@4ae10000 {
 172                         compatible = "ti,omap4-gpio";
 173                         reg = <0x4ae10000 0x200>;
 174                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 175                         ti,hwmods = "gpio1";
 176                         gpio-controller;
 177                         #gpio-cells = <2>;
 178                         interrupt-controller;
 179                         #interrupt-cells = <1>;
 180                 };
 181
 182                 gpio2: gpio@48055000 {
 183                         compatible = "ti,omap4-gpio";
 184                         reg = <0x48055000 0x200>;
 185                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 186                         ti,hwmods = "gpio2";
 187                         gpio-controller;
 188                         #gpio-cells = <2>;
 189                         interrupt-controller;
 190                         #interrupt-cells = <1>;
 191                 };
 192
 193                 gpio3: gpio@48057000 {
 194                         compatible = "ti,omap4-gpio";
 195                         reg = <0x48057000 0x200>;
 196                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 197                         ti,hwmods = "gpio3";
 198                         gpio-controller;
 199                         #gpio-cells = <2>;
 200                         interrupt-controller;
 201                         #interrupt-cells = <1>;
 202                 };
 203
 204                 gpio4: gpio@48059000 {
 205                         compatible = "ti,omap4-gpio";
 206                         reg = <0x48059000 0x200>;
 207                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 208                         ti,hwmods = "gpio4";
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211                         interrupt-controller;
 212                         #interrupt-cells = <1>;
 213                 };
 214
 215                 gpio5: gpio@4805b000 {
 216                         compatible = "ti,omap4-gpio";
 217                         reg = <0x4805b000 0x200>;
 218                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 219                         ti,hwmods = "gpio5";
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222                         interrupt-controller;
 223                         #interrupt-cells = <1>;
 224                 };
 225
 226                 gpio6: gpio@4805d000 {
 227                         compatible = "ti,omap4-gpio";
 228                         reg = <0x4805d000 0x200>;
 229                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 230                         ti,hwmods = "gpio6";
 231                         gpio-controller;
 232                         #gpio-cells = <2>;
 233                         interrupt-controller;
 234                         #interrupt-cells = <1>;
 235                 };
 236
 237                 gpio7: gpio@48051000 {
 238                         compatible = "ti,omap4-gpio";
 239                         reg = <0x48051000 0x200>;
 240                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 241                         ti,hwmods = "gpio7";
 242                         gpio-controller;
 243                         #gpio-cells = <2>;
 244                         interrupt-controller;
 245                         #interrupt-cells = <1>;
 246                 };
 247
 248                 gpio8: gpio@48053000 {
 249                         compatible = "ti,omap4-gpio";
 250                         reg = <0x48053000 0x200>;
 251                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 252                         ti,hwmods = "gpio8";
 253                         gpio-controller;
 254                         #gpio-cells = <2>;
 255                         interrupt-controller;
 256                         #interrupt-cells = <1>;
 257                 };
 258
 259                 uart1: serial@4806a000 {
 260                         compatible = "ti,omap4-uart";
 261                         reg = <0x4806a000 0x100>;
 262                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 263                         ti,hwmods = "uart1";
 264                         clock-frequency = <48000000>;
 265                         status = "disabled";
 266                 };
 267
 268                 uart2: serial@4806c000 {
 269                         compatible = "ti,omap4-uart";
 270                         reg = <0x4806c000 0x100>;
 271                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 272                         ti,hwmods = "uart2";
 273                         clock-frequency = <48000000>;
 274                         status = "disabled";
 275                 };
 276
 277                 uart3: serial@48020000 {
 278                         compatible = "ti,omap4-uart";
 279                         reg = <0x48020000 0x100>;
 280                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 281                         ti,hwmods = "uart3";
 282                         clock-frequency = <48000000>;
 283                         status = "disabled";
 284                 };
 285
 286                 uart4: serial@4806e000 {
 287                         compatible = "ti,omap4-uart";
 288                         reg = <0x4806e000 0x100>;
 289                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 290                         ti,hwmods = "uart4";
 291                         clock-frequency = <48000000>;
 292                         status = "disabled";
 293                 };
 294
 295                 uart5: serial@48066000 {
 296                         compatible = "ti,omap4-uart";
 297                         reg = <0x48066000 0x100>;
 298                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 299                         ti,hwmods = "uart5";
 300                         clock-frequency = <48000000>;
 301                         status = "disabled";
 302                 };
 303
 304                 uart6: serial@48068000 {
 305                         compatible = "ti,omap4-uart";
 306                         reg = <0x48068000 0x100>;
 307                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 308                         ti,hwmods = "uart6";
 309                         clock-frequency = <48000000>;
 310                         status = "disabled";
 311                 };
 312
 313                 uart7: serial@48420000 {
 314                         compatible = "ti,omap4-uart";
 315                         reg = <0x48420000 0x100>;
 316                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 317                         ti,hwmods = "uart7";
 318                         clock-frequency = <48000000>;
 319                         status = "disabled";
 320                 };
 321
 322                 uart8: serial@48422000 {
 323                         compatible = "ti,omap4-uart";
 324                         reg = <0x48422000 0x100>;
 325                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 326                         ti,hwmods = "uart8";
 327                         clock-frequency = <48000000>;
 328                         status = "disabled";
 329                 };
 330
 331                 uart9: serial@48424000 {
 332                         compatible = "ti,omap4-uart";
 333                         reg = <0x48424000 0x100>;
 334                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 335                         ti,hwmods = "uart9";
 336                         clock-frequency = <48000000>;
 337                         status = "disabled";
 338                 };
 339
 340                 uart10: serial@4ae2b000 {
 341                         compatible = "ti,omap4-uart";
 342                         reg = <0x4ae2b000 0x100>;
 343                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 344                         ti,hwmods = "uart10";
 345                         clock-frequency = <48000000>;
 346                         status = "disabled";
 347                 };
 348
 349                 timer1: timer@4ae18000 {
 350                         compatible = "ti,omap5430-timer";
 351                         reg = <0x4ae18000 0x80>;
 352                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 353                         ti,hwmods = "timer1";
 354                         ti,timer-alwon;
 355                 };
 356
 357                 timer2: timer@48032000 {
 358                         compatible = "ti,omap5430-timer";
 359                         reg = <0x48032000 0x80>;
 360                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 361                         ti,hwmods = "timer2";
 362                 };
 363
 364                 timer3: timer@48034000 {
 365                         compatible = "ti,omap5430-timer";
 366                         reg = <0x48034000 0x80>;
 367                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "timer3";
 369                 };
 370
 371                 timer4: timer@48036000 {
 372                         compatible = "ti,omap5430-timer";
 373                         reg = <0x48036000 0x80>;
 374                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 375                         ti,hwmods = "timer4";
 376                 };
 377
 378                 timer5: timer@48820000 {
 379                         compatible = "ti,omap5430-timer";
 380                         reg = <0x48820000 0x80>;
 381                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 382                         ti,hwmods = "timer5";
 383                         ti,timer-dsp;
 384                 };
 385
 386                 timer6: timer@48822000 {
 387                         compatible = "ti,omap5430-timer";
 388                         reg = <0x48822000 0x80>;
 389                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 390                         ti,hwmods = "timer6";
 391                         ti,timer-dsp;
 392                         ti,timer-pwm;
 393                 };
 394
 395                 timer7: timer@48824000 {
 396                         compatible = "ti,omap5430-timer";
 397                         reg = <0x48824000 0x80>;
 398                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 399                         ti,hwmods = "timer7";
 400                         ti,timer-dsp;
 401                 };
 402
 403                 timer8: timer@48826000 {
 404                         compatible = "ti,omap5430-timer";
 405                         reg = <0x48826000 0x80>;
 406                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 407                         ti,hwmods = "timer8";
 408                         ti,timer-dsp;
 409                         ti,timer-pwm;
 410                 };
 411
 412                 timer9: timer@4803e000 {
 413                         compatible = "ti,omap5430-timer";
 414                         reg = <0x4803e000 0x80>;
 415                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 416                         ti,hwmods = "timer9";
 417                 };
 418
 419                 timer10: timer@48086000 {
 420                         compatible = "ti,omap5430-timer";
 421                         reg = <0x48086000 0x80>;
 422                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 423                         ti,hwmods = "timer10";
 424                 };
 425
 426                 timer11: timer@48088000 {
 427                         compatible = "ti,omap5430-timer";
 428                         reg = <0x48088000 0x80>;
 429                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 430                         ti,hwmods = "timer11";
 431                         ti,timer-pwm;
 432                 };
 433
 434                 timer13: timer@48828000 {
 435                         compatible = "ti,omap5430-timer";
 436                         reg = <0x48828000 0x80>;
 437                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 438                         ti,hwmods = "timer13";
 439                         status = "disabled";
 440                 };
 441
 442                 timer14: timer@4882a000 {
 443                         compatible = "ti,omap5430-timer";
 444                         reg = <0x4882a000 0x80>;
 445                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 446                         ti,hwmods = "timer14";
 447                         status = "disabled";
 448                 };
 449
 450                 timer15: timer@4882c000 {
 451                         compatible = "ti,omap5430-timer";
 452                         reg = <0x4882c000 0x80>;
 453                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 454                         ti,hwmods = "timer15";
 455                         status = "disabled";
 456                 };
 457
 458                 timer16: timer@4882e000 {
 459                         compatible = "ti,omap5430-timer";
 460                         reg = <0x4882e000 0x80>;
 461                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 462                         ti,hwmods = "timer16";
 463                         status = "disabled";
 464                 };
 465
 466                 wdt2: wdt@4ae14000 {
 467                         compatible = "ti,omap4-wdt";
 468                         reg = <0x4ae14000 0x80>;
 469                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "wd_timer2";
 471                 };
 472
 473                 hwspinlock: spinlock@4a0f6000 {
 474                         compatible = "ti,omap4-hwspinlock";
 475                         reg = <0x4a0f6000 0x1000>;
 476                         ti,hwmods = "spinlock";
 477                         #hwlock-cells = <1>;
 478                 };
 479
 480                 dmm@4e000000 {
 481                         compatible = "ti,omap5-dmm";
 482                         reg = <0x4e000000 0x800>;
 483                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 484                         ti,hwmods = "dmm";
 485                 };
 486
 487                 i2c1: i2c@48070000 {
 488                         compatible = "ti,omap4-i2c";
 489                         reg = <0x48070000 0x100>;
 490                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         ti,hwmods = "i2c1";
 494                         status = "disabled";
 495                 };
 496
 497                 i2c2: i2c@48072000 {
 498                         compatible = "ti,omap4-i2c";
 499                         reg = <0x48072000 0x100>;
 500                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         ti,hwmods = "i2c2";
 504                         status = "disabled";
 505                 };
 506
 507                 i2c3: i2c@48060000 {
 508                         compatible = "ti,omap4-i2c";
 509                         reg = <0x48060000 0x100>;
 510                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         ti,hwmods = "i2c3";
 514                         status = "disabled";
 515                 };
 516
 517                 i2c4: i2c@4807a000 {
 518                         compatible = "ti,omap4-i2c";
 519                         reg = <0x4807a000 0x100>;
 520                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         ti,hwmods = "i2c4";
 524                         status = "disabled";
 525                 };
 526
 527                 i2c5: i2c@4807c000 {
 528                         compatible = "ti,omap4-i2c";
 529                         reg = <0x4807c000 0x100>;
 530                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         ti,hwmods = "i2c5";
 534                         status = "disabled";
 535                 };
 536
 537                 mmc1: mmc@4809c000 {
 538                         compatible = "ti,omap4-hsmmc";
 539                         reg = <0x4809c000 0x400>;
 540                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 541                         ti,hwmods = "mmc1";
 542                         ti,dual-volt;
 543                         ti,needs-special-reset;
 544                         dmas = <&sdma 61>, <&sdma 62>;
 545                         dma-names = "tx", "rx";
 546                         status = "disabled";
 547                         pbias-supply = <&pbias_mmc_reg>;
 548                 };
 549
 550                 mmc2: mmc@480b4000 {
 551                         compatible = "ti,omap4-hsmmc";
 552                         reg = <0x480b4000 0x400>;
 553                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 554                         ti,hwmods = "mmc2";
 555                         ti,needs-special-reset;
 556                         dmas = <&sdma 47>, <&sdma 48>;
 557                         dma-names = "tx", "rx";
 558                         status = "disabled";
 559                 };
 560
 561                 mmc3: mmc@480ad000 {
 562                         compatible = "ti,omap4-hsmmc";
 563                         reg = <0x480ad000 0x400>;
 564                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 565                         ti,hwmods = "mmc3";
 566                         ti,needs-special-reset;
 567                         dmas = <&sdma 77>, <&sdma 78>;
 568                         dma-names = "tx", "rx";
 569                         status = "disabled";
 570                 };
 571
 572                 mmc4: mmc@480d1000 {
 573                         compatible = "ti,omap4-hsmmc";
 574                         reg = <0x480d1000 0x400>;
 575                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 576                         ti,hwmods = "mmc4";
 577                         ti,needs-special-reset;
 578                         dmas = <&sdma 57>, <&sdma 58>;
 579                         dma-names = "tx", "rx";
 580                         status = "disabled";
 581                 };
 582
 583                 abb_mpu: regulator-abb-mpu {
 584                         compatible = "ti,abb-v3";
 585                         regulator-name = "abb_mpu";
 586                         #address-cells = <0>;
 587                         #size-cells = <0>;
 588                         clocks = <&sys_clkin1>;
 589                         ti,settling-time = <50>;
 590                         ti,clock-cycles = <16>;
 591
 592                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 593                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 594                               <0x4ae0c158 0x4>;
 595                         reg-names = "setup-address", "control-address",
 596                                     "int-address", "efuse-address",
 597                                     "ldo-address";
 598                         ti,tranxdone-status-mask = <0x80>;
 599                         /* LDOVBBMPU_FBB_MUX_CTRL */
 600                         ti,ldovbb-override-mask = <0x400>;
 601                         /* LDOVBBMPU_FBB_VSET_OUT */
 602                         ti,ldovbb-vset-mask = <0x1F>;
 603
 604                         /*
 605                          * NOTE: only FBB mode used but actual vset will
 606                          * determine final biasing
 607                          */
 608                         ti,abb_info = <
 609                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 610                         1060000         0       0x0     0 0x02000000 0x01F00000
 611                         1160000         0       0x4     0 0x02000000 0x01F00000
 612                         1210000         0       0x8     0 0x02000000 0x01F00000
 613                         >;
 614                 };
 615
 616                 abb_ivahd: regulator-abb-ivahd {
 617                         compatible = "ti,abb-v3";
 618                         regulator-name = "abb_ivahd";
 619                         #address-cells = <0>;
 620                         #size-cells = <0>;
 621                         clocks = <&sys_clkin1>;
 622                         ti,settling-time = <50>;
 623                         ti,clock-cycles = <16>;
 624
 625                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 626                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 627                               <0x4a002470 0x4>;
 628                         reg-names = "setup-address", "control-address",
 629                                     "int-address", "efuse-address",
 630                                     "ldo-address";
 631                         ti,tranxdone-status-mask = <0x40000000>;
 632                         /* LDOVBBIVA_FBB_MUX_CTRL */
 633                         ti,ldovbb-override-mask = <0x400>;
 634                         /* LDOVBBIVA_FBB_VSET_OUT */
 635                         ti,ldovbb-vset-mask = <0x1F>;
 636
 637                         /*
 638                          * NOTE: only FBB mode used but actual vset will
 639                          * determine final biasing
 640                          */
 641                         ti,abb_info = <
 642                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 643                         1055000         0       0x0     0 0x02000000 0x01F00000
 644                         1150000         0       0x4     0 0x02000000 0x01F00000
 645                         1250000         0       0x8     0 0x02000000 0x01F00000
 646                         >;
 647                 };
 648
 649                 abb_dspeve: regulator-abb-dspeve {
 650                         compatible = "ti,abb-v3";
 651                         regulator-name = "abb_dspeve";
 652                         #address-cells = <0>;
 653                         #size-cells = <0>;
 654                         clocks = <&sys_clkin1>;
 655                         ti,settling-time = <50>;
 656                         ti,clock-cycles = <16>;
 657
 658                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 659                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 660                               <0x4a00246c 0x4>;
 661                         reg-names = "setup-address", "control-address",
 662                                     "int-address", "efuse-address",
 663                                     "ldo-address";
 664                         ti,tranxdone-status-mask = <0x20000000>;
 665                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 666                         ti,ldovbb-override-mask = <0x400>;
 667                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 668                         ti,ldovbb-vset-mask = <0x1F>;
 669
 670                         /*
 671                          * NOTE: only FBB mode used but actual vset will
 672                          * determine final biasing
 673                          */
 674                         ti,abb_info = <
 675                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 676                         1055000         0       0x0     0 0x02000000 0x01F00000
 677                         1150000         0       0x4     0 0x02000000 0x01F00000
 678                         1250000         0       0x8     0 0x02000000 0x01F00000
 679                         >;
 680                 };
 681
 682                 abb_gpu: regulator-abb-gpu {
 683                         compatible = "ti,abb-v3";
 684                         regulator-name = "abb_gpu";
 685                         #address-cells = <0>;
 686                         #size-cells = <0>;
 687                         clocks = <&sys_clkin1>;
 688                         ti,settling-time = <50>;
 689                         ti,clock-cycles = <16>;
 690
 691                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 692                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 693                               <0x4ae0c154 0x4>;
 694                         reg-names = "setup-address", "control-address",
 695                                     "int-address", "efuse-address",
 696                                     "ldo-address";
 697                         ti,tranxdone-status-mask = <0x10000000>;
 698                         /* LDOVBBGPU_FBB_MUX_CTRL */
 699                         ti,ldovbb-override-mask = <0x400>;
 700                         /* LDOVBBGPU_FBB_VSET_OUT */
 701                         ti,ldovbb-vset-mask = <0x1F>;
 702
 703                         /*
 704                          * NOTE: only FBB mode used but actual vset will
 705                          * determine final biasing
 706                          */
 707                         ti,abb_info = <
 708                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 709                         1090000         0       0x0     0 0x02000000 0x01F00000
 710                         1210000         0       0x4     0 0x02000000 0x01F00000
 711                         1280000         0       0x8     0 0x02000000 0x01F00000
 712                         >;
 713                 };
 714
 715                 mcspi1: spi@48098000 {
 716                         compatible = "ti,omap4-mcspi";
 717                         reg = <0x48098000 0x200>;
 718                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 719                         #address-cells = <1>;
 720                         #size-cells = <0>;
 721                         ti,hwmods = "mcspi1";
 722                         ti,spi-num-cs = <4>;
 723                         dmas = <&sdma 35>,
 724                                <&sdma 36>,
 725                                <&sdma 37>,
 726                                <&sdma 38>,
 727                                <&sdma 39>,
 728                                <&sdma 40>,
 729                                <&sdma 41>,
 730                                <&sdma 42>;
 731                         dma-names = "tx0", "rx0", "tx1", "rx1",
 732                                     "tx2", "rx2", "tx3", "rx3";
 733                         status = "disabled";
 734                 };
 735
 736                 mcspi2: spi@4809a000 {
 737                         compatible = "ti,omap4-mcspi";
 738                         reg = <0x4809a000 0x200>;
 739                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                         ti,hwmods = "mcspi2";
 743                         ti,spi-num-cs = <2>;
 744                         dmas = <&sdma 43>,
 745                                <&sdma 44>,
 746                                <&sdma 45>,
 747                                <&sdma 46>;
 748                         dma-names = "tx0", "rx0", "tx1", "rx1";
 749                         status = "disabled";
 750                 };
 751
 752                 mcspi3: spi@480b8000 {
 753                         compatible = "ti,omap4-mcspi";
 754                         reg = <0x480b8000 0x200>;
 755                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 756                         #address-cells = <1>;
 757                         #size-cells = <0>;
 758                         ti,hwmods = "mcspi3";
 759                         ti,spi-num-cs = <2>;
 760                         dmas = <&sdma 15>, <&sdma 16>;
 761                         dma-names = "tx0", "rx0";
 762                         status = "disabled";
 763                 };
 764
 765                 mcspi4: spi@480ba000 {
 766                         compatible = "ti,omap4-mcspi";
 767                         reg = <0x480ba000 0x200>;
 768                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 769                         #address-cells = <1>;
 770                         #size-cells = <0>;
 771                         ti,hwmods = "mcspi4";
 772                         ti,spi-num-cs = <1>;
 773                         dmas = <&sdma 70>, <&sdma 71>;
 774                         dma-names = "tx0", "rx0";
 775                         status = "disabled";
 776                 };
 777
 778                 qspi: qspi@4b300000 {
 779                         compatible = "ti,dra7xxx-qspi";
 780                         reg = <0x4b300000 0x100>;
 781                         reg-names = "qspi_base";
 782                         #address-cells = <1>;
 783                         #size-cells = <0>;
 784                         ti,hwmods = "qspi";
 785                         clocks = <&qspi_gfclk_div>;
 786                         clock-names = "fck";
 787                         num-cs = <4>;
 788                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 789                         status = "disabled";
 790                 };
 791
 792                 omap_control_sata: control-phy@4a002374 {
 793                         compatible = "ti,control-phy-pipe3";
 794                         reg = <0x4a002374 0x4>;
 795                         reg-names = "power";
 796                         clocks = <&sys_clkin1>;
 797                         clock-names = "sysclk";
 798                 };
 799
 800                 /* OCP2SCP3 */
 801                 ocp2scp@4a090000 {
 802                         compatible = "ti,omap-ocp2scp";
 803                         #address-cells = <1>;
 804                         #size-cells = <1>;
 805                         ranges;
 806                         reg = <0x4a090000 0x20>;
 807                         ti,hwmods = "ocp2scp3";
 808                         sata_phy: phy@4A096000 {
 809                                 compatible = "ti,phy-pipe3-sata";
 810                                 reg = <0x4A096000 0x80>, /* phy_rx */
 811                                       <0x4A096400 0x64>, /* phy_tx */
 812                                       <0x4A096800 0x40>; /* pll_ctrl */
 813                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 814                                 ctrl-module = <&omap_control_sata>;
 815                                 clocks = <&sys_clkin1>;
 816                                 clock-names = "sysclk";
 817                                 #phy-cells = <0>;
 818                         };
 819
 820                         pcie1_phy: pciephy@4a094000 {
 821                                 compatible = "ti,phy-pipe3-pcie";
 822                                 reg = <0x4a094000 0x80>, /* phy_rx */
 823                                       <0x4a094400 0x64>; /* phy_tx */
 824                                 reg-names = "phy_rx", "phy_tx";
 825                                 ctrl-module = <&omap_control_pcie1phy>;
 826                                 clocks = <&dpll_pcie_ref_ck>,
 827                                          <&dpll_pcie_ref_m2ldo_ck>,
 828                                          <&optfclk_pciephy1_32khz>,
 829                                          <&optfclk_pciephy1_clk>,
 830                                          <&optfclk_pciephy1_div_clk>,
 831                                          <&optfclk_pciephy_div>;
 832                                 clock-names = "dpll_ref", "dpll_ref_m2",
 833                                               "wkupclk", "refclk",
 834                                               "div-clk", "phy-div";
 835                                 #phy-cells = <0>;
 836                                 id = <1>;
 837                                 ti,hwmods = "pcie1-phy";
 838                         };
 839
 840                         pcie2_phy: pciephy@4a095000 {
 841                                 compatible = "ti,phy-pipe3-pcie";
 842                                 reg = <0x4a095000 0x80>, /* phy_rx */
 843                                       <0x4a095400 0x64>; /* phy_tx */
 844                                 reg-names = "phy_rx", "phy_tx";
 845                                 ctrl-module = <&omap_control_pcie2phy>;
 846                                 clocks = <&dpll_pcie_ref_ck>,
 847                                          <&dpll_pcie_ref_m2ldo_ck>,
 848                                          <&optfclk_pciephy2_32khz>,
 849                                          <&optfclk_pciephy2_clk>,
 850                                          <&optfclk_pciephy2_div_clk>,
 851                                          <&optfclk_pciephy_div>;
 852                                 clock-names = "dpll_ref", "dpll_ref_m2",
 853                                               "wkupclk", "refclk",
 854                                               "div-clk", "phy-div";
 855                                 #phy-cells = <0>;
 856                                 ti,hwmods = "pcie2-phy";
 857                                 id = <2>;
 858                                 status = "disabled";
 859                         };
 860                 };
 861
 862                 sata: sata@4a141100 {
 863                         compatible = "snps,dwc-ahci";
 864                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 865                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 866                         phys = <&sata_phy>;
 867                         phy-names = "sata-phy";
 868                         clocks = <&sata_ref_clk>;
 869                         ti,hwmods = "sata";
 870                 };
 871
 872                 omap_control_pcie1phy: control-phy@0x4a003c40 {
 873                         compatible = "ti,control-phy-pcie";
 874                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
 875                         reg-names = "power", "control_sma", "pcie_pcs";
 876                         clocks = <&sys_clkin1>;
 877                         clock-names = "sysclk";
 878                 };
 879
 880                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
 881                         compatible = "ti,control-phy-pcie";
 882                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
 883                         reg-names = "power", "control_sma", "pcie_pcs";
 884                         clocks = <&sys_clkin1>;
 885                         clock-names = "sysclk";
 886                         status = "disabled";
 887                 };
 888
 889                 omap_control_usb2phy1: control-phy@4a002300 {
 890                         compatible = "ti,control-phy-usb2";
 891                         reg = <0x4a002300 0x4>;
 892                         reg-names = "power";
 893                 };
 894
 895                 omap_control_usb3phy1: control-phy@4a002370 {
 896                         compatible = "ti,control-phy-pipe3";
 897                         reg = <0x4a002370 0x4>;
 898                         reg-names = "power";
 899                 };
 900
 901                 omap_control_usb2phy2: control-phy@0x4a002e74 {
 902                         compatible = "ti,control-phy-usb2-dra7";
 903                         reg = <0x4a002e74 0x4>;
 904                         reg-names = "power";
 905                 };
 906
 907                 /* OCP2SCP1 */
 908                 ocp2scp@4a080000 {
 909                         compatible = "ti,omap-ocp2scp";
 910                         #address-cells = <1>;
 911                         #size-cells = <1>;
 912                         ranges;
 913                         reg = <0x4a080000 0x20>;
 914                         ti,hwmods = "ocp2scp1";
 915
 916                         usb2_phy1: phy@4a084000 {
 917                                 compatible = "ti,omap-usb2";
 918                                 reg = <0x4a084000 0x400>;
 919                                 ctrl-module = <&omap_control_usb2phy1>;
 920                                 clocks = <&usb_phy1_always_on_clk32k>,
 921                                          <&usb_otg_ss1_refclk960m>;
 922                                 clock-names =   "wkupclk",
 923                                                 "refclk";
 924                                 #phy-cells = <0>;
 925                         };
 926
 927                         usb2_phy2: phy@4a085000 {
 928                                 compatible = "ti,omap-usb2";
 929                                 reg = <0x4a085000 0x400>;
 930                                 ctrl-module = <&omap_control_usb2phy2>;
 931                                 clocks = <&usb_phy2_always_on_clk32k>,
 932                                          <&usb_otg_ss2_refclk960m>;
 933                                 clock-names =   "wkupclk",
 934                                                 "refclk";
 935                                 #phy-cells = <0>;
 936                         };
 937
 938                         usb3_phy1: phy@4a084400 {
 939                                 compatible = "ti,omap-usb3";
 940                                 reg = <0x4a084400 0x80>,
 941                                       <0x4a084800 0x64>,
 942                                       <0x4a084c00 0x40>;
 943                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 944                                 ctrl-module = <&omap_control_usb3phy1>;
 945                                 clocks = <&usb_phy3_always_on_clk32k>,
 946                                          <&sys_clkin1>,
 947                                          <&usb_otg_ss1_refclk960m>;
 948                                 clock-names =   "wkupclk",
 949                                                 "sysclk",
 950                                                 "refclk";
 951                                 #phy-cells = <0>;
 952                         };
 953                 };
 954
 955                 omap_dwc3_1@48880000 {
 956                         compatible = "ti,dwc3";
 957                         ti,hwmods = "usb_otg_ss1";
 958                         reg = <0x48880000 0x10000>;
 959                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 960                         #address-cells = <1>;
 961                         #size-cells = <1>;
 962                         utmi-mode = <2>;
 963                         ranges;
 964                         usb1: usb@48890000 {
 965                                 compatible = "snps,dwc3";
 966                                 reg = <0x48890000 0x17000>;
 967                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 968                                 phys = <&usb2_phy1>, <&usb3_phy1>;
 969                                 phy-names = "usb2-phy", "usb3-phy";
 970                                 tx-fifo-resize;
 971                                 maximum-speed = "super-speed";
 972                                 dr_mode = "otg";
 973                         };
 974                 };
 975
 976                 omap_dwc3_2@488c0000 {
 977                         compatible = "ti,dwc3";
 978                         ti,hwmods = "usb_otg_ss2";
 979                         reg = <0x488c0000 0x10000>;
 980                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 981                         #address-cells = <1>;
 982                         #size-cells = <1>;
 983                         utmi-mode = <2>;
 984                         ranges;
 985                         usb2: usb@488d0000 {
 986                                 compatible = "snps,dwc3";
 987                                 reg = <0x488d0000 0x17000>;
 988                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 989                                 phys = <&usb2_phy2>;
 990                                 phy-names = "usb2-phy";
 991                                 tx-fifo-resize;
 992                                 maximum-speed = "high-speed";
 993                                 dr_mode = "otg";
 994                         };
 995                 };
 996
 997                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
 998                 omap_dwc3_3@48900000 {
 999                         compatible = "ti,dwc3";
1000                         ti,hwmods = "usb_otg_ss3";
1001                         reg = <0x48900000 0x10000>;
1002                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1003                         #address-cells = <1>;
1004                         #size-cells = <1>;
1005                         utmi-mode = <2>;
1006                         ranges;
1007                         status = "disabled";
1008                         usb3: usb@48910000 {
1009                                 compatible = "snps,dwc3";
1010                                 reg = <0x48910000 0x17000>;
1011                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1012                                 tx-fifo-resize;
1013                                 maximum-speed = "high-speed";
1014                                 dr_mode = "otg";
1015                         };
1016                 };
1017
1018                 omap_dwc3_4@48940000 {
1019                         compatible = "ti,dwc3";
1020                         ti,hwmods = "usb_otg_ss4";
1021                         reg = <0x48940000 0x10000>;
1022                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1023                         #address-cells = <1>;
1024                         #size-cells = <1>;
1025                         utmi-mode = <2>;
1026                         ranges;
1027                         status = "disabled";
1028                         usb4: usb@48950000 {
1029                                 compatible = "snps,dwc3";
1030                                 reg = <0x48950000 0x17000>;
1031                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1032                                 tx-fifo-resize;
1033                                 maximum-speed = "high-speed";
1034                                 dr_mode = "otg";
1035                         };
1036                 };
1037
1038                 elm: elm@48078000 {
1039                         compatible = "ti,am3352-elm";
1040                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1041                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1042                         ti,hwmods = "elm";
1043                         status = "disabled";
1044                 };
1045
1046                 gpmc: gpmc@50000000 {
1047                         compatible = "ti,am3352-gpmc";
1048                         ti,hwmods = "gpmc";
1049                         reg = <0x50000000 0x37c>;      /* device IO registers */
1050                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1051                         gpmc,num-cs = <8>;
1052                         gpmc,num-waitpins = <2>;
1053                         #address-cells = <2>;
1054                         #size-cells = <1>;
1055                         status = "disabled";
1056                 };
1057
1058                 crossbar_mpu: crossbar@4a020000 {
1059                         compatible = "ti,irq-crossbar";
1060                         reg = <0x4a002a48 0x130>;
1061                         ti,max-irqs = <160>;
1062                         ti,max-crossbar-sources = <MAX_SOURCES>;
1063                         ti,reg-size = <2>;
1064                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1065                         ti,irqs-skip = <10 133 139 140>;
1066                         ti,irqs-safe-map = <0>;
1067                 };
1068         };
1069 };
1070
1071 /include/ "dra7xx-clocks.dtsi"