arch/arm/boot/dts/exynos4415.dtsi

   1 /*
   2  * Samsung's Exynos4415 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *
   6  * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
   7  * based board files can include this file and provide values for board
   8  * specific bindings.
   9  *
  10  * Note: This file does not include device nodes for all the controllers in
  11  * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
  12  * nodes can be added to this file.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include "skeleton.dtsi"
  20 #include <dt-bindings/clock/exynos4415.h>
  21 #include <dt-bindings/clock/exynos-audss-clk.h>
  22
  23 / {
  24         compatible = "samsung,exynos4415";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 mshc0 = &mshc_0;
  32                 mshc1 = &mshc_1;
  33                 mshc2 = &mshc_2;
  34                 spi0 = &spi_0;
  35                 spi1 = &spi_1;
  36                 spi2 = &spi_2;
  37                 i2c0 = &i2c_0;
  38                 i2c1 = &i2c_1;
  39                 i2c2 = &i2c_2;
  40                 i2c3 = &i2c_3;
  41                 i2c4 = &i2c_4;
  42                 i2c5 = &i2c_5;
  43                 i2c6 = &i2c_6;
  44                 i2c7 = &i2c_7;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@a00 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         reg = <0xa00>;
  55                         clock-frequency = <1600000000>;
  56                 };
  57
  58                 cpu1: cpu@a01 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a9";
  61                         reg = <0xa01>;
  62                         clock-frequency = <1600000000>;
  63                 };
  64
  65                 cpu2: cpu@a02 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a9";
  68                         reg = <0xa02>;
  69                         clock-frequency = <1600000000>;
  70                 };
  71
  72                 cpu3: cpu@a03 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a9";
  75                         reg = <0xa03>;
  76                         clock-frequency = <1600000000>;
  77                 };
  78         };
  79
  80         soc: soc {
  81                 compatible = "simple-bus";
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 ranges;
  85
  86                 sysram@02020000 {
  87                         compatible = "mmio-sram";
  88                         reg = <0x02020000 0x50000>;
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         ranges = <0 0x02020000 0x50000>;
  92
  93                         smp-sysram@0 {
  94                                 compatible = "samsung,exynos4210-sysram";
  95                                 reg = <0x0 0x1000>;
  96                         };
  97
  98                         smp-sysram@4f000 {
  99                                 compatible = "samsung,exynos4210-sysram-ns";
 100                                 reg = <0x4f000 0x1000>;
 101                         };
 102                 };
 103
 104                 pinctrl_2: pinctrl@03860000 {
 105                         compatible = "samsung,exynos4415-pinctrl";
 106                         reg = <0x03860000 0x1000>;
 107                         interrupts = <0 242 0>;
 108                 };
 109
 110                 chipid@10000000 {
 111                         compatible = "samsung,exynos4210-chipid";
 112                         reg = <0x10000000 0x100>;
 113                 };
 114
 115                 sysreg_system_controller: syscon@10010000 {
 116                         compatible = "samsung,exynos4-sysreg", "syscon";
 117                         reg = <0x10010000 0x400>;
 118                 };
 119
 120                 pmu_system_controller: system-controller@10020000 {
 121                         compatible = "samsung,exynos4415-pmu", "syscon";
 122                         reg = <0x10020000 0x4000>;
 123                 };
 124
 125                 mipi_phy: video-phy@10020710 {
 126                         compatible = "samsung,s5pv210-mipi-video-phy";
 127                         reg = <0x10020710 8>;
 128                         #phy-cells = <1>;
 129                 };
 130
 131                 pd_cam: cam-power-domain@10024000 {
 132                         compatible = "samsung,exynos4210-pd";
 133                         reg = <0x10024000 0x20>;
 134                 };
 135
 136                 pd_tv: tv-power-domain@10024020 {
 137                         compatible = "samsung,exynos4210-pd";
 138                         reg = <0x10024020 0x20>;
 139                 };
 140
 141                 pd_mfc: mfc-power-domain@10024040 {
 142                         compatible = "samsung,exynos4210-pd";
 143                         reg = <0x10024040 0x20>;
 144                 };
 145
 146                 pd_g3d: g3d-power-domain@10024060 {
 147                         compatible = "samsung,exynos4210-pd";
 148                         reg = <0x10024060 0x20>;
 149                 };
 150
 151                 pd_lcd0: lcd0-power-domain@10024080 {
 152                         compatible = "samsung,exynos4210-pd";
 153                         reg = <0x10024080 0x20>;
 154                 };
 155
 156                 pd_isp0: isp0-power-domain@100240A0 {
 157                         compatible = "samsung,exynos4210-pd";
 158                         reg = <0x100240A0 0x20>;
 159                 };
 160
 161                 pd_isp1: isp1-power-domain@100240E0 {
 162                         compatible = "samsung,exynos4210-pd";
 163                         reg = <0x100240E0 0x20>;
 164                 };
 165
 166                 cmu: clock-controller@10030000 {
 167                         compatible = "samsung,exynos4415-cmu";
 168                         reg = <0x10030000 0x18000>;
 169                         #clock-cells = <1>;
 170                 };
 171
 172                 rtc: rtc@10070000 {
 173                         compatible = "samsung,exynos3250-rtc";
 174                         reg = <0x10070000 0x100>;
 175                         interrupts = <0 73 0>, <0 74 0>;
 176                         status = "disabled";
 177                 };
 178
 179                 mct@10050000 {
 180                         compatible = "samsung,exynos4210-mct";
 181                         reg = <0x10050000 0x800>;
 182                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 183                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 184                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 185                         clock-names = "fin_pll", "mct";
 186                 };
 187
 188                 gic: interrupt-controller@10481000 {
 189                         compatible = "arm,cortex-a9-gic";
 190                         #interrupt-cells = <3>;
 191                         interrupt-controller;
 192                         reg = <0x10481000 0x1000>,
 193                               <0x10482000 0x1000>,
 194                               <0x10484000 0x2000>,
 195                               <0x10486000 0x2000>;
 196                         interrupts = <1 9 0xf04>;
 197                 };
 198
 199                 l2c: l2-cache-controller@10502000 {
 200                         compatible = "arm,pl310-cache";
 201                         reg = <0x10502000 0x1000>;
 202                         cache-unified;
 203                         cache-level = <2>;
 204                         arm,tag-latency = <2 2 1>;
 205                         arm,data-latency = <3 2 1>;
 206                         arm,double-linefill = <1>;
 207                         arm,double-linefill-incr = <0>;
 208                         arm,double-linefill-wrap = <1>;
 209                         arm,prefetch-drop = <1>;
 210                         arm,prefetch-offset = <7>;
 211                 };
 212
 213                 cmu_dmc: clock-controller@105C0000 {
 214                         compatible = "samsung,exynos4415-cmu-dmc";
 215                         reg = <0x105C0000 0x3000>;
 216                         #clock-cells = <1>;
 217                 };
 218
 219                 pinctrl_1: pinctrl@11000000 {
 220                         compatible = "samsung,exynos4415-pinctrl";
 221                         reg = <0x11000000 0x1000>;
 222                         interrupts = <0 225 0>;
 223
 224                         wakeup-interrupt-controller {
 225                                 compatible = "samsung,exynos4210-wakeup-eint";
 226                                 interrupt-parent = <&gic>;
 227                                 interrupts = <0 48 0>;
 228                         };
 229                 };
 230
 231                 pinctrl_0: pinctrl@11400000 {
 232                         compatible = "samsung,exynos4415-pinctrl";
 233                         reg = <0x11400000 0x1000>;
 234                         interrupts = <0 240 0>;
 235                 };
 236
 237                 hsotg: hsotg@12480000 {
 238                         compatible = "samsung,s3c6400-hsotg";
 239                         reg = <0x12480000 0x20000>;
 240                         interrupts = <0 141 0>;
 241                         clocks = <&cmu CLK_USBDEVICE>;
 242                         clock-names = "otg";
 243                         phys = <&exynos_usbphy 0>;
 244                         phy-names = "usb2-phy";
 245                         status = "disabled";
 246                 };
 247
 248                 mshc_0: mshc@12510000 {
 249                         compatible = "samsung,exynos5250-dw-mshc";
 250                         reg = <0x12510000 0x1000>;
 251                         interrupts = <0 142 0>;
 252                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 253                         clock-names = "biu", "ciu";
 254                         fifo-depth = <0x80>;
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         status = "disabled";
 258                 };
 259
 260                 mshc_1: mshc@12520000 {
 261                         compatible = "samsung,exynos5250-dw-mshc";
 262                         reg = <0x12520000 0x1000>;
 263                         interrupts = <0 143 0>;
 264                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 265                         clock-names = "biu", "ciu";
 266                         fifo-depth = <0x80>;
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         status = "disabled";
 270                 };
 271
 272                 mshc_2: mshc@12530000 {
 273                         compatible = "samsung,exynos5250-dw-mshc";
 274                         reg = <0x12530000 0x1000>;
 275                         interrupts = <0 144 0>;
 276                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 277                         clock-names = "biu", "ciu";
 278                         fifo-depth = <0x80>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         status = "disabled";
 282                 };
 283
 284                 ehci: ehci@12580000 {
 285                         compatible = "samsung,exynos4210-ehci";
 286                         reg = <0x12580000 0x100>;
 287                         interrupts = <0 140 0>;
 288                         clocks = <&cmu CLK_USBHOST>;
 289                         clock-names = "usbhost";
 290                         status = "disabled";
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         port@0 {
 294                                 reg = <0>;
 295                                 phys = <&exynos_usbphy 1>;
 296                                 status = "disabled";
 297                         };
 298                         port@1 {
 299                                 reg = <1>;
 300                                 phys = <&exynos_usbphy 2>;
 301                                 status = "disabled";
 302                         };
 303                         port@2 {
 304                                 reg = <2>;
 305                                 phys = <&exynos_usbphy 3>;
 306                                 status = "disabled";
 307                         };
 308                 };
 309
 310                 ohci: ohci@12590000 {
 311                         compatible = "samsung,exynos4210-ohci";
 312                         reg = <0x12590000 0x100>;
 313                         interrupts = <0 140 0>;
 314                         clocks = <&cmu CLK_USBHOST>;
 315                         clock-names = "usbhost";
 316                         status = "disabled";
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         port@0 {
 320                                 reg = <0>;
 321                                 phys = <&exynos_usbphy 1>;
 322                                 status = "disabled";
 323                         };
 324                 };
 325
 326                 exynos_usbphy: exynos-usbphy@125B0000 {
 327                         compatible = "samsung,exynos4x12-usb2-phy";
 328                         reg = <0x125B0000 0x100>;
 329                         samsung,pmureg-phandle = <&pmu_system_controller>;
 330                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 331                         clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
 332                         clock-names = "phy", "ref";
 333                         #phy-cells = <1>;
 334                         status = "disabled";
 335                 };
 336
 337                 amba {
 338                         compatible = "arm,amba-bus";
 339                         #address-cells = <1>;
 340                         #size-cells = <1>;
 341                         interrupt-parent = <&gic>;
 342                         ranges;
 343
 344                         pdma0: pdma@12680000 {
 345                                 compatible = "arm,pl330", "arm,primecell";
 346                                 reg = <0x12680000 0x1000>;
 347                                 interrupts = <0 138 0>;
 348                                 clocks = <&cmu CLK_PDMA0>;
 349                                 clock-names = "apb_pclk";
 350                                 #dma-cells = <1>;
 351                                 #dma-channels = <8>;
 352                                 #dma-requests = <32>;
 353                         };
 354
 355                         pdma1: pdma@12690000 {
 356                                 compatible = "arm,pl330", "arm,primecell";
 357                                 reg = <0x12690000 0x1000>;
 358                                 interrupts = <0 139 0>;
 359                                 clocks = <&cmu CLK_PDMA1>;
 360                                 clock-names = "apb_pclk";
 361                                 #dma-cells = <1>;
 362                                 #dma-channels = <8>;
 363                                 #dma-requests = <32>;
 364                         };
 365                 };
 366
 367                 adc: adc@126C0000 {
 368                         compatible = "samsung,exynos3250-adc",
 369                                      "samsung,exynos-adc-v2";
 370                         reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 371                         interrupts = <0 137 0>;
 372                         clock-names = "adc", "sclk";
 373                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 374                         #io-channel-cells = <1>;
 375                         io-channel-ranges;
 376                         status = "disabled";
 377                 };
 378
 379                 serial_0: serial@13800000 {
 380                         compatible = "samsung,exynos4210-uart";
 381                         reg = <0x13800000 0x100>;
 382                         interrupts = <0 109 0>;
 383                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 384                         clock-names = "uart", "clk_uart_baud0";
 385                         status = "disabled";
 386                 };
 387
 388                 serial_1: serial@13810000 {
 389                         compatible = "samsung,exynos4210-uart";
 390                         reg = <0x13810000 0x100>;
 391                         interrupts = <0 110 0>;
 392                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 393                         clock-names = "uart", "clk_uart_baud0";
 394                         status = "disabled";
 395                 };
 396
 397                 serial_2: serial@13820000 {
 398                         compatible = "samsung,exynos4210-uart";
 399                         reg = <0x13820000 0x100>;
 400                         interrupts = <0 111 0>;
 401                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 402                         clock-names = "uart", "clk_uart_baud0";
 403                         status = "disabled";
 404                 };
 405
 406                 serial_3: serial@13830000 {
 407                         compatible = "samsung,exynos4210-uart";
 408                         reg = <0x13830000 0x100>;
 409                         interrupts = <0 112 0>;
 410                         clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
 411                         clock-names = "uart", "clk_uart_baud0";
 412                         status = "disabled";
 413                 };
 414
 415                 i2c_0: i2c@13860000 {
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         compatible = "samsung,s3c2440-i2c";
 419                         reg = <0x13860000 0x100>;
 420                         interrupts = <0 113 0>;
 421                         clocks = <&cmu CLK_I2C0>;
 422                         clock-names = "i2c";
 423                         pinctrl-names = "default";
 424                         pinctrl-0 = <&i2c0_bus>;
 425                         status = "disabled";
 426                 };
 427
 428                 i2c_1: i2c@13870000 {
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         compatible = "samsung,s3c2440-i2c";
 432                         reg = <0x13870000 0x100>;
 433                         interrupts = <0 114 0>;
 434                         clocks = <&cmu CLK_I2C1>;
 435                         clock-names = "i2c";
 436                         pinctrl-names = "default";
 437                         pinctrl-0 = <&i2c1_bus>;
 438                         status = "disabled";
 439                 };
 440
 441                 i2c_2: i2c@13880000 {
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         compatible = "samsung,s3c2440-i2c";
 445                         reg = <0x13880000 0x100>;
 446                         interrupts = <0 115 0>;
 447                         clocks = <&cmu CLK_I2C2>;
 448                         clock-names = "i2c";
 449                         pinctrl-names = "default";
 450                         pinctrl-0 = <&i2c2_bus>;
 451                         status = "disabled";
 452                 };
 453
 454                 i2c_3: i2c@13890000 {
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         compatible = "samsung,s3c2440-i2c";
 458                         reg = <0x13890000 0x100>;
 459                         interrupts = <0 116 0>;
 460                         clocks = <&cmu CLK_I2C3>;
 461                         clock-names = "i2c";
 462                         pinctrl-names = "default";
 463                         pinctrl-0 = <&i2c3_bus>;
 464                         status = "disabled";
 465                 };
 466
 467                 i2c_4: i2c@138A0000 {
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                         compatible = "samsung,s3c2440-i2c";
 471                         reg = <0x138A0000 0x100>;
 472                         interrupts = <0 117 0>;
 473                         clocks = <&cmu CLK_I2C4>;
 474                         clock-names = "i2c";
 475                         pinctrl-names = "default";
 476                         pinctrl-0 = <&i2c4_bus>;
 477                         status = "disabled";
 478                 };
 479
 480                 i2c_5: i2c@138B0000 {
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         compatible = "samsung,s3c2440-i2c";
 484                         reg = <0x138B0000 0x100>;
 485                         interrupts = <0 118 0>;
 486                         clocks = <&cmu CLK_I2C5>;
 487                         clock-names = "i2c";
 488                         pinctrl-names = "default";
 489                         pinctrl-0 = <&i2c5_bus>;
 490                         status = "disabled";
 491                 };
 492
 493                 i2c_6: i2c@138C0000 {
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         compatible = "samsung,s3c2440-i2c";
 497                         reg = <0x138C0000 0x100>;
 498                         interrupts = <0 119 0>;
 499                         clocks = <&cmu CLK_I2C6>;
 500                         clock-names = "i2c";
 501                         pinctrl-names = "default";
 502                         pinctrl-0 = <&i2c6_bus>;
 503                         status = "disabled";
 504                 };
 505
 506                 i2c_7: i2c@138D0000 {
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         compatible = "samsung,s3c2440-i2c";
 510                         reg = <0x138D0000 0x100>;
 511                         interrupts = <0 120 0>;
 512                         clocks = <&cmu CLK_I2C7>;
 513                         clock-names = "i2c";
 514                         pinctrl-names = "default";
 515                         pinctrl-0 = <&i2c7_bus>;
 516                         status = "disabled";
 517                 };
 518
 519                 spi_0: spi@13920000 {
 520                         compatible = "samsung,exynos4210-spi";
 521                         reg = <0x13920000 0x100>;
 522                         interrupts = <0 121 0>;
 523                         dmas = <&pdma0 7>, <&pdma0 6>;
 524                         dma-names = "tx", "rx";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 528                         clock-names = "spi", "spi_busclk0";
 529                         samsung,spi-src-clk = <0>;
 530                         pinctrl-names = "default";
 531                         pinctrl-0 = <&spi0_bus>;
 532                         status = "disabled";
 533                 };
 534
 535                 spi_1: spi@13930000 {
 536                         compatible = "samsung,exynos4210-spi";
 537                         reg = <0x13930000 0x100>;
 538                         interrupts = <0 122 0>;
 539                         dmas = <&pdma1 7>, <&pdma1 6>;
 540                         dma-names = "tx", "rx";
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 544                         clock-names = "spi", "spi_busclk0";
 545                         samsung,spi-src-clk = <0>;
 546                         pinctrl-names = "default";
 547                         pinctrl-0 = <&spi1_bus>;
 548                         status = "disabled";
 549                 };
 550
 551                 spi_2: spi@13940000 {
 552                         compatible = "samsung,exynos4210-spi";
 553                         reg = <0x13940000 0x100>;
 554                         interrupts = <0 123 0>;
 555                         dmas = <&pdma0 9>, <&pdma0 8>;
 556                         dma-names = "tx", "rx";
 557                         #address-cells = <1>;
 558                         #size-cells = <0>;
 559                         clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
 560                         clock-names = "spi", "spi_busclk0";
 561                         samsung,spi-src-clk = <0>;
 562                         pinctrl-names = "default";
 563                         pinctrl-0 = <&spi2_bus>;
 564                         status = "disabled";
 565                 };
 566
 567                 clock_audss: clock-controller@03810000 {
 568                         compatible = "samsung,exynos4210-audss-clock";
 569                         reg = <0x03810000 0x0C>;
 570                         #clock-cells = <1>;
 571                 };
 572
 573                 i2s0: i2s@3830000 {
 574                         compatible = "samsung,s5pv210-i2s";
 575                         reg = <0x03830000 0x100>;
 576                         interrupts = <0 124 0>;
 577                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 578                                 <&clock_audss EXYNOS_SCLK_I2S>;
 579                         clock-names = "iis", "i2s_opclk0";
 580                         dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
 581                         dma-names = "tx", "rx", "tx-sec";
 582                         pinctrl-names = "default";
 583                         pinctrl-0 = <&i2s0_bus>;
 584                         samsung,idma-addr = <0x03000000>;
 585                         status = "disabled";
 586                 };
 587
 588                 pwm: pwm@139D0000 {
 589                         compatible = "samsung,exynos4210-pwm";
 590                         reg = <0x139D0000 0x1000>;
 591                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 592                                      <0 107 0>, <0 108 0>;
 593                         #pwm-cells = <3>;
 594                         status = "disabled";
 595                 };
 596
 597                 pmu {
 598                         compatible = "arm,cortex-a9-pmu";
 599                         interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
 600                 };
 601         };
 602 };
 603
 604 #include "exynos4415-pinctrl.dtsi"