arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22
  23 / {
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         pmu {
  35                 compatible = "arm,cortex-a9-pmu";
  36                 interrupt-parent = <&combiner>;
  37                 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
  38         };
  39
  40         sysram@02020000 {
  41                 compatible = "mmio-sram";
  42                 reg = <0x02020000 0x40000>;
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 ranges = <0 0x02020000 0x40000>;
  46
  47                 smp-sysram@0 {
  48                         compatible = "samsung,exynos4210-sysram";
  49                         reg = <0x0 0x1000>;
  50                 };
  51
  52                 smp-sysram@2f000 {
  53                         compatible = "samsung,exynos4210-sysram-ns";
  54                         reg = <0x2f000 0x1000>;
  55                 };
  56         };
  57
  58         pd_isp: isp-power-domain@10023CA0 {
  59                 compatible = "samsung,exynos4210-pd";
  60                 reg = <0x10023CA0 0x20>;
  61         };
  62
  63         clock: clock-controller@10030000 {
  64                 compatible = "samsung,exynos4412-clock";
  65                 reg = <0x10030000 0x20000>;
  66                 #clock-cells = <1>;
  67         };
  68
  69         mct@10050000 {
  70                 compatible = "samsung,exynos4412-mct";
  71                 reg = <0x10050000 0x800>;
  72                 interrupt-parent = <&mct_map>;
  73                 interrupts = <0>, <1>, <2>, <3>, <4>;
  74                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  75                 clock-names = "fin_pll", "mct";
  76
  77                 mct_map: mct-map {
  78                         #interrupt-cells = <1>;
  79                         #address-cells = <0>;
  80                         #size-cells = <0>;
  81                         interrupt-map = <0 &gic 0 57 0>,
  82                                         <1 &combiner 12 5>,
  83                                         <2 &combiner 12 6>,
  84                                         <3 &combiner 12 7>,
  85                                         <4 &gic 1 12 0>;
  86                 };
  87         };
  88
  89         combiner: interrupt-controller@10440000 {
  90                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  91                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  92                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  93                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  94                              <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
  95         };
  96
  97         pinctrl_0: pinctrl@11400000 {
  98                 compatible = "samsung,exynos4x12-pinctrl";
  99                 reg = <0x11400000 0x1000>;
 100                 interrupts = <0 47 0>;
 101         };
 102
 103         pinctrl_1: pinctrl@11000000 {
 104                 compatible = "samsung,exynos4x12-pinctrl";
 105                 reg = <0x11000000 0x1000>;
 106                 interrupts = <0 46 0>;
 107
 108                 wakup_eint: wakeup-interrupt-controller {
 109                         compatible = "samsung,exynos4210-wakeup-eint";
 110                         interrupt-parent = <&gic>;
 111                         interrupts = <0 32 0>;
 112                 };
 113         };
 114
 115         adc: adc@126C0000 {
 116                 compatible = "samsung,exynos-adc-v1";
 117                 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 118                 interrupt-parent = <&combiner>;
 119                 interrupts = <10 3>;
 120                 clocks = <&clock CLK_TSADC>;
 121                 clock-names = "adc";
 122                 #io-channel-cells = <1>;
 123                 io-channel-ranges;
 124                 status = "disabled";
 125         };
 126
 127         pinctrl_2: pinctrl@03860000 {
 128                 compatible = "samsung,exynos4x12-pinctrl";
 129                 reg = <0x03860000 0x1000>;
 130                 interrupt-parent = <&combiner>;
 131                 interrupts = <10 0>;
 132         };
 133
 134         pinctrl_3: pinctrl@106E0000 {
 135                 compatible = "samsung,exynos4x12-pinctrl";
 136                 reg = <0x106E0000 0x1000>;
 137                 interrupts = <0 72 0>;
 138         };
 139
 140         g2d@10800000 {
 141                 compatible = "samsung,exynos4212-g2d";
 142                 reg = <0x10800000 0x1000>;
 143                 interrupts = <0 89 0>;
 144                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 145                 clock-names = "sclk_fimg2d", "fimg2d";
 146                 status = "disabled";
 147         };
 148
 149         camera {
 150                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 151                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 152                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 153
 154                 fimc_0: fimc@11800000 {
 155                         compatible = "samsung,exynos4212-fimc";
 156                         samsung,pix-limits = <4224 8192 1920 4224>;
 157                         samsung,mainscaler-ext;
 158                         samsung,isp-wb;
 159                         samsung,cam-if;
 160                 };
 161
 162                 fimc_1: fimc@11810000 {
 163                         compatible = "samsung,exynos4212-fimc";
 164                         samsung,pix-limits = <4224 8192 1920 4224>;
 165                         samsung,mainscaler-ext;
 166                         samsung,isp-wb;
 167                         samsung,cam-if;
 168                 };
 169
 170                 fimc_2: fimc@11820000 {
 171                         compatible = "samsung,exynos4212-fimc";
 172                         samsung,pix-limits = <4224 8192 1920 4224>;
 173                         samsung,mainscaler-ext;
 174                         samsung,isp-wb;
 175                         samsung,lcd-wb;
 176                         samsung,cam-if;
 177                 };
 178
 179                 fimc_3: fimc@11830000 {
 180                         compatible = "samsung,exynos4212-fimc";
 181                         samsung,pix-limits = <1920 8192 1366 1920>;
 182                         samsung,rotators = <0>;
 183                         samsung,mainscaler-ext;
 184                         samsung,isp-wb;
 185                         samsung,lcd-wb;
 186                 };
 187
 188                 fimc_lite_0: fimc-lite@12390000 {
 189                         compatible = "samsung,exynos4212-fimc-lite";
 190                         reg = <0x12390000 0x1000>;
 191                         interrupts = <0 105 0>;
 192                         samsung,power-domain = <&pd_isp>;
 193                         clocks = <&clock CLK_FIMC_LITE0>;
 194                         clock-names = "flite";
 195                         status = "disabled";
 196                 };
 197
 198                 fimc_lite_1: fimc-lite@123A0000 {
 199                         compatible = "samsung,exynos4212-fimc-lite";
 200                         reg = <0x123A0000 0x1000>;
 201                         interrupts = <0 106 0>;
 202                         samsung,power-domain = <&pd_isp>;
 203                         clocks = <&clock CLK_FIMC_LITE1>;
 204                         clock-names = "flite";
 205                         status = "disabled";
 206                 };
 207
 208                 fimc_is: fimc-is@12000000 {
 209                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
 210                         reg = <0x12000000 0x260000>;
 211                         interrupts = <0 90 0>, <0 95 0>;
 212                         samsung,power-domain = <&pd_isp>;
 213                         clocks = <&clock CLK_FIMC_LITE0>,
 214                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 215                                  <&clock CLK_PPMUISPMX>,
 216                                  <&clock CLK_MOUT_MPLL_USER_T>,
 217                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 218                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 219                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
 220                                  <&clock CLK_DIV_MCUISP0>,
 221                                  <&clock CLK_DIV_MCUISP1>,
 222                                  <&clock CLK_SCLK_UART_ISP>,
 223                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 224                                  <&clock CLK_ACLK400_MCUISP>,
 225                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 226                         clock-names = "lite0", "lite1", "ppmuispx",
 227                                       "ppmuispmx", "mpll", "isp",
 228                                       "drc", "fd", "mcuisp",
 229                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 230                                       "mcuispdiv1", "uart", "aclk200",
 231                                       "div_aclk200", "aclk400mcuisp",
 232                                       "div_aclk400mcuisp";
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                         ranges;
 236                         status = "disabled";
 237
 238                         pmu {
 239                                 reg = <0x10020000 0x3000>;
 240                         };
 241
 242                         i2c1_isp: i2c-isp@12140000 {
 243                                 compatible = "samsung,exynos4212-i2c-isp";
 244                                 reg = <0x12140000 0x100>;
 245                                 clocks = <&clock CLK_I2C1_ISP>;
 246                                 clock-names = "i2c_isp";
 247                                 #address-cells = <1>;
 248                                 #size-cells = <0>;
 249                         };
 250                 };
 251         };
 252
 253         mshc_0: mmc@12550000 {
 254                 compatible = "samsung,exynos4412-dw-mshc";
 255                 reg = <0x12550000 0x1000>;
 256                 interrupts = <0 77 0>;
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 fifo-depth = <0x80>;
 260                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 261                 clock-names = "biu", "ciu";
 262                 status = "disabled";
 263         };
 264 };