arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420", "samsung,exynos5";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x0>;
  60                         clock-frequency = <1800000000>;
  61                         cci-control-port = <&cci_control1>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <0x1>;
  68                         clock-frequency = <1800000000>;
  69                         cci-control-port = <&cci_control1>;
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a15";
  75                         reg = <0x2>;
  76                         clock-frequency = <1800000000>;
  77                         cci-control-port = <&cci_control1>;
  78                 };
  79
  80                 cpu3: cpu@3 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a15";
  83                         reg = <0x3>;
  84                         clock-frequency = <1800000000>;
  85                         cci-control-port = <&cci_control1>;
  86                 };
  87
  88                 cpu4: cpu@100 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         reg = <0x100>;
  92                         clock-frequency = <1000000000>;
  93                         cci-control-port = <&cci_control0>;
  94                 };
  95
  96                 cpu5: cpu@101 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a7";
  99                         reg = <0x101>;
 100                         clock-frequency = <1000000000>;
 101                         cci-control-port = <&cci_control0>;
 102                 };
 103
 104                 cpu6: cpu@102 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a7";
 107                         reg = <0x102>;
 108                         clock-frequency = <1000000000>;
 109                         cci-control-port = <&cci_control0>;
 110                 };
 111
 112                 cpu7: cpu@103 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a7";
 115                         reg = <0x103>;
 116                         clock-frequency = <1000000000>;
 117                         cci-control-port = <&cci_control0>;
 118                 };
 119         };
 120
 121         cci@10d20000 {
 122                 compatible = "arm,cci-400";
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 reg = <0x10d20000 0x1000>;
 126                 ranges = <0x0 0x10d20000 0x6000>;
 127
 128                 cci_control0: slave-if@4000 {
 129                         compatible = "arm,cci-400-ctrl-if";
 130                         interface-type = "ace";
 131                         reg = <0x4000 0x1000>;
 132                 };
 133                 cci_control1: slave-if@5000 {
 134                         compatible = "arm,cci-400-ctrl-if";
 135                         interface-type = "ace";
 136                         reg = <0x5000 0x1000>;
 137                 };
 138         };
 139
 140         sysram@02020000 {
 141                 compatible = "mmio-sram";
 142                 reg = <0x02020000 0x54000>;
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0 0x02020000 0x54000>;
 146
 147                 smp-sysram@0 {
 148                         compatible = "samsung,exynos4210-sysram";
 149                         reg = <0x0 0x1000>;
 150                 };
 151
 152                 smp-sysram@53000 {
 153                         compatible = "samsung,exynos4210-sysram-ns";
 154                         reg = <0x53000 0x1000>;
 155                 };
 156         };
 157
 158         clock: clock-controller@10010000 {
 159                 compatible = "samsung,exynos5420-clock";
 160                 reg = <0x10010000 0x30000>;
 161                 #clock-cells = <1>;
 162         };
 163
 164         clock_audss: audss-clock-controller@3810000 {
 165                 compatible = "samsung,exynos5420-audss-clock";
 166                 reg = <0x03810000 0x0C>;
 167                 #clock-cells = <1>;
 168                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 169                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 170                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 171         };
 172
 173         mfc: codec@11000000 {
 174                 compatible = "samsung,mfc-v7";
 175                 reg = <0x11000000 0x10000>;
 176                 interrupts = <0 96 0>;
 177                 clocks = <&clock CLK_MFC>;
 178                 clock-names = "mfc";
 179         };
 180
 181         mmc_0: mmc@12200000 {
 182                 compatible = "samsung,exynos5420-dw-mshc-smu";
 183                 interrupts = <0 75 0>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 reg = <0x12200000 0x2000>;
 187                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 188                 clock-names = "biu", "ciu";
 189                 fifo-depth = <0x40>;
 190                 status = "disabled";
 191         };
 192
 193         mmc_1: mmc@12210000 {
 194                 compatible = "samsung,exynos5420-dw-mshc-smu";
 195                 interrupts = <0 76 0>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 reg = <0x12210000 0x2000>;
 199                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 200                 clock-names = "biu", "ciu";
 201                 fifo-depth = <0x40>;
 202                 status = "disabled";
 203         };
 204
 205         mmc_2: mmc@12220000 {
 206                 compatible = "samsung,exynos5420-dw-mshc";
 207                 interrupts = <0 77 0>;
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 reg = <0x12220000 0x1000>;
 211                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 212                 clock-names = "biu", "ciu";
 213                 fifo-depth = <0x40>;
 214                 status = "disabled";
 215         };
 216
 217         mct: mct@101C0000 {
 218                 compatible = "samsung,exynos4210-mct";
 219                 reg = <0x101C0000 0x800>;
 220                 interrupt-controller;
 221                 #interrups-cells = <1>;
 222                 interrupt-parent = <&mct_map>;
 223                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 224                                 <8>, <9>, <10>, <11>;
 225                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 226                 clock-names = "fin_pll", "mct";
 227
 228                 mct_map: mct-map {
 229                         #interrupt-cells = <1>;
 230                         #address-cells = <0>;
 231                         #size-cells = <0>;
 232                         interrupt-map = <0 &combiner 23 3>,
 233                                         <1 &combiner 23 4>,
 234                                         <2 &combiner 25 2>,
 235                                         <3 &combiner 25 3>,
 236                                         <4 &gic 0 120 0>,
 237                                         <5 &gic 0 121 0>,
 238                                         <6 &gic 0 122 0>,
 239                                         <7 &gic 0 123 0>,
 240                                         <8 &gic 0 128 0>,
 241                                         <9 &gic 0 129 0>,
 242                                         <10 &gic 0 130 0>,
 243                                         <11 &gic 0 131 0>;
 244                 };
 245         };
 246
 247         gsc_pd: power-domain@10044000 {
 248                 compatible = "samsung,exynos4210-pd";
 249                 reg = <0x10044000 0x20>;
 250         };
 251
 252         isp_pd: power-domain@10044020 {
 253                 compatible = "samsung,exynos4210-pd";
 254                 reg = <0x10044020 0x20>;
 255         };
 256
 257         mfc_pd: power-domain@10044060 {
 258                 compatible = "samsung,exynos4210-pd";
 259                 reg = <0x10044060 0x20>;
 260         };
 261
 262         disp_pd: power-domain@100440C0 {
 263                 compatible = "samsung,exynos4210-pd";
 264                 reg = <0x100440C0 0x20>;
 265         };
 266
 267         msc_pd: power-domain@10044120 {
 268                 compatible = "samsung,exynos4210-pd";
 269                 reg = <0x10044120 0x20>;
 270         };
 271
 272         pinctrl_0: pinctrl@13400000 {
 273                 compatible = "samsung,exynos5420-pinctrl";
 274                 reg = <0x13400000 0x1000>;
 275                 interrupts = <0 45 0>;
 276
 277                 wakeup-interrupt-controller {
 278                         compatible = "samsung,exynos4210-wakeup-eint";
 279                         interrupt-parent = <&gic>;
 280                         interrupts = <0 32 0>;
 281                 };
 282         };
 283
 284         pinctrl_1: pinctrl@13410000 {
 285                 compatible = "samsung,exynos5420-pinctrl";
 286                 reg = <0x13410000 0x1000>;
 287                 interrupts = <0 78 0>;
 288         };
 289
 290         pinctrl_2: pinctrl@14000000 {
 291                 compatible = "samsung,exynos5420-pinctrl";
 292                 reg = <0x14000000 0x1000>;
 293                 interrupts = <0 46 0>;
 294         };
 295
 296         pinctrl_3: pinctrl@14010000 {
 297                 compatible = "samsung,exynos5420-pinctrl";
 298                 reg = <0x14010000 0x1000>;
 299                 interrupts = <0 50 0>;
 300         };
 301
 302         pinctrl_4: pinctrl@03860000 {
 303                 compatible = "samsung,exynos5420-pinctrl";
 304                 reg = <0x03860000 0x1000>;
 305                 interrupts = <0 47 0>;
 306         };
 307
 308         rtc: rtc@101E0000 {
 309                 clocks = <&clock CLK_RTC>;
 310                 clock-names = "rtc";
 311                 status = "disabled";
 312         };
 313
 314         amba {
 315                 #address-cells = <1>;
 316                 #size-cells = <1>;
 317                 compatible = "arm,amba-bus";
 318                 interrupt-parent = <&gic>;
 319                 ranges;
 320
 321                 adma: adma@03880000 {
 322                         compatible = "arm,pl330", "arm,primecell";
 323                         reg = <0x03880000 0x1000>;
 324                         interrupts = <0 110 0>;
 325                         clocks = <&clock_audss EXYNOS_ADMA>;
 326                         clock-names = "apb_pclk";
 327                         #dma-cells = <1>;
 328                         #dma-channels = <6>;
 329                         #dma-requests = <16>;
 330                 };
 331
 332                 pdma0: pdma@121A0000 {
 333                         compatible = "arm,pl330", "arm,primecell";
 334                         reg = <0x121A0000 0x1000>;
 335                         interrupts = <0 34 0>;
 336                         clocks = <&clock CLK_PDMA0>;
 337                         clock-names = "apb_pclk";
 338                         #dma-cells = <1>;
 339                         #dma-channels = <8>;
 340                         #dma-requests = <32>;
 341                 };
 342
 343                 pdma1: pdma@121B0000 {
 344                         compatible = "arm,pl330", "arm,primecell";
 345                         reg = <0x121B0000 0x1000>;
 346                         interrupts = <0 35 0>;
 347                         clocks = <&clock CLK_PDMA1>;
 348                         clock-names = "apb_pclk";
 349                         #dma-cells = <1>;
 350                         #dma-channels = <8>;
 351                         #dma-requests = <32>;
 352                 };
 353
 354                 mdma0: mdma@10800000 {
 355                         compatible = "arm,pl330", "arm,primecell";
 356                         reg = <0x10800000 0x1000>;
 357                         interrupts = <0 33 0>;
 358                         clocks = <&clock CLK_MDMA0>;
 359                         clock-names = "apb_pclk";
 360                         #dma-cells = <1>;
 361                         #dma-channels = <8>;
 362                         #dma-requests = <1>;
 363                 };
 364
 365                 mdma1: mdma@11C10000 {
 366                         compatible = "arm,pl330", "arm,primecell";
 367                         reg = <0x11C10000 0x1000>;
 368                         interrupts = <0 124 0>;
 369                         clocks = <&clock CLK_MDMA1>;
 370                         clock-names = "apb_pclk";
 371                         #dma-cells = <1>;
 372                         #dma-channels = <8>;
 373                         #dma-requests = <1>;
 374                         /*
 375                          * MDMA1 can support both secure and non-secure
 376                          * AXI transactions. When this is enabled in the kernel
 377                          * for boards that run in secure mode, we are getting
 378                          * imprecise external aborts causing the kernel to oops.
 379                          */
 380                         status = "disabled";
 381                 };
 382         };
 383
 384         i2s0: i2s@03830000 {
 385                 compatible = "samsung,exynos5420-i2s";
 386                 reg = <0x03830000 0x100>;
 387                 dmas = <&adma 0
 388                         &adma 2
 389                         &adma 1>;
 390                 dma-names = "tx", "rx", "tx-sec";
 391                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 392                         <&clock_audss EXYNOS_I2S_BUS>,
 393                         <&clock_audss EXYNOS_SCLK_I2S>;
 394                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 395                 samsung,idma-addr = <0x03000000>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&i2s0_bus>;
 398                 status = "disabled";
 399         };
 400
 401         i2s1: i2s@12D60000 {
 402                 compatible = "samsung,exynos5420-i2s";
 403                 reg = <0x12D60000 0x100>;
 404                 dmas = <&pdma1 12
 405                         &pdma1 11>;
 406                 dma-names = "tx", "rx";
 407                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 408                 clock-names = "iis", "i2s_opclk0";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&i2s1_bus>;
 411                 status = "disabled";
 412         };
 413
 414         i2s2: i2s@12D70000 {
 415                 compatible = "samsung,exynos5420-i2s";
 416                 reg = <0x12D70000 0x100>;
 417                 dmas = <&pdma0 12
 418                         &pdma0 11>;
 419                 dma-names = "tx", "rx";
 420                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 421                 clock-names = "iis", "i2s_opclk0";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&i2s2_bus>;
 424                 status = "disabled";
 425         };
 426
 427         spi_0: spi@12d20000 {
 428                 compatible = "samsung,exynos4210-spi";
 429                 reg = <0x12d20000 0x100>;
 430                 interrupts = <0 68 0>;
 431                 dmas = <&pdma0 5
 432                         &pdma0 4>;
 433                 dma-names = "tx", "rx";
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&spi0_bus>;
 438                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 439                 clock-names = "spi", "spi_busclk0";
 440                 status = "disabled";
 441         };
 442
 443         spi_1: spi@12d30000 {
 444                 compatible = "samsung,exynos4210-spi";
 445                 reg = <0x12d30000 0x100>;
 446                 interrupts = <0 69 0>;
 447                 dmas = <&pdma1 5
 448                         &pdma1 4>;
 449                 dma-names = "tx", "rx";
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&spi1_bus>;
 454                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 455                 clock-names = "spi", "spi_busclk0";
 456                 status = "disabled";
 457         };
 458
 459         spi_2: spi@12d40000 {
 460                 compatible = "samsung,exynos4210-spi";
 461                 reg = <0x12d40000 0x100>;
 462                 interrupts = <0 70 0>;
 463                 dmas = <&pdma0 7
 464                         &pdma0 6>;
 465                 dma-names = "tx", "rx";
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&spi2_bus>;
 470                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 471                 clock-names = "spi", "spi_busclk0";
 472                 status = "disabled";
 473         };
 474
 475         uart_0: serial@12C00000 {
 476                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 477                 clock-names = "uart", "clk_uart_baud0";
 478         };
 479
 480         uart_1: serial@12C10000 {
 481                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 482                 clock-names = "uart", "clk_uart_baud0";
 483         };
 484
 485         uart_2: serial@12C20000 {
 486                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 487                 clock-names = "uart", "clk_uart_baud0";
 488         };
 489
 490         uart_3: serial@12C30000 {
 491                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 492                 clock-names = "uart", "clk_uart_baud0";
 493         };
 494
 495         pwm: pwm@12dd0000 {
 496                 compatible = "samsung,exynos4210-pwm";
 497                 reg = <0x12dd0000 0x100>;
 498                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 499                 #pwm-cells = <3>;
 500                 clocks = <&clock CLK_PWM>;
 501                 clock-names = "timers";
 502         };
 503
 504         dp_phy: video-phy@10040728 {
 505                 compatible = "samsung,exynos5250-dp-video-phy";
 506                 reg = <0x10040728 4>;
 507                 #phy-cells = <0>;
 508         };
 509
 510         dp: dp-controller@145B0000 {
 511                 clocks = <&clock CLK_DP1>;
 512                 clock-names = "dp";
 513                 phys = <&dp_phy>;
 514                 phy-names = "dp";
 515         };
 516
 517         fimd: fimd@14400000 {
 518                 samsung,power-domain = <&disp_pd>;
 519                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 520                 clock-names = "sclk_fimd", "fimd";
 521         };
 522
 523         adc: adc@12D10000 {
 524                 compatible = "samsung,exynos-adc-v2";
 525                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 526                 interrupts = <0 106 0>;
 527                 clocks = <&clock CLK_TSADC>;
 528                 clock-names = "adc";
 529                 #io-channel-cells = <1>;
 530                 io-channel-ranges;
 531                 status = "disabled";
 532         };
 533
 534         i2c_0: i2c@12C60000 {
 535                 compatible = "samsung,s3c2440-i2c";
 536                 reg = <0x12C60000 0x100>;
 537                 interrupts = <0 56 0>;
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 clocks = <&clock CLK_I2C0>;
 541                 clock-names = "i2c";
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&i2c0_bus>;
 544                 status = "disabled";
 545         };
 546
 547         i2c_1: i2c@12C70000 {
 548                 compatible = "samsung,s3c2440-i2c";
 549                 reg = <0x12C70000 0x100>;
 550                 interrupts = <0 57 0>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 clocks = <&clock CLK_I2C1>;
 554                 clock-names = "i2c";
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&i2c1_bus>;
 557                 status = "disabled";
 558         };
 559
 560         i2c_2: i2c@12C80000 {
 561                 compatible = "samsung,s3c2440-i2c";
 562                 reg = <0x12C80000 0x100>;
 563                 interrupts = <0 58 0>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 clocks = <&clock CLK_I2C2>;
 567                 clock-names = "i2c";
 568                 pinctrl-names = "default";
 569                 pinctrl-0 = <&i2c2_bus>;
 570                 status = "disabled";
 571         };
 572
 573         i2c_3: i2c@12C90000 {
 574                 compatible = "samsung,s3c2440-i2c";
 575                 reg = <0x12C90000 0x100>;
 576                 interrupts = <0 59 0>;
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 clocks = <&clock CLK_I2C3>;
 580                 clock-names = "i2c";
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&i2c3_bus>;
 583                 status = "disabled";
 584         };
 585
 586         hsi2c_4: i2c@12CA0000 {
 587                 compatible = "samsung,exynos5-hsi2c";
 588                 reg = <0x12CA0000 0x1000>;
 589                 interrupts = <0 60 0>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&i2c4_hs_bus>;
 594                 clocks = <&clock CLK_USI0>;
 595                 clock-names = "hsi2c";
 596                 status = "disabled";
 597         };
 598
 599         hsi2c_5: i2c@12CB0000 {
 600                 compatible = "samsung,exynos5-hsi2c";
 601                 reg = <0x12CB0000 0x1000>;
 602                 interrupts = <0 61 0>;
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&i2c5_hs_bus>;
 607                 clocks = <&clock CLK_USI1>;
 608                 clock-names = "hsi2c";
 609                 status = "disabled";
 610         };
 611
 612         hsi2c_6: i2c@12CC0000 {
 613                 compatible = "samsung,exynos5-hsi2c";
 614                 reg = <0x12CC0000 0x1000>;
 615                 interrupts = <0 62 0>;
 616                 #address-cells = <1>;
 617                 #size-cells = <0>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&i2c6_hs_bus>;
 620                 clocks = <&clock CLK_USI2>;
 621                 clock-names = "hsi2c";
 622                 status = "disabled";
 623         };
 624
 625         hsi2c_7: i2c@12CD0000 {
 626                 compatible = "samsung,exynos5-hsi2c";
 627                 reg = <0x12CD0000 0x1000>;
 628                 interrupts = <0 63 0>;
 629                 #address-cells = <1>;
 630                 #size-cells = <0>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&i2c7_hs_bus>;
 633                 clocks = <&clock CLK_USI3>;
 634                 clock-names = "hsi2c";
 635                 status = "disabled";
 636         };
 637
 638         hsi2c_8: i2c@12E00000 {
 639                 compatible = "samsung,exynos5-hsi2c";
 640                 reg = <0x12E00000 0x1000>;
 641                 interrupts = <0 87 0>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&i2c8_hs_bus>;
 646                 clocks = <&clock CLK_USI4>;
 647                 clock-names = "hsi2c";
 648                 status = "disabled";
 649         };
 650
 651         hsi2c_9: i2c@12E10000 {
 652                 compatible = "samsung,exynos5-hsi2c";
 653                 reg = <0x12E10000 0x1000>;
 654                 interrupts = <0 88 0>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&i2c9_hs_bus>;
 659                 clocks = <&clock CLK_USI5>;
 660                 clock-names = "hsi2c";
 661                 status = "disabled";
 662         };
 663
 664         hsi2c_10: i2c@12E20000 {
 665                 compatible = "samsung,exynos5-hsi2c";
 666                 reg = <0x12E20000 0x1000>;
 667                 interrupts = <0 203 0>;
 668                 #address-cells = <1>;
 669                 #size-cells = <0>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&i2c10_hs_bus>;
 672                 clocks = <&clock CLK_USI6>;
 673                 clock-names = "hsi2c";
 674                 status = "disabled";
 675         };
 676
 677         hdmi: hdmi@14530000 {
 678                 compatible = "samsung,exynos4212-hdmi";
 679                 reg = <0x14530000 0x70000>;
 680                 interrupts = <0 95 0>;
 681                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 682                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 683                          <&clock CLK_MOUT_HDMI>;
 684                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 685                         "sclk_hdmiphy", "mout_hdmi";
 686                 status = "disabled";
 687         };
 688
 689         mixer: mixer@14450000 {
 690                 compatible = "samsung,exynos5420-mixer";
 691                 reg = <0x14450000 0x10000>;
 692                 interrupts = <0 94 0>;
 693                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 694                 clock-names = "mixer", "sclk_hdmi";
 695         };
 696
 697         gsc_0: video-scaler@13e00000 {
 698                 compatible = "samsung,exynos5-gsc";
 699                 reg = <0x13e00000 0x1000>;
 700                 interrupts = <0 85 0>;
 701                 clocks = <&clock CLK_GSCL0>;
 702                 clock-names = "gscl";
 703                 samsung,power-domain = <&gsc_pd>;
 704         };
 705
 706         gsc_1: video-scaler@13e10000 {
 707                 compatible = "samsung,exynos5-gsc";
 708                 reg = <0x13e10000 0x1000>;
 709                 interrupts = <0 86 0>;
 710                 clocks = <&clock CLK_GSCL1>;
 711                 clock-names = "gscl";
 712                 samsung,power-domain = <&gsc_pd>;
 713         };
 714
 715         pmu_system_controller: system-controller@10040000 {
 716                 compatible = "samsung,exynos5420-pmu", "syscon";
 717                 reg = <0x10040000 0x5000>;
 718         };
 719
 720         tmu_cpu0: tmu@10060000 {
 721                 compatible = "samsung,exynos5420-tmu";
 722                 reg = <0x10060000 0x100>;
 723                 interrupts = <0 65 0>;
 724                 clocks = <&clock CLK_TMU>;
 725                 clock-names = "tmu_apbif";
 726         };
 727
 728         tmu_cpu1: tmu@10064000 {
 729                 compatible = "samsung,exynos5420-tmu";
 730                 reg = <0x10064000 0x100>;
 731                 interrupts = <0 183 0>;
 732                 clocks = <&clock CLK_TMU>;
 733                 clock-names = "tmu_apbif";
 734         };
 735
 736         tmu_cpu2: tmu@10068000 {
 737                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 738                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 739                 interrupts = <0 184 0>;
 740                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 741                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 742         };
 743
 744         tmu_cpu3: tmu@1006c000 {
 745                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 746                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 747                 interrupts = <0 185 0>;
 748                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 749                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 750         };
 751
 752         tmu_gpu: tmu@100a0000 {
 753                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 754                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 755                 interrupts = <0 215 0>;
 756                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 757                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 758         };
 759
 760         watchdog: watchdog@101D0000 {
 761                 compatible = "samsung,exynos5420-wdt";
 762                 reg = <0x101D0000 0x100>;
 763                 interrupts = <0 42 0>;
 764                 clocks = <&clock CLK_WDT>;
 765                 clock-names = "watchdog";
 766                 samsung,syscon-phandle = <&pmu_system_controller>;
 767         };
 768
 769         sss: sss@10830000 {
 770                 compatible = "samsung,exynos4210-secss";
 771                 reg = <0x10830000 0x10000>;
 772                 interrupts = <0 112 0>;
 773                 clocks = <&clock 471>;
 774                 clock-names = "secss";
 775         };
 776 };