arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420", "samsung,exynos5";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x0>;
  60                         clock-frequency = <1800000000>;
  61                 };
  62
  63                 cpu1: cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x1>;
  67                         clock-frequency = <1800000000>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a15";
  73                         reg = <0x2>;
  74                         clock-frequency = <1800000000>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a15";
  80                         reg = <0x3>;
  81                         clock-frequency = <1800000000>;
  82                 };
  83
  84                 cpu4: cpu@100 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0x100>;
  88                         clock-frequency = <1000000000>;
  89                 };
  90
  91                 cpu5: cpu@101 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a7";
  94                         reg = <0x101>;
  95                         clock-frequency = <1000000000>;
  96                 };
  97
  98                 cpu6: cpu@102 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x102>;
 102                         clock-frequency = <1000000000>;
 103                 };
 104
 105                 cpu7: cpu@103 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a7";
 108                         reg = <0x103>;
 109                         clock-frequency = <1000000000>;
 110                 };
 111         };
 112
 113         clock: clock-controller@10010000 {
 114                 compatible = "samsung,exynos5420-clock";
 115                 reg = <0x10010000 0x30000>;
 116                 #clock-cells = <1>;
 117         };
 118
 119         clock_audss: audss-clock-controller@3810000 {
 120                 compatible = "samsung,exynos5420-audss-clock";
 121                 reg = <0x03810000 0x0C>;
 122                 #clock-cells = <1>;
 123                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 124                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 125                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 126         };
 127
 128         codec@11000000 {
 129                 compatible = "samsung,mfc-v7";
 130                 reg = <0x11000000 0x10000>;
 131                 interrupts = <0 96 0>;
 132                 clocks = <&clock CLK_MFC>;
 133                 clock-names = "mfc";
 134         };
 135
 136         mmc_0: mmc@12200000 {
 137                 compatible = "samsung,exynos5420-dw-mshc-smu";
 138                 interrupts = <0 75 0>;
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 reg = <0x12200000 0x2000>;
 142                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 143                 clock-names = "biu", "ciu";
 144                 fifo-depth = <0x40>;
 145                 status = "disabled";
 146         };
 147
 148         mmc_1: mmc@12210000 {
 149                 compatible = "samsung,exynos5420-dw-mshc-smu";
 150                 interrupts = <0 76 0>;
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153                 reg = <0x12210000 0x2000>;
 154                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 155                 clock-names = "biu", "ciu";
 156                 fifo-depth = <0x40>;
 157                 status = "disabled";
 158         };
 159
 160         mmc_2: mmc@12220000 {
 161                 compatible = "samsung,exynos5420-dw-mshc";
 162                 interrupts = <0 77 0>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 reg = <0x12220000 0x1000>;
 166                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 167                 clock-names = "biu", "ciu";
 168                 fifo-depth = <0x40>;
 169                 status = "disabled";
 170         };
 171
 172         mct@101C0000 {
 173                 compatible = "samsung,exynos4210-mct";
 174                 reg = <0x101C0000 0x800>;
 175                 interrupt-controller;
 176                 #interrups-cells = <1>;
 177                 interrupt-parent = <&mct_map>;
 178                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 179                                 <8>, <9>, <10>, <11>;
 180                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 181                 clock-names = "fin_pll", "mct";
 182
 183                 mct_map: mct-map {
 184                         #interrupt-cells = <1>;
 185                         #address-cells = <0>;
 186                         #size-cells = <0>;
 187                         interrupt-map = <0 &combiner 23 3>,
 188                                         <1 &combiner 23 4>,
 189                                         <2 &combiner 25 2>,
 190                                         <3 &combiner 25 3>,
 191                                         <4 &gic 0 120 0>,
 192                                         <5 &gic 0 121 0>,
 193                                         <6 &gic 0 122 0>,
 194                                         <7 &gic 0 123 0>,
 195                                         <8 &gic 0 128 0>,
 196                                         <9 &gic 0 129 0>,
 197                                         <10 &gic 0 130 0>,
 198                                         <11 &gic 0 131 0>;
 199                 };
 200         };
 201
 202         gsc_pd: power-domain@10044000 {
 203                 compatible = "samsung,exynos4210-pd";
 204                 reg = <0x10044000 0x20>;
 205         };
 206
 207         isp_pd: power-domain@10044020 {
 208                 compatible = "samsung,exynos4210-pd";
 209                 reg = <0x10044020 0x20>;
 210         };
 211
 212         mfc_pd: power-domain@10044060 {
 213                 compatible = "samsung,exynos4210-pd";
 214                 reg = <0x10044060 0x20>;
 215         };
 216
 217         disp_pd: power-domain@100440C0 {
 218                 compatible = "samsung,exynos4210-pd";
 219                 reg = <0x100440C0 0x20>;
 220         };
 221
 222         msc_pd: power-domain@10044120 {
 223                 compatible = "samsung,exynos4210-pd";
 224                 reg = <0x10044120 0x20>;
 225         };
 226
 227         pinctrl_0: pinctrl@13400000 {
 228                 compatible = "samsung,exynos5420-pinctrl";
 229                 reg = <0x13400000 0x1000>;
 230                 interrupts = <0 45 0>;
 231
 232                 wakeup-interrupt-controller {
 233                         compatible = "samsung,exynos4210-wakeup-eint";
 234                         interrupt-parent = <&gic>;
 235                         interrupts = <0 32 0>;
 236                 };
 237         };
 238
 239         pinctrl_1: pinctrl@13410000 {
 240                 compatible = "samsung,exynos5420-pinctrl";
 241                 reg = <0x13410000 0x1000>;
 242                 interrupts = <0 78 0>;
 243         };
 244
 245         pinctrl_2: pinctrl@14000000 {
 246                 compatible = "samsung,exynos5420-pinctrl";
 247                 reg = <0x14000000 0x1000>;
 248                 interrupts = <0 46 0>;
 249         };
 250
 251         pinctrl_3: pinctrl@14010000 {
 252                 compatible = "samsung,exynos5420-pinctrl";
 253                 reg = <0x14010000 0x1000>;
 254                 interrupts = <0 50 0>;
 255         };
 256
 257         pinctrl_4: pinctrl@03860000 {
 258                 compatible = "samsung,exynos5420-pinctrl";
 259                 reg = <0x03860000 0x1000>;
 260                 interrupts = <0 47 0>;
 261         };
 262
 263         rtc@101E0000 {
 264                 clocks = <&clock CLK_RTC>;
 265                 clock-names = "rtc";
 266                 status = "disabled";
 267         };
 268
 269         amba {
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272                 compatible = "arm,amba-bus";
 273                 interrupt-parent = <&gic>;
 274                 ranges;
 275
 276                 adma: adma@03880000 {
 277                         compatible = "arm,pl330", "arm,primecell";
 278                         reg = <0x03880000 0x1000>;
 279                         interrupts = <0 110 0>;
 280                         clocks = <&clock_audss EXYNOS_ADMA>;
 281                         clock-names = "apb_pclk";
 282                         #dma-cells = <1>;
 283                         #dma-channels = <6>;
 284                         #dma-requests = <16>;
 285                 };
 286
 287                 pdma0: pdma@121A0000 {
 288                         compatible = "arm,pl330", "arm,primecell";
 289                         reg = <0x121A0000 0x1000>;
 290                         interrupts = <0 34 0>;
 291                         clocks = <&clock CLK_PDMA0>;
 292                         clock-names = "apb_pclk";
 293                         #dma-cells = <1>;
 294                         #dma-channels = <8>;
 295                         #dma-requests = <32>;
 296                 };
 297
 298                 pdma1: pdma@121B0000 {
 299                         compatible = "arm,pl330", "arm,primecell";
 300                         reg = <0x121B0000 0x1000>;
 301                         interrupts = <0 35 0>;
 302                         clocks = <&clock CLK_PDMA1>;
 303                         clock-names = "apb_pclk";
 304                         #dma-cells = <1>;
 305                         #dma-channels = <8>;
 306                         #dma-requests = <32>;
 307                 };
 308
 309                 mdma0: mdma@10800000 {
 310                         compatible = "arm,pl330", "arm,primecell";
 311                         reg = <0x10800000 0x1000>;
 312                         interrupts = <0 33 0>;
 313                         clocks = <&clock CLK_MDMA0>;
 314                         clock-names = "apb_pclk";
 315                         #dma-cells = <1>;
 316                         #dma-channels = <8>;
 317                         #dma-requests = <1>;
 318                 };
 319
 320                 mdma1: mdma@11C10000 {
 321                         compatible = "arm,pl330", "arm,primecell";
 322                         reg = <0x11C10000 0x1000>;
 323                         interrupts = <0 124 0>;
 324                         clocks = <&clock CLK_MDMA1>;
 325                         clock-names = "apb_pclk";
 326                         #dma-cells = <1>;
 327                         #dma-channels = <8>;
 328                         #dma-requests = <1>;
 329                         /*
 330                          * MDMA1 can support both secure and non-secure
 331                          * AXI transactions. When this is enabled in the kernel
 332                          * for boards that run in secure mode, we are getting
 333                          * imprecise external aborts causing the kernel to oops.
 334                          */
 335                         status = "disabled";
 336                 };
 337         };
 338
 339         i2s0: i2s@03830000 {
 340                 compatible = "samsung,exynos5420-i2s";
 341                 reg = <0x03830000 0x100>;
 342                 dmas = <&adma 0
 343                         &adma 2
 344                         &adma 1>;
 345                 dma-names = "tx", "rx", "tx-sec";
 346                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 347                         <&clock_audss EXYNOS_I2S_BUS>,
 348                         <&clock_audss EXYNOS_SCLK_I2S>;
 349                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 350                 samsung,idma-addr = <0x03000000>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2s0_bus>;
 353                 status = "disabled";
 354         };
 355
 356         i2s1: i2s@12D60000 {
 357                 compatible = "samsung,exynos5420-i2s";
 358                 reg = <0x12D60000 0x100>;
 359                 dmas = <&pdma1 12
 360                         &pdma1 11>;
 361                 dma-names = "tx", "rx";
 362                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 363                 clock-names = "iis", "i2s_opclk0";
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2s1_bus>;
 366                 status = "disabled";
 367         };
 368
 369         i2s2: i2s@12D70000 {
 370                 compatible = "samsung,exynos5420-i2s";
 371                 reg = <0x12D70000 0x100>;
 372                 dmas = <&pdma0 12
 373                         &pdma0 11>;
 374                 dma-names = "tx", "rx";
 375                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 376                 clock-names = "iis", "i2s_opclk0";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2s2_bus>;
 379                 status = "disabled";
 380         };
 381
 382         spi_0: spi@12d20000 {
 383                 compatible = "samsung,exynos4210-spi";
 384                 reg = <0x12d20000 0x100>;
 385                 interrupts = <0 68 0>;
 386                 dmas = <&pdma0 5
 387                         &pdma0 4>;
 388                 dma-names = "tx", "rx";
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&spi0_bus>;
 393                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 394                 clock-names = "spi", "spi_busclk0";
 395                 status = "disabled";
 396         };
 397
 398         spi_1: spi@12d30000 {
 399                 compatible = "samsung,exynos4210-spi";
 400                 reg = <0x12d30000 0x100>;
 401                 interrupts = <0 69 0>;
 402                 dmas = <&pdma1 5
 403                         &pdma1 4>;
 404                 dma-names = "tx", "rx";
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&spi1_bus>;
 409                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 410                 clock-names = "spi", "spi_busclk0";
 411                 status = "disabled";
 412         };
 413
 414         spi_2: spi@12d40000 {
 415                 compatible = "samsung,exynos4210-spi";
 416                 reg = <0x12d40000 0x100>;
 417                 interrupts = <0 70 0>;
 418                 dmas = <&pdma0 7
 419                         &pdma0 6>;
 420                 dma-names = "tx", "rx";
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&spi2_bus>;
 425                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 426                 clock-names = "spi", "spi_busclk0";
 427                 status = "disabled";
 428         };
 429
 430         serial@12C00000 {
 431                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 432                 clock-names = "uart", "clk_uart_baud0";
 433         };
 434
 435         serial@12C10000 {
 436                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 437                 clock-names = "uart", "clk_uart_baud0";
 438         };
 439
 440         serial@12C20000 {
 441                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 442                 clock-names = "uart", "clk_uart_baud0";
 443         };
 444
 445         serial@12C30000 {
 446                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 447                 clock-names = "uart", "clk_uart_baud0";
 448         };
 449
 450         pwm: pwm@12dd0000 {
 451                 compatible = "samsung,exynos4210-pwm";
 452                 reg = <0x12dd0000 0x100>;
 453                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 454                 #pwm-cells = <3>;
 455                 clocks = <&clock CLK_PWM>;
 456                 clock-names = "timers";
 457         };
 458
 459         dp_phy: video-phy@10040728 {
 460                 compatible = "samsung,exynos5250-dp-video-phy";
 461                 reg = <0x10040728 4>;
 462                 #phy-cells = <0>;
 463         };
 464
 465         dp-controller@145B0000 {
 466                 clocks = <&clock CLK_DP1>;
 467                 clock-names = "dp";
 468                 phys = <&dp_phy>;
 469                 phy-names = "dp";
 470         };
 471
 472         fimd@14400000 {
 473                 samsung,power-domain = <&disp_pd>;
 474                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 475                 clock-names = "sclk_fimd", "fimd";
 476         };
 477
 478         adc: adc@12D10000 {
 479                 compatible = "samsung,exynos-adc-v2";
 480                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 481                 interrupts = <0 106 0>;
 482                 clocks = <&clock CLK_TSADC>;
 483                 clock-names = "adc";
 484                 #io-channel-cells = <1>;
 485                 io-channel-ranges;
 486                 status = "disabled";
 487         };
 488
 489         i2c_0: i2c@12C60000 {
 490                 compatible = "samsung,s3c2440-i2c";
 491                 reg = <0x12C60000 0x100>;
 492                 interrupts = <0 56 0>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 clocks = <&clock CLK_I2C0>;
 496                 clock-names = "i2c";
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&i2c0_bus>;
 499                 status = "disabled";
 500         };
 501
 502         i2c_1: i2c@12C70000 {
 503                 compatible = "samsung,s3c2440-i2c";
 504                 reg = <0x12C70000 0x100>;
 505                 interrupts = <0 57 0>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 clocks = <&clock CLK_I2C1>;
 509                 clock-names = "i2c";
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&i2c1_bus>;
 512                 status = "disabled";
 513         };
 514
 515         i2c_2: i2c@12C80000 {
 516                 compatible = "samsung,s3c2440-i2c";
 517                 reg = <0x12C80000 0x100>;
 518                 interrupts = <0 58 0>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 clocks = <&clock CLK_I2C2>;
 522                 clock-names = "i2c";
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&i2c2_bus>;
 525                 status = "disabled";
 526         };
 527
 528         i2c_3: i2c@12C90000 {
 529                 compatible = "samsung,s3c2440-i2c";
 530                 reg = <0x12C90000 0x100>;
 531                 interrupts = <0 59 0>;
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 clocks = <&clock CLK_I2C3>;
 535                 clock-names = "i2c";
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&i2c3_bus>;
 538                 status = "disabled";
 539         };
 540
 541         hsi2c_4: i2c@12CA0000 {
 542                 compatible = "samsung,exynos5-hsi2c";
 543                 reg = <0x12CA0000 0x1000>;
 544                 interrupts = <0 60 0>;
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&i2c4_hs_bus>;
 549                 clocks = <&clock CLK_I2C4>;
 550                 clock-names = "hsi2c";
 551                 status = "disabled";
 552         };
 553
 554         hsi2c_5: i2c@12CB0000 {
 555                 compatible = "samsung,exynos5-hsi2c";
 556                 reg = <0x12CB0000 0x1000>;
 557                 interrupts = <0 61 0>;
 558                 #address-cells = <1>;
 559                 #size-cells = <0>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2c5_hs_bus>;
 562                 clocks = <&clock CLK_I2C5>;
 563                 clock-names = "hsi2c";
 564                 status = "disabled";
 565         };
 566
 567         hsi2c_6: i2c@12CC0000 {
 568                 compatible = "samsung,exynos5-hsi2c";
 569                 reg = <0x12CC0000 0x1000>;
 570                 interrupts = <0 62 0>;
 571                 #address-cells = <1>;
 572                 #size-cells = <0>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&i2c6_hs_bus>;
 575                 clocks = <&clock CLK_I2C6>;
 576                 clock-names = "hsi2c";
 577                 status = "disabled";
 578         };
 579
 580         hsi2c_7: i2c@12CD0000 {
 581                 compatible = "samsung,exynos5-hsi2c";
 582                 reg = <0x12CD0000 0x1000>;
 583                 interrupts = <0 63 0>;
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&i2c7_hs_bus>;
 588                 clocks = <&clock CLK_I2C7>;
 589                 clock-names = "hsi2c";
 590                 status = "disabled";
 591         };
 592
 593         hsi2c_8: i2c@12E00000 {
 594                 compatible = "samsung,exynos5-hsi2c";
 595                 reg = <0x12E00000 0x1000>;
 596                 interrupts = <0 87 0>;
 597                 #address-cells = <1>;
 598                 #size-cells = <0>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&i2c8_hs_bus>;
 601                 clocks = <&clock CLK_I2C8>;
 602                 clock-names = "hsi2c";
 603                 status = "disabled";
 604         };
 605
 606         hsi2c_9: i2c@12E10000 {
 607                 compatible = "samsung,exynos5-hsi2c";
 608                 reg = <0x12E10000 0x1000>;
 609                 interrupts = <0 88 0>;
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 pinctrl-names = "default";
 613                 pinctrl-0 = <&i2c9_hs_bus>;
 614                 clocks = <&clock CLK_I2C9>;
 615                 clock-names = "hsi2c";
 616                 status = "disabled";
 617         };
 618
 619         hsi2c_10: i2c@12E20000 {
 620                 compatible = "samsung,exynos5-hsi2c";
 621                 reg = <0x12E20000 0x1000>;
 622                 interrupts = <0 203 0>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&i2c10_hs_bus>;
 627                 clocks = <&clock CLK_I2C10>;
 628                 clock-names = "hsi2c";
 629                 status = "disabled";
 630         };
 631
 632         hdmi@14530000 {
 633                 compatible = "samsung,exynos4212-hdmi";
 634                 reg = <0x14530000 0x70000>;
 635                 interrupts = <0 95 0>;
 636                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 637                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 638                          <&clock CLK_MOUT_HDMI>;
 639                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 640                         "sclk_hdmiphy", "mout_hdmi";
 641                 status = "disabled";
 642         };
 643
 644         mixer@14450000 {
 645                 compatible = "samsung,exynos5420-mixer";
 646                 reg = <0x14450000 0x10000>;
 647                 interrupts = <0 94 0>;
 648                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 649                 clock-names = "mixer", "sclk_hdmi";
 650         };
 651
 652         gsc_0: video-scaler@13e00000 {
 653                 compatible = "samsung,exynos5-gsc";
 654                 reg = <0x13e00000 0x1000>;
 655                 interrupts = <0 85 0>;
 656                 clocks = <&clock CLK_GSCL0>;
 657                 clock-names = "gscl";
 658                 samsung,power-domain = <&gsc_pd>;
 659         };
 660
 661         gsc_1: video-scaler@13e10000 {
 662                 compatible = "samsung,exynos5-gsc";
 663                 reg = <0x13e10000 0x1000>;
 664                 interrupts = <0 86 0>;
 665                 clocks = <&clock CLK_GSCL1>;
 666                 clock-names = "gscl";
 667                 samsung,power-domain = <&gsc_pd>;
 668         };
 669
 670         pmu_system_controller: system-controller@10040000 {
 671                 compatible = "samsung,exynos5420-pmu", "syscon";
 672                 reg = <0x10040000 0x5000>;
 673         };
 674
 675         tmu_cpu0: tmu@10060000 {
 676                 compatible = "samsung,exynos5420-tmu";
 677                 reg = <0x10060000 0x100>;
 678                 interrupts = <0 65 0>;
 679                 clocks = <&clock CLK_TMU>;
 680                 clock-names = "tmu_apbif";
 681         };
 682
 683         tmu_cpu1: tmu@10064000 {
 684                 compatible = "samsung,exynos5420-tmu";
 685                 reg = <0x10064000 0x100>;
 686                 interrupts = <0 183 0>;
 687                 clocks = <&clock CLK_TMU>;
 688                 clock-names = "tmu_apbif";
 689         };
 690
 691         tmu_cpu2: tmu@10068000 {
 692                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 693                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 694                 interrupts = <0 184 0>;
 695                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 696                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 697         };
 698
 699         tmu_cpu3: tmu@1006c000 {
 700                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 701                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 702                 interrupts = <0 185 0>;
 703                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 704                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 705         };
 706
 707         tmu_gpu: tmu@100a0000 {
 708                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 709                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 710                 interrupts = <0 215 0>;
 711                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 712                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 713         };
 714
 715         watchdog@101D0000 {
 716                 compatible = "samsung,exynos5420-wdt";
 717                 reg = <0x101D0000 0x100>;
 718                 interrupts = <0 42 0>;
 719                 clocks = <&clock CLK_WDT>;
 720                 clock-names = "watchdog";
 721                 samsung,syscon-phandle = <&pmu_system_controller>;
 722         };
 723
 724         sss@10830000 {
 725                 compatible = "samsung,exynos4210-secss";
 726                 reg = <0x10830000 0x10000>;
 727                 interrupts = <0 112 0>;
 728                 clocks = <&clock 471>;
 729                 clock-names = "secss";
 730         };
 731 };