arch/arm/boot/dts/imx51-apf51dev.dts

   1 /*
   2  * Copyright 2013 Armadeus Systems - <support@armadeus.com>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /* APF51Dev is a docking board for the APF51 SOM */
  13 #include "imx51-apf51.dts"
  14
  15 / {
  16         model = "Armadeus Systems APF51Dev docking/development board";
  17         compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
  18
  19         display@di1 {
  20                 compatible = "fsl,imx-parallel-display";
  21                 crtcs = <&ipu 0>;
  22                 interface-pix-fmt = "bgr666";
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  25
  26                 display-timings {
  27                         lw700 {
  28                                 native-mode;
  29                                 clock-frequency = <33000033>;
  30                                 hactive = <800>;
  31                                 vactive = <480>;
  32                                 hback-porch = <96>;
  33                                 hfront-porch = <96>;
  34                                 vback-porch = <20>;
  35                                 vfront-porch = <21>;
  36                                 hsync-len = <64>;
  37                                 vsync-len = <4>;
  38                                 hsync-active = <1>;
  39                                 vsync-active = <1>;
  40                                 de-active = <1>;
  41                                 pixelclk-active = <0>;
  42                         };
  43                 };
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48
  49                 user-key {
  50                         label = "user";
  51                         gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
  52                         linux,code = <256>; /* BTN_0 */
  53                 };
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 user {
  60                         label = "Heartbeat";
  61                         gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  62                         linux,default-trigger = "heartbeat";
  63                 };
  64         };
  65 };
  66
  67 &ecspi1 {
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&pinctrl_ecspi1>;
  70         fsl,spi-num-chipselects = <2>;
  71         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
  72                    <&gpio4 25 GPIO_ACTIVE_HIGH>;
  73         status = "okay";
  74 };
  75
  76 &ecspi2 {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&pinctrl_ecspi2>;
  79         fsl,spi-num-chipselects = <2>;
  80         cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
  81                    <&gpio3 27 GPIO_ACTIVE_LOW>;
  82         status = "okay";
  83 };
  84
  85 &esdhc1 {
  86         pinctrl-names = "default";
  87         pinctrl-0 = <&pinctrl_esdhc1>;
  88         cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
  89         bus-width = <4>;
  90         status = "okay";
  91 };
  92
  93 &esdhc2 {
  94         pinctrl-names = "default";
  95         pinctrl-0 = <&pinctrl_esdhc2>;
  96         bus-width = <4>;
  97         non-removable;
  98         status = "okay";
  99 };
 100
 101 &i2c2 {
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_i2c2>;
 104         status = "okay";
 105 };
 106
 107 &iomuxc {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_hog>;
 110
 111         imx51-apf51dev {
 112                 pinctrl_hog: hoggrp {
 113                         fsl,pins = <
 114                                 MX51_PAD_EIM_EB2__GPIO2_22   0x0C5
 115                                 MX51_PAD_EIM_EB3__GPIO2_23   0x0C5
 116                                 MX51_PAD_EIM_CS4__GPIO2_29   0x100
 117                                 MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
 118                                 MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
 119                                 MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
 120                                 MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
 121                                 MX51_PAD_GPIO1_2__GPIO1_2    0x0C5
 122                                 MX51_PAD_GPIO1_3__GPIO1_3    0x0C5
 123                         >;
 124                 };
 125
 126                 pinctrl_ecspi1: ecspi1grp {
 127                         fsl,pins = <
 128                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 129                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 130                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 131                         >;
 132                 };
 133
 134                 pinctrl_ecspi2: ecspi2grp {
 135                         fsl,pins = <
 136                                 MX51_PAD_NANDF_RB3__ECSPI2_MISO         0x185
 137                                 MX51_PAD_NANDF_D15__ECSPI2_MOSI         0x185
 138                                 MX51_PAD_NANDF_RB2__ECSPI2_SCLK         0x185
 139                         >;
 140                 };
 141
 142                 pinctrl_esdhc1: esdhc1grp {
 143                         fsl,pins = <
 144                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 145                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
 146                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
 147                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
 148                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
 149                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
 150                         >;
 151                 };
 152
 153                 pinctrl_esdhc2: esdhc2grp {
 154                         fsl,pins = <
 155                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 156                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 157                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 158                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 159                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 160                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 161                         >;
 162                 };
 163
 164                 pinctrl_i2c2: i2c2grp {
 165                         fsl,pins = <
 166                                 MX51_PAD_EIM_D27__I2C2_SCL              0x400001ed
 167                                 MX51_PAD_EIM_D24__I2C2_SDA              0x400001ed
 168                         >;
 169                 };
 170
 171                 pinctrl_ipu_disp1: ipudisp1grp {
 172                         fsl,pins = <
 173                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
 174                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
 175                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
 176                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
 177                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
 178                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
 179                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
 180                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
 181                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
 182                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
 183                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
 184                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
 185                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
 186                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
 187                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
 188                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
 189                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
 190                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
 191                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
 192                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
 193                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
 194                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
 195                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
 196                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
 197                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
 198                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
 199                         >;
 200                 };
 201         };
 202 };