arch/arm/boot/dts/imx53-m53evk.dts

   1 /*
   2  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx53.dtsi"
  14
  15 / {
  16         model = "DENX M53EVK";
  17         compatible = "denx,imx53-m53evk", "fsl,imx53";
  18
  19         memory {
  20                 reg = <0x70000000 0x20000000>,
  21                       <0xb0000000 0x20000000>;
  22         };
  23
  24         display1: display@di1 {
  25                 compatible = "fsl,imx-parallel-display";
  26                 interface-pix-fmt = "bgr666";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  29
  30                 display-timings {
  31                         800x480p60 {
  32                                 native-mode;
  33                                 clock-frequency = <31500000>;
  34                                 hactive = <800>;
  35                                 vactive = <480>;
  36                                 hfront-porch = <40>;
  37                                 hback-porch = <88>;
  38                                 hsync-len = <128>;
  39                                 vback-porch = <33>;
  40                                 vfront-porch = <9>;
  41                                 vsync-len = <3>;
  42                                 vsync-active = <1>;
  43                         };
  44                 };
  45
  46                 port {
  47                         display1_in: endpoint {
  48                                 remote-endpoint = <&ipu_di1_disp1>;
  49                         };
  50                 };
  51         };
  52
  53         backlight {
  54                 compatible = "pwm-backlight";
  55                 pwms = <&pwm1 0 3000>;
  56                 brightness-levels = <0 4 8 16 32 64 128 255>;
  57                 default-brightness-level = <6>;
  58                 power-supply = <&reg_backlight>;
  59         };
  60
  61         leds {
  62                 compatible = "gpio-leds";
  63                 pinctrl-names = "default";
  64                 pinctrl-0 = <&led_pin_gpio>;
  65
  66                 user1 {
  67                         label = "user1";
  68                         gpios = <&gpio2 8 0>;
  69                         linux,default-trigger = "heartbeat";
  70                 };
  71
  72                 user2 {
  73                         label = "user2";
  74                         gpios = <&gpio2 9 0>;
  75                         linux,default-trigger = "heartbeat";
  76                 };
  77         };
  78
  79         regulators {
  80                 compatible = "simple-bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 reg_3p2v: regulator@0 {
  85                         compatible = "regulator-fixed";
  86                         reg = <0>;
  87                         regulator-name = "3P2V";
  88                         regulator-min-microvolt = <3200000>;
  89                         regulator-max-microvolt = <3200000>;
  90                         regulator-always-on;
  91                 };
  92
  93
  94                 reg_backlight: regulator@1 {
  95                         compatible = "regulator-fixed";
  96                         reg = <1>;
  97                         regulator-name = "lcd-supply";
  98                         regulator-min-microvolt = <3200000>;
  99                         regulator-max-microvolt = <3200000>;
 100                         regulator-always-on;
 101                 };
 102
 103                 reg_usbh1_vbus: regulator@3 {
 104                         compatible = "regulator-fixed";
 105                         reg = <3>;
 106                         regulator-name = "vbus";
 107                         regulator-min-microvolt = <5000000>;
 108                         regulator-max-microvolt = <5000000>;
 109                         gpio = <&gpio1 2 0>;
 110                 };
 111         };
 112
 113         sound {
 114                 compatible = "fsl,imx53-m53evk-sgtl5000",
 115                              "fsl,imx-audio-sgtl5000";
 116                 model = "imx53-m53evk-sgtl5000";
 117                 ssi-controller = <&ssi2>;
 118                 audio-codec = <&sgtl5000>;
 119                 audio-routing =
 120                         "MIC_IN", "Mic Jack",
 121                         "Mic Jack", "Mic Bias",
 122                         "LINE_IN", "Line In Jack",
 123                         "Headphone Jack", "HP_OUT",
 124                         "Ext Spk", "LINE_OUT";
 125                 mux-int-port = <2>;
 126                 mux-ext-port = <4>;
 127         };
 128 };
 129
 130 &audmux {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_audmux>;
 133         status = "okay";
 134 };
 135
 136 &can1 {
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&pinctrl_can1>;
 139         status = "okay";
 140 };
 141
 142 &can2 {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_can2>;
 145         status = "okay";
 146 };
 147
 148 &esdhc1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_esdhc1>;
 151         cd-gpios = <&gpio1 1 0>;
 152         wp-gpios = <&gpio1 9 0>;
 153         status = "okay";
 154 };
 155
 156 &fec {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_fec>;
 159         phy-mode = "rmii";
 160         status = "okay";
 161 };
 162
 163 &i2c1 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_i2c1>;
 166         status = "okay";
 167
 168         sgtl5000: codec@0a {
 169                 compatible = "fsl,sgtl5000";
 170                 reg = <0x0a>;
 171                 VDDA-supply = <&reg_3p2v>;
 172                 VDDIO-supply = <&reg_3p2v>;
 173                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 174         };
 175 };
 176
 177 &i2c2 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_i2c2>;
 180         clock-frequency = <400000>;
 181         status = "okay";
 182
 183         stmpe610@41 {
 184                 compatible = "st,stmpe610";
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 reg = <0x41>;
 188                 id = <0>;
 189                 blocks = <0x5>;
 190                 interrupts = <6 0x0>;
 191                 interrupt-parent = <&gpio7>;
 192                 irq-trigger = <0x1>;
 193
 194                 stmpe_touchscreen {
 195                         compatible = "st,stmpe-ts";
 196                         reg = <0>;
 197                         st,sample-time = <4>;
 198                         st,mod-12b = <1>;
 199                         st,ref-sel = <0>;
 200                         st,adc-freq = <1>;
 201                         st,ave-ctrl = <3>;
 202                         st,touch-det-delay = <3>;
 203                         st,settling = <4>;
 204                         st,fraction-z = <7>;
 205                         st,i-drive = <1>;
 206                 };
 207         };
 208
 209         eeprom: eeprom@50 {
 210                 compatible = "atmel,24c128";
 211                 reg = <0x50>;
 212                 pagesize = <32>;
 213         };
 214
 215         rtc: rtc@68 {
 216                 compatible = "stm,m41t62";
 217                 reg = <0x68>;
 218         };
 219 };
 220
 221 &i2c3 {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_i2c3>;
 224         status = "okay";
 225 };
 226
 227 &iomuxc {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_hog>;
 230
 231         imx53-m53evk {
 232                 pinctrl_hog: hoggrp {
 233                         fsl,pins = <
 234                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
 235                                 MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
 236                                 MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
 237                                 MX53_PAD_GPIO_2__GPIO1_2                0x80000000
 238                                 MX53_PAD_GPIO_3__USBOH3_USBH1_OC        0x80000000
 239                         >;
 240                 };
 241
 242                 led_pin_gpio: led_gpio@0 {
 243                         fsl,pins = <
 244                                 MX53_PAD_PATA_DATA8__GPIO2_8            0x80000000
 245                                 MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
 246                         >;
 247                 };
 248
 249                 pinctrl_audmux: audmuxgrp {
 250                         fsl,pins = <
 251                                 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 252                                 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 253                                 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 254                                 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 255                         >;
 256                 };
 257
 258                 pinctrl_can1: can1grp {
 259                         fsl,pins = <
 260                                 MX53_PAD_GPIO_7__CAN1_TXCAN             0x80000000
 261                                 MX53_PAD_GPIO_8__CAN1_RXCAN             0x80000000
 262                         >;
 263                 };
 264
 265                 pinctrl_can2: can2grp {
 266                         fsl,pins = <
 267                                 MX53_PAD_KEY_COL4__CAN2_TXCAN           0x80000000
 268                                 MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x80000000
 269                         >;
 270                 };
 271
 272                 pinctrl_esdhc1: esdhc1grp {
 273                         fsl,pins = <
 274                                 MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
 275                                 MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
 276                                 MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
 277                                 MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
 278                                 MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
 279                                 MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
 280                         >;
 281                 };
 282
 283                 pinctrl_fec: fecgrp {
 284                         fsl,pins = <
 285                                 MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
 286                                 MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
 287                                 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
 288                                 MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
 289                                 MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
 290                                 MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
 291                                 MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
 292                                 MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
 293                                 MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
 294                                 MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
 295                         >;
 296                 };
 297
 298                 pinctrl_i2c1: i2c1grp {
 299                         fsl,pins = <
 300                                 MX53_PAD_EIM_D21__I2C1_SCL              0xc0000000
 301                                 MX53_PAD_EIM_D28__I2C1_SDA              0xc0000000
 302                         >;
 303                 };
 304
 305                 pinctrl_i2c2: i2c2grp {
 306                         fsl,pins = <
 307                                 MX53_PAD_EIM_D16__I2C2_SDA              0xc0000000
 308                                 MX53_PAD_EIM_EB2__I2C2_SCL              0xc0000000
 309                         >;
 310                 };
 311
 312                 pinctrl_i2c3: i2c3grp {
 313                         fsl,pins = <
 314                                 MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
 315                                 MX53_PAD_GPIO_5__I2C3_SCL               0xc0000000
 316                         >;
 317                 };
 318
 319                 pinctrl_ipu_disp1: ipudisp1grp {
 320                         fsl,pins = <
 321                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
 322                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
 323                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
 324                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
 325                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
 326                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
 327                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
 328                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
 329                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
 330                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
 331                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
 332                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
 333                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
 334                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
 335                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
 336                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
 337                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
 338                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
 339                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
 340                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
 341                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
 342                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
 343                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
 344                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
 345                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
 346                                 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
 347                                 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
 348                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
 349                                 MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
 350                                 MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
 351                                 MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
 352                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
 353                         >;
 354                 };
 355
 356                 pinctrl_nand: nandgrp {
 357                         fsl,pins = <
 358                                 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
 359                                 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
 360                                 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
 361                                 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
 362                                 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
 363                                 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
 364                                 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
 365                                 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
 366                                 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
 367                                 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
 368                                 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
 369                                 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
 370                                 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
 371                                 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
 372                                 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
 373                         >;
 374                 };
 375
 376                 pinctrl_pwm1: pwm1grp {
 377                         fsl,pins = <
 378                                 MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
 379                         >;
 380                 };
 381
 382                 pinctrl_uart1: uart1grp {
 383                         fsl,pins = <
 384                                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
 385                                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
 386                         >;
 387                 };
 388
 389                 pinctrl_uart2: uart2grp {
 390                         fsl,pins = <
 391                                 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
 392                                 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
 393                         >;
 394                 };
 395
 396                 pinctrl_uart3: uart3grp {
 397                         fsl,pins = <
 398                                 MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
 399                                 MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
 400                                 MX53_PAD_PATA_DA_1__UART3_CTS           0x1e4
 401                                 MX53_PAD_PATA_DA_2__UART3_RTS           0x1e4
 402                         >;
 403                 };
 404         };
 405 };
 406
 407 &ipu_di1_disp1 {
 408         remote-endpoint = <&display1_in>;
 409 };
 410
 411 &nfc {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_nand>;
 414         nand-bus-width = <8>;
 415         nand-ecc-mode = "hw";
 416         status = "okay";
 417 };
 418
 419 &pwm1 {
 420         pinctrl-names = "default";
 421         pinctrl-0 = <&pinctrl_pwm1>;
 422         status = "okay";
 423 };
 424
 425 &sata {
 426         status = "okay";
 427 };
 428
 429 &ssi2 {
 430         fsl,mode = "i2s-slave";
 431         status = "okay";
 432 };
 433
 434 &uart1 {
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&pinctrl_uart1>;
 437         status = "okay";
 438 };
 439
 440 &uart2 {
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&pinctrl_uart2>;
 443         status = "okay";
 444 };
 445
 446 &uart3 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_uart3>;
 449         status = "okay";
 450 };
 451
 452 &usbh1 {
 453         vbus-supply = <&reg_usbh1_vbus>;
 454         phy_type = "utmi";
 455         status = "okay";
 456 };
 457
 458 &usbotg {
 459         dr_mode = "peripheral";
 460         status = "okay";
 461 };