arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18
  19 / {
  20         aliases {
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 mmc0 = &esdhc1;
  32                 mmc1 = &esdhc2;
  33                 mmc2 = &esdhc3;
  34                 mmc3 = &esdhc4;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 spi0 = &ecspi1;
  41                 spi1 = &ecspi2;
  42                 spi2 = &cspi;
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a8";
  51                         reg = <0x0>;
  52                 };
  53         };
  54
  55         tzic: tz-interrupt-controller@0fffc000 {
  56                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <1>;
  59                 reg = <0x0fffc000 0x4000>;
  60         };
  61
  62         clocks {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 ckil {
  67                         compatible = "fsl,imx-ckil", "fixed-clock";
  68                         clock-frequency = <32768>;
  69                 };
  70
  71                 ckih1 {
  72                         compatible = "fsl,imx-ckih1", "fixed-clock";
  73                         clock-frequency = <22579200>;
  74                 };
  75
  76                 ckih2 {
  77                         compatible = "fsl,imx-ckih2", "fixed-clock";
  78                         clock-frequency = <0>;
  79                 };
  80
  81                 osc {
  82                         compatible = "fsl,imx-osc", "fixed-clock";
  83                         clock-frequency = <24000000>;
  84                 };
  85         };
  86
  87         soc {
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 compatible = "simple-bus";
  91                 interrupt-parent = <&tzic>;
  92                 ranges;
  93
  94                 sata: sata@10000000 {
  95                         compatible = "fsl,imx53-ahci";
  96                         reg = <0x10000000 0x1000>;
  97                         interrupts = <28>;
  98                         clocks = <&clks IMX5_CLK_SATA_GATE>,
  99                                  <&clks IMX5_CLK_SATA_REF>,
 100                                  <&clks IMX5_CLK_AHB>;
 101                         clock-names = "sata_gate", "sata_ref", "ahb";
 102                         status = "disabled";
 103                 };
 104
 105                 ipu: ipu@18000000 {
 106                         #crtc-cells = <1>;
 107                         compatible = "fsl,imx53-ipu";
 108                         reg = <0x18000000 0x080000000>;
 109                         interrupts = <11 10>;
 110                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 111                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 112                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 113                         clock-names = "bus", "di0", "di1";
 114                         resets = <&src 2>;
 115                 };
 116
 117                 aips@50000000 { /* AIPS1 */
 118                         compatible = "fsl,aips-bus", "simple-bus";
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         reg = <0x50000000 0x10000000>;
 122                         ranges;
 123
 124                         spba@50000000 {
 125                                 compatible = "fsl,spba-bus", "simple-bus";
 126                                 #address-cells = <1>;
 127                                 #size-cells = <1>;
 128                                 reg = <0x50000000 0x40000>;
 129                                 ranges;
 130
 131                                 esdhc1: esdhc@50004000 {
 132                                         compatible = "fsl,imx53-esdhc";
 133                                         reg = <0x50004000 0x4000>;
 134                                         interrupts = <1>;
 135                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 136                                                  <&clks IMX5_CLK_DUMMY>,
 137                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 138                                         clock-names = "ipg", "ahb", "per";
 139                                         bus-width = <4>;
 140                                         status = "disabled";
 141                                 };
 142
 143                                 esdhc2: esdhc@50008000 {
 144                                         compatible = "fsl,imx53-esdhc";
 145                                         reg = <0x50008000 0x4000>;
 146                                         interrupts = <2>;
 147                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 148                                                  <&clks IMX5_CLK_DUMMY>,
 149                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 150                                         clock-names = "ipg", "ahb", "per";
 151                                         bus-width = <4>;
 152                                         status = "disabled";
 153                                 };
 154
 155                                 uart3: serial@5000c000 {
 156                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 157                                         reg = <0x5000c000 0x4000>;
 158                                         interrupts = <33>;
 159                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 160                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 161                                         clock-names = "ipg", "per";
 162                                         status = "disabled";
 163                                 };
 164
 165                                 ecspi1: ecspi@50010000 {
 166                                         #address-cells = <1>;
 167                                         #size-cells = <0>;
 168                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 169                                         reg = <0x50010000 0x4000>;
 170                                         interrupts = <36>;
 171                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 172                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 173                                         clock-names = "ipg", "per";
 174                                         status = "disabled";
 175                                 };
 176
 177                                 ssi2: ssi@50014000 {
 178                                         compatible = "fsl,imx53-ssi",
 179                                                         "fsl,imx51-ssi",
 180                                                         "fsl,imx21-ssi";
 181                                         reg = <0x50014000 0x4000>;
 182                                         interrupts = <30>;
 183                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 184                                         dmas = <&sdma 24 1 0>,
 185                                                <&sdma 25 1 0>;
 186                                         dma-names = "rx", "tx";
 187                                         fsl,fifo-depth = <15>;
 188                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 189                                         status = "disabled";
 190                                 };
 191
 192                                 esdhc3: esdhc@50020000 {
 193                                         compatible = "fsl,imx53-esdhc";
 194                                         reg = <0x50020000 0x4000>;
 195                                         interrupts = <3>;
 196                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 197                                                  <&clks IMX5_CLK_DUMMY>,
 198                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 199                                         clock-names = "ipg", "ahb", "per";
 200                                         bus-width = <4>;
 201                                         status = "disabled";
 202                                 };
 203
 204                                 esdhc4: esdhc@50024000 {
 205                                         compatible = "fsl,imx53-esdhc";
 206                                         reg = <0x50024000 0x4000>;
 207                                         interrupts = <4>;
 208                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 209                                                  <&clks IMX5_CLK_DUMMY>,
 210                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 211                                         clock-names = "ipg", "ahb", "per";
 212                                         bus-width = <4>;
 213                                         status = "disabled";
 214                                 };
 215                         };
 216
 217                         usbphy0: usbphy@0 {
 218                                 compatible = "usb-nop-xceiv";
 219                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 220                                 clock-names = "main_clk";
 221                                 status = "okay";
 222                         };
 223
 224                         usbphy1: usbphy@1 {
 225                                 compatible = "usb-nop-xceiv";
 226                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 227                                 clock-names = "main_clk";
 228                                 status = "okay";
 229                         };
 230
 231                         usbotg: usb@53f80000 {
 232                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 233                                 reg = <0x53f80000 0x0200>;
 234                                 interrupts = <18>;
 235                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 236                                 fsl,usbmisc = <&usbmisc 0>;
 237                                 fsl,usbphy = <&usbphy0>;
 238                                 status = "disabled";
 239                         };
 240
 241                         usbh1: usb@53f80200 {
 242                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 243                                 reg = <0x53f80200 0x0200>;
 244                                 interrupts = <14>;
 245                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 246                                 fsl,usbmisc = <&usbmisc 1>;
 247                                 fsl,usbphy = <&usbphy1>;
 248                                 status = "disabled";
 249                         };
 250
 251                         usbh2: usb@53f80400 {
 252                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 253                                 reg = <0x53f80400 0x0200>;
 254                                 interrupts = <16>;
 255                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 256                                 fsl,usbmisc = <&usbmisc 2>;
 257                                 status = "disabled";
 258                         };
 259
 260                         usbh3: usb@53f80600 {
 261                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 262                                 reg = <0x53f80600 0x0200>;
 263                                 interrupts = <17>;
 264                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 265                                 fsl,usbmisc = <&usbmisc 3>;
 266                                 status = "disabled";
 267                         };
 268
 269                         usbmisc: usbmisc@53f80800 {
 270                                 #index-cells = <1>;
 271                                 compatible = "fsl,imx53-usbmisc";
 272                                 reg = <0x53f80800 0x200>;
 273                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 274                         };
 275
 276                         gpio1: gpio@53f84000 {
 277                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 278                                 reg = <0x53f84000 0x4000>;
 279                                 interrupts = <50 51>;
 280                                 gpio-controller;
 281                                 #gpio-cells = <2>;
 282                                 interrupt-controller;
 283                                 #interrupt-cells = <2>;
 284                         };
 285
 286                         gpio2: gpio@53f88000 {
 287                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 288                                 reg = <0x53f88000 0x4000>;
 289                                 interrupts = <52 53>;
 290                                 gpio-controller;
 291                                 #gpio-cells = <2>;
 292                                 interrupt-controller;
 293                                 #interrupt-cells = <2>;
 294                         };
 295
 296                         gpio3: gpio@53f8c000 {
 297                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 298                                 reg = <0x53f8c000 0x4000>;
 299                                 interrupts = <54 55>;
 300                                 gpio-controller;
 301                                 #gpio-cells = <2>;
 302                                 interrupt-controller;
 303                                 #interrupt-cells = <2>;
 304                         };
 305
 306                         gpio4: gpio@53f90000 {
 307                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 308                                 reg = <0x53f90000 0x4000>;
 309                                 interrupts = <56 57>;
 310                                 gpio-controller;
 311                                 #gpio-cells = <2>;
 312                                 interrupt-controller;
 313                                 #interrupt-cells = <2>;
 314                         };
 315
 316                         kpp: kpp@53f94000 {
 317                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 318                                 reg = <0x53f94000 0x4000>;
 319                                 interrupts = <60>;
 320                                 clocks = <&clks IMX5_CLK_DUMMY>;
 321                                 status = "disabled";
 322                         };
 323
 324                         wdog1: wdog@53f98000 {
 325                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 326                                 reg = <0x53f98000 0x4000>;
 327                                 interrupts = <58>;
 328                                 clocks = <&clks IMX5_CLK_DUMMY>;
 329                         };
 330
 331                         wdog2: wdog@53f9c000 {
 332                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 333                                 reg = <0x53f9c000 0x4000>;
 334                                 interrupts = <59>;
 335                                 clocks = <&clks IMX5_CLK_DUMMY>;
 336                                 status = "disabled";
 337                         };
 338
 339                         gpt: timer@53fa0000 {
 340                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 341                                 reg = <0x53fa0000 0x4000>;
 342                                 interrupts = <39>;
 343                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 344                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 345                                 clock-names = "ipg", "per";
 346                         };
 347
 348                         iomuxc: iomuxc@53fa8000 {
 349                                 compatible = "fsl,imx53-iomuxc";
 350                                 reg = <0x53fa8000 0x4000>;
 351                         };
 352
 353                         gpr: iomuxc-gpr@53fa8000 {
 354                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 355                                 reg = <0x53fa8000 0xc>;
 356                         };
 357
 358                         ldb: ldb@53fa8008 {
 359                                 #address-cells = <1>;
 360                                 #size-cells = <0>;
 361                                 compatible = "fsl,imx53-ldb";
 362                                 reg = <0x53fa8008 0x4>;
 363                                 gpr = <&gpr>;
 364                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 365                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 366                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 367                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 368                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 369                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 370                                 clock-names = "di0_pll", "di1_pll",
 371                                               "di0_sel", "di1_sel",
 372                                               "di0", "di1";
 373                                 status = "disabled";
 374
 375                                 lvds-channel@0 {
 376                                         reg = <0>;
 377                                         crtcs = <&ipu 0>;
 378                                         status = "disabled";
 379                                 };
 380
 381                                 lvds-channel@1 {
 382                                         reg = <1>;
 383                                         crtcs = <&ipu 1>;
 384                                         status = "disabled";
 385                                 };
 386                         };
 387
 388                         pwm1: pwm@53fb4000 {
 389                                 #pwm-cells = <2>;
 390                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 391                                 reg = <0x53fb4000 0x4000>;
 392                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 393                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 394                                 clock-names = "ipg", "per";
 395                                 interrupts = <61>;
 396                         };
 397
 398                         pwm2: pwm@53fb8000 {
 399                                 #pwm-cells = <2>;
 400                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 401                                 reg = <0x53fb8000 0x4000>;
 402                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 403                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 404                                 clock-names = "ipg", "per";
 405                                 interrupts = <94>;
 406                         };
 407
 408                         uart1: serial@53fbc000 {
 409                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 410                                 reg = <0x53fbc000 0x4000>;
 411                                 interrupts = <31>;
 412                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 413                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 414                                 clock-names = "ipg", "per";
 415                                 status = "disabled";
 416                         };
 417
 418                         uart2: serial@53fc0000 {
 419                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 420                                 reg = <0x53fc0000 0x4000>;
 421                                 interrupts = <32>;
 422                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 423                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 424                                 clock-names = "ipg", "per";
 425                                 status = "disabled";
 426                         };
 427
 428                         can1: can@53fc8000 {
 429                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 430                                 reg = <0x53fc8000 0x4000>;
 431                                 interrupts = <82>;
 432                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 433                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 434                                 clock-names = "ipg", "per";
 435                                 status = "disabled";
 436                         };
 437
 438                         can2: can@53fcc000 {
 439                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 440                                 reg = <0x53fcc000 0x4000>;
 441                                 interrupts = <83>;
 442                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 443                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 444                                 clock-names = "ipg", "per";
 445                                 status = "disabled";
 446                         };
 447
 448                         src: src@53fd0000 {
 449                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 450                                 reg = <0x53fd0000 0x4000>;
 451                                 #reset-cells = <1>;
 452                         };
 453
 454                         clks: ccm@53fd4000{
 455                                 compatible = "fsl,imx53-ccm";
 456                                 reg = <0x53fd4000 0x4000>;
 457                                 interrupts = <0 71 0x04 0 72 0x04>;
 458                                 #clock-cells = <1>;
 459                         };
 460
 461                         gpio5: gpio@53fdc000 {
 462                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 463                                 reg = <0x53fdc000 0x4000>;
 464                                 interrupts = <103 104>;
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <2>;
 469                         };
 470
 471                         gpio6: gpio@53fe0000 {
 472                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 473                                 reg = <0x53fe0000 0x4000>;
 474                                 interrupts = <105 106>;
 475                                 gpio-controller;
 476                                 #gpio-cells = <2>;
 477                                 interrupt-controller;
 478                                 #interrupt-cells = <2>;
 479                         };
 480
 481                         gpio7: gpio@53fe4000 {
 482                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 483                                 reg = <0x53fe4000 0x4000>;
 484                                 interrupts = <107 108>;
 485                                 gpio-controller;
 486                                 #gpio-cells = <2>;
 487                                 interrupt-controller;
 488                                 #interrupt-cells = <2>;
 489                         };
 490
 491                         i2c3: i2c@53fec000 {
 492                                 #address-cells = <1>;
 493                                 #size-cells = <0>;
 494                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 495                                 reg = <0x53fec000 0x4000>;
 496                                 interrupts = <64>;
 497                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 498                                 status = "disabled";
 499                         };
 500
 501                         uart4: serial@53ff0000 {
 502                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 503                                 reg = <0x53ff0000 0x4000>;
 504                                 interrupts = <13>;
 505                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 506                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 507                                 clock-names = "ipg", "per";
 508                                 status = "disabled";
 509                         };
 510                 };
 511
 512                 aips@60000000 { /* AIPS2 */
 513                         compatible = "fsl,aips-bus", "simple-bus";
 514                         #address-cells = <1>;
 515                         #size-cells = <1>;
 516                         reg = <0x60000000 0x10000000>;
 517                         ranges;
 518
 519                         iim: iim@63f98000 {
 520                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 521                                 reg = <0x63f98000 0x4000>;
 522                                 interrupts = <69>;
 523                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 524                         };
 525
 526                         uart5: serial@63f90000 {
 527                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 528                                 reg = <0x63f90000 0x4000>;
 529                                 interrupts = <86>;
 530                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 531                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 532                                 clock-names = "ipg", "per";
 533                                 status = "disabled";
 534                         };
 535
 536                         owire: owire@63fa4000 {
 537                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 538                                 reg = <0x63fa4000 0x4000>;
 539                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 540                                 status = "disabled";
 541                         };
 542
 543                         ecspi2: ecspi@63fac000 {
 544                                 #address-cells = <1>;
 545                                 #size-cells = <0>;
 546                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 547                                 reg = <0x63fac000 0x4000>;
 548                                 interrupts = <37>;
 549                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 550                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 551                                 clock-names = "ipg", "per";
 552                                 status = "disabled";
 553                         };
 554
 555                         sdma: sdma@63fb0000 {
 556                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 557                                 reg = <0x63fb0000 0x4000>;
 558                                 interrupts = <6>;
 559                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 560                                          <&clks IMX5_CLK_SDMA_GATE>;
 561                                 clock-names = "ipg", "ahb";
 562                                 #dma-cells = <3>;
 563                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 564                         };
 565
 566                         cspi: cspi@63fc0000 {
 567                                 #address-cells = <1>;
 568                                 #size-cells = <0>;
 569                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 570                                 reg = <0x63fc0000 0x4000>;
 571                                 interrupts = <38>;
 572                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 573                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 574                                 clock-names = "ipg", "per";
 575                                 status = "disabled";
 576                         };
 577
 578                         i2c2: i2c@63fc4000 {
 579                                 #address-cells = <1>;
 580                                 #size-cells = <0>;
 581                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 582                                 reg = <0x63fc4000 0x4000>;
 583                                 interrupts = <63>;
 584                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 585                                 status = "disabled";
 586                         };
 587
 588                         i2c1: i2c@63fc8000 {
 589                                 #address-cells = <1>;
 590                                 #size-cells = <0>;
 591                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 592                                 reg = <0x63fc8000 0x4000>;
 593                                 interrupts = <62>;
 594                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 595                                 status = "disabled";
 596                         };
 597
 598                         ssi1: ssi@63fcc000 {
 599                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 600                                                 "fsl,imx21-ssi";
 601                                 reg = <0x63fcc000 0x4000>;
 602                                 interrupts = <29>;
 603                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 604                                 dmas = <&sdma 28 0 0>,
 605                                        <&sdma 29 0 0>;
 606                                 dma-names = "rx", "tx";
 607                                 fsl,fifo-depth = <15>;
 608                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 609                                 status = "disabled";
 610                         };
 611
 612                         audmux: audmux@63fd0000 {
 613                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 614                                 reg = <0x63fd0000 0x4000>;
 615                                 status = "disabled";
 616                         };
 617
 618                         nfc: nand@63fdb000 {
 619                                 compatible = "fsl,imx53-nand";
 620                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 621                                 interrupts = <8>;
 622                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 623                                 status = "disabled";
 624                         };
 625
 626                         ssi3: ssi@63fe8000 {
 627                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 628                                                 "fsl,imx21-ssi";
 629                                 reg = <0x63fe8000 0x4000>;
 630                                 interrupts = <96>;
 631                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
 632                                 dmas = <&sdma 46 0 0>,
 633                                        <&sdma 47 0 0>;
 634                                 dma-names = "rx", "tx";
 635                                 fsl,fifo-depth = <15>;
 636                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 637                                 status = "disabled";
 638                         };
 639
 640                         fec: ethernet@63fec000 {
 641                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 642                                 reg = <0x63fec000 0x4000>;
 643                                 interrupts = <87>;
 644                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 645                                          <&clks IMX5_CLK_FEC_GATE>,
 646                                          <&clks IMX5_CLK_FEC_GATE>;
 647                                 clock-names = "ipg", "ahb", "ptp";
 648                                 status = "disabled";
 649                         };
 650
 651                         tve: tve@63ff0000 {
 652                                 compatible = "fsl,imx53-tve";
 653                                 reg = <0x63ff0000 0x1000>;
 654                                 interrupts = <92>;
 655                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 656                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 657                                 clock-names = "tve", "di_sel";
 658                                 crtcs = <&ipu 1>;
 659                                 status = "disabled";
 660                         };
 661
 662                         vpu: vpu@63ff4000 {
 663                                 compatible = "fsl,imx53-vpu";
 664                                 reg = <0x63ff4000 0x1000>;
 665                                 interrupts = <9>;
 666                                 clocks = <&clks IMX5_CLK_VPU_GATE>,
 667                                          <&clks IMX5_CLK_VPU_GATE>;
 668                                 clock-names = "per", "ahb";
 669                                 iram = <&ocram>;
 670                                 status = "disabled";
 671                         };
 672                 };
 673
 674                 ocram: sram@f8000000 {
 675                         compatible = "mmio-sram";
 676                         reg = <0xf8000000 0x20000>;
 677                         clocks = <&clks IMX5_CLK_OCRAM>;
 678                 };
 679         };
 680 };