arch/arm/boot/dts/imx6q-cm-fx6.dts

   1 /*
   2  * Copyright 2013 CompuLab Ltd.
   3  *
   4  * Author: Valentin Raevsky <valentin@compulab.co.il>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /dts-v1/;
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include "imx6q.dtsi"
  17
  18 / {
  19         model = "CompuLab CM-FX6";
  20         compatible = "compulab,cm-fx6", "fsl,imx6q";
  21
  22         memory {
  23                 reg = <0x10000000 0x80000000>;
  24         };
  25
  26         leds {
  27                 compatible = "gpio-leds";
  28
  29                 heartbeat-led {
  30                         label = "Heartbeat";
  31                         gpios = <&gpio2 31 0>;
  32                         linux,default-trigger = "heartbeat";
  33                 };
  34         };
  35
  36         reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "regulator-pcie-power-on-gpio";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  42                 enable-active-high;
  43         };
  44
  45         reg_usb_h1_vbus: usb_h1_vbus {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "usb_h1_vbus";
  48                 regulator-min-microvolt = <5000000>;
  49                 regulator-max-microvolt = <5000000>;
  50                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         reg_usb_otg_vbus: usb_otg_vbus {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "usb_otg_vbus";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  60                 enable-active-high;
  61         };
  62 };
  63
  64 &ecspi1 {
  65         fsl,spi-num-chipselects = <2>;
  66         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
  67         pinctrl-names = "default";
  68         pinctrl-0 = <&pinctrl_ecspi1>;
  69         status = "okay";
  70
  71         m25p80@0 {
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 compatible = "st,m25p", "jedec,spi-nor";
  75                 spi-max-frequency = <20000000>;
  76                 reg = <0>;
  77         };
  78 };
  79
  80 &fec {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_enet>;
  83         phy-mode = "rgmii";
  84         status = "okay";
  85 };
  86
  87 &gpmi {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_gpmi_nand>;
  90         status = "okay";
  91 };
  92
  93 &i2c3 {
  94         pinctrl-names = "default";
  95         pinctrl-0 = <&pinctrl_i2c3>;
  96         status = "okay";
  97         clock-frequency = <100000>;
  98
  99         eeprom@50 {
 100                 compatible = "at24,24c02";
 101                 reg = <0x50>;
 102                 pagesize = <16>;
 103         };
 104 };
 105
 106 &iomuxc {
 107         pinctrl_ecspi1: ecspi1grp {
 108                 fsl,pins = <
 109                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 110                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 111                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 112                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x100b1
 113                         MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x100b1
 114                 >;
 115         };
 116
 117         pinctrl_enet: enetgrp {
 118                 fsl,pins = <
 119                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 120                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 121                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 122                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 123                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 124                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 125                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 126                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 127                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 128                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 129                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 130                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 131                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 132                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 133                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 134                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 135                 >;
 136         };
 137
 138         pinctrl_gpmi_nand: gpminandgrp {
 139                 fsl,pins = <
 140                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 141                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 142                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 143                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 144                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 145                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 146                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 147                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 148                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 149                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 150                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 151                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 152                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 153                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 154                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 155                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 156                         MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 157                 >;
 158         };
 159
 160         pinctrl_i2c3: i2c3grp {
 161                 fsl,pins = <
 162                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
 163                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
 164                 >;
 165         };
 166
 167         pinctrl_pcie: pciegrp {
 168                 fsl,pins = <
 169                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 170                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0x1b0b1
 171                 >;
 172         };
 173
 174         pinctrl_uart4: uart4grp {
 175                 fsl,pins = <
 176                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 177                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 178                 >;
 179         };
 180
 181         pinctrl_usbh1: usbh1grp {
 182                 fsl,pins = <
 183                         MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b0b1
 184                 >;
 185         };
 186
 187         pinctrl_usbotg: usbotggrp {
 188                 fsl,pins = <
 189                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 190                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x130b0
 191                 >;
 192         };
 193 };
 194
 195 &pcie {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_pcie>;
 198         reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
 199         vdd-supply = <&reg_pcie_power_on_gpio>;
 200         status = "okay";
 201 };
 202
 203 &sata {
 204         status = "okay";
 205 };
 206
 207 &snvs_poweroff {
 208         status = "okay";
 209 };
 210
 211 &uart4 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_uart4>;
 214         status = "okay";
 215 };
 216
 217 &usbh1 {
 218         vbus-supply = <&reg_usb_h1_vbus>;
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_usbh1>;
 221         status = "okay";
 222 };
 223
 224 &usbotg {
 225         vbus-supply = <&reg_usb_otg_vbus>;
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_usbotg>;
 228         dr_mode = "otg";
 229         status = "okay";
 230 };