arch/arm/boot/dts/imx6q.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a9";
  37                         reg = <0>;
  38                         next-level-cache = <&L2>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a9";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                 };
  46
  47                 cpu@2 {
  48                         compatible = "arm,cortex-a9";
  49                         reg = <2>;
  50                         next-level-cache = <&L2>;
  51                 };
  52
  53                 cpu@3 {
  54                         compatible = "arm,cortex-a9";
  55                         reg = <3>;
  56                         next-level-cache = <&L2>;
  57                 };
  58         };
  59
  60         intc: interrupt-controller@00a01000 {
  61                 compatible = "arm,cortex-a9-gic";
  62                 #interrupt-cells = <3>;
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 interrupt-controller;
  66                 reg = <0x00a01000 0x1000>,
  67                       <0x00a00100 0x100>;
  68         };
  69
  70         clocks {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 ckil {
  75                         compatible = "fsl,imx-ckil", "fixed-clock";
  76                         clock-frequency = <32768>;
  77                 };
  78
  79                 ckih1 {
  80                         compatible = "fsl,imx-ckih1", "fixed-clock";
  81                         clock-frequency = <0>;
  82                 };
  83
  84                 osc {
  85                         compatible = "fsl,imx-osc", "fixed-clock";
  86                         clock-frequency = <24000000>;
  87                 };
  88         };
  89
  90         soc {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 compatible = "simple-bus";
  94                 interrupt-parent = <&intc>;
  95                 ranges;
  96
  97                 dma-apbh@00110000 {
  98                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  99                         reg = <0x00110000 0x2000>;
 100                 };
 101
 102                 gpmi-nand@00112000 {
 103                        compatible = "fsl,imx6q-gpmi-nand";
 104                        #address-cells = <1>;
 105                        #size-cells = <1>;
 106                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 107                        reg-names = "gpmi-nand", "bch";
 108                        interrupts = <0 13 0x04>, <0 15 0x04>;
 109                        interrupt-names = "gpmi-dma", "bch";
 110                        fsl,gpmi-dma-channel = <0>;
 111                        status = "disabled";
 112                 };
 113
 114                 timer@00a00600 {
 115                         compatible = "arm,cortex-a9-twd-timer";
 116                         reg = <0x00a00600 0x20>;
 117                         interrupts = <1 13 0xf01>;
 118                 };
 119
 120                 L2: l2-cache@00a02000 {
 121                         compatible = "arm,pl310-cache";
 122                         reg = <0x00a02000 0x1000>;
 123                         interrupts = <0 92 0x04>;
 124                         cache-unified;
 125                         cache-level = <2>;
 126                 };
 127
 128                 aips-bus@02000000 { /* AIPS1 */
 129                         compatible = "fsl,aips-bus", "simple-bus";
 130                         #address-cells = <1>;
 131                         #size-cells = <1>;
 132                         reg = <0x02000000 0x100000>;
 133                         ranges;
 134
 135                         spba-bus@02000000 {
 136                                 compatible = "fsl,spba-bus", "simple-bus";
 137                                 #address-cells = <1>;
 138                                 #size-cells = <1>;
 139                                 reg = <0x02000000 0x40000>;
 140                                 ranges;
 141
 142                                 spdif@02004000 {
 143                                         reg = <0x02004000 0x4000>;
 144                                         interrupts = <0 52 0x04>;
 145                                 };
 146
 147                                 ecspi@02008000 { /* eCSPI1 */
 148                                         #address-cells = <1>;
 149                                         #size-cells = <0>;
 150                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 151                                         reg = <0x02008000 0x4000>;
 152                                         interrupts = <0 31 0x04>;
 153                                         status = "disabled";
 154                                 };
 155
 156                                 ecspi@0200c000 { /* eCSPI2 */
 157                                         #address-cells = <1>;
 158                                         #size-cells = <0>;
 159                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 160                                         reg = <0x0200c000 0x4000>;
 161                                         interrupts = <0 32 0x04>;
 162                                         status = "disabled";
 163                                 };
 164
 165                                 ecspi@02010000 { /* eCSPI3 */
 166                                         #address-cells = <1>;
 167                                         #size-cells = <0>;
 168                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 169                                         reg = <0x02010000 0x4000>;
 170                                         interrupts = <0 33 0x04>;
 171                                         status = "disabled";
 172                                 };
 173
 174                                 ecspi@02014000 { /* eCSPI4 */
 175                                         #address-cells = <1>;
 176                                         #size-cells = <0>;
 177                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 178                                         reg = <0x02014000 0x4000>;
 179                                         interrupts = <0 34 0x04>;
 180                                         status = "disabled";
 181                                 };
 182
 183                                 ecspi@02018000 { /* eCSPI5 */
 184                                         #address-cells = <1>;
 185                                         #size-cells = <0>;
 186                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 187                                         reg = <0x02018000 0x4000>;
 188                                         interrupts = <0 35 0x04>;
 189                                         status = "disabled";
 190                                 };
 191
 192                                 uart1: serial@02020000 {
 193                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 194                                         reg = <0x02020000 0x4000>;
 195                                         interrupts = <0 26 0x04>;
 196                                         status = "disabled";
 197                                 };
 198
 199                                 esai@02024000 {
 200                                         reg = <0x02024000 0x4000>;
 201                                         interrupts = <0 51 0x04>;
 202                                 };
 203
 204                                 ssi1: ssi@02028000 {
 205                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 206                                         reg = <0x02028000 0x4000>;
 207                                         interrupts = <0 46 0x04>;
 208                                         fsl,fifo-depth = <15>;
 209                                         fsl,ssi-dma-events = <38 37>;
 210                                         status = "disabled";
 211                                 };
 212
 213                                 ssi2: ssi@0202c000 {
 214                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 215                                         reg = <0x0202c000 0x4000>;
 216                                         interrupts = <0 47 0x04>;
 217                                         fsl,fifo-depth = <15>;
 218                                         fsl,ssi-dma-events = <42 41>;
 219                                         status = "disabled";
 220                                 };
 221
 222                                 ssi3: ssi@02030000 {
 223                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 224                                         reg = <0x02030000 0x4000>;
 225                                         interrupts = <0 48 0x04>;
 226                                         fsl,fifo-depth = <15>;
 227                                         fsl,ssi-dma-events = <46 45>;
 228                                         status = "disabled";
 229                                 };
 230
 231                                 asrc@02034000 {
 232                                         reg = <0x02034000 0x4000>;
 233                                         interrupts = <0 50 0x04>;
 234                                 };
 235
 236                                 spba@0203c000 {
 237                                         reg = <0x0203c000 0x4000>;
 238                                 };
 239                         };
 240
 241                         vpu@02040000 {
 242                                 reg = <0x02040000 0x3c000>;
 243                                 interrupts = <0 3 0x04 0 12 0x04>;
 244                         };
 245
 246                         aipstz@0207c000 { /* AIPSTZ1 */
 247                                 reg = <0x0207c000 0x4000>;
 248                         };
 249
 250                         pwm@02080000 { /* PWM1 */
 251                                 reg = <0x02080000 0x4000>;
 252                                 interrupts = <0 83 0x04>;
 253                         };
 254
 255                         pwm@02084000 { /* PWM2 */
 256                                 reg = <0x02084000 0x4000>;
 257                                 interrupts = <0 84 0x04>;
 258                         };
 259
 260                         pwm@02088000 { /* PWM3 */
 261                                 reg = <0x02088000 0x4000>;
 262                                 interrupts = <0 85 0x04>;
 263                         };
 264
 265                         pwm@0208c000 { /* PWM4 */
 266                                 reg = <0x0208c000 0x4000>;
 267                                 interrupts = <0 86 0x04>;
 268                         };
 269
 270                         flexcan@02090000 { /* CAN1 */
 271                                 reg = <0x02090000 0x4000>;
 272                                 interrupts = <0 110 0x04>;
 273                         };
 274
 275                         flexcan@02094000 { /* CAN2 */
 276                                 reg = <0x02094000 0x4000>;
 277                                 interrupts = <0 111 0x04>;
 278                         };
 279
 280                         gpt@02098000 {
 281                                 compatible = "fsl,imx6q-gpt";
 282                                 reg = <0x02098000 0x4000>;
 283                                 interrupts = <0 55 0x04>;
 284                         };
 285
 286                         gpio1: gpio@0209c000 {
 287                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 288                                 reg = <0x0209c000 0x4000>;
 289                                 interrupts = <0 66 0x04 0 67 0x04>;
 290                                 gpio-controller;
 291                                 #gpio-cells = <2>;
 292                                 interrupt-controller;
 293                                 #interrupt-cells = <2>;
 294                         };
 295
 296                         gpio2: gpio@020a0000 {
 297                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 298                                 reg = <0x020a0000 0x4000>;
 299                                 interrupts = <0 68 0x04 0 69 0x04>;
 300                                 gpio-controller;
 301                                 #gpio-cells = <2>;
 302                                 interrupt-controller;
 303                                 #interrupt-cells = <2>;
 304                         };
 305
 306                         gpio3: gpio@020a4000 {
 307                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 308                                 reg = <0x020a4000 0x4000>;
 309                                 interrupts = <0 70 0x04 0 71 0x04>;
 310                                 gpio-controller;
 311                                 #gpio-cells = <2>;
 312                                 interrupt-controller;
 313                                 #interrupt-cells = <2>;
 314                         };
 315
 316                         gpio4: gpio@020a8000 {
 317                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 318                                 reg = <0x020a8000 0x4000>;
 319                                 interrupts = <0 72 0x04 0 73 0x04>;
 320                                 gpio-controller;
 321                                 #gpio-cells = <2>;
 322                                 interrupt-controller;
 323                                 #interrupt-cells = <2>;
 324                         };
 325
 326                         gpio5: gpio@020ac000 {
 327                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 328                                 reg = <0x020ac000 0x4000>;
 329                                 interrupts = <0 74 0x04 0 75 0x04>;
 330                                 gpio-controller;
 331                                 #gpio-cells = <2>;
 332                                 interrupt-controller;
 333                                 #interrupt-cells = <2>;
 334                         };
 335
 336                         gpio6: gpio@020b0000 {
 337                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 338                                 reg = <0x020b0000 0x4000>;
 339                                 interrupts = <0 76 0x04 0 77 0x04>;
 340                                 gpio-controller;
 341                                 #gpio-cells = <2>;
 342                                 interrupt-controller;
 343                                 #interrupt-cells = <2>;
 344                         };
 345
 346                         gpio7: gpio@020b4000 {
 347                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 348                                 reg = <0x020b4000 0x4000>;
 349                                 interrupts = <0 78 0x04 0 79 0x04>;
 350                                 gpio-controller;
 351                                 #gpio-cells = <2>;
 352                                 interrupt-controller;
 353                                 #interrupt-cells = <2>;
 354                         };
 355
 356                         kpp@020b8000 {
 357                                 reg = <0x020b8000 0x4000>;
 358                                 interrupts = <0 82 0x04>;
 359                         };
 360
 361                         wdog@020bc000 { /* WDOG1 */
 362                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 363                                 reg = <0x020bc000 0x4000>;
 364                                 interrupts = <0 80 0x04>;
 365                                 status = "disabled";
 366                         };
 367
 368                         wdog@020c0000 { /* WDOG2 */
 369                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 370                                 reg = <0x020c0000 0x4000>;
 371                                 interrupts = <0 81 0x04>;
 372                                 status = "disabled";
 373                         };
 374
 375                         ccm@020c4000 {
 376                                 compatible = "fsl,imx6q-ccm";
 377                                 reg = <0x020c4000 0x4000>;
 378                                 interrupts = <0 87 0x04 0 88 0x04>;
 379                         };
 380
 381                         anatop@020c8000 {
 382                                 compatible = "fsl,imx6q-anatop";
 383                                 reg = <0x020c8000 0x1000>;
 384                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 385
 386                                 regulator-1p1@110 {
 387                                         compatible = "fsl,anatop-regulator";
 388                                         regulator-name = "vdd1p1";
 389                                         regulator-min-microvolt = <800000>;
 390                                         regulator-max-microvolt = <1375000>;
 391                                         regulator-always-on;
 392                                         anatop-reg-offset = <0x110>;
 393                                         anatop-vol-bit-shift = <8>;
 394                                         anatop-vol-bit-width = <5>;
 395                                         anatop-min-bit-val = <4>;
 396                                         anatop-min-voltage = <800000>;
 397                                         anatop-max-voltage = <1375000>;
 398                                 };
 399
 400                                 regulator-3p0@120 {
 401                                         compatible = "fsl,anatop-regulator";
 402                                         regulator-name = "vdd3p0";
 403                                         regulator-min-microvolt = <2800000>;
 404                                         regulator-max-microvolt = <3150000>;
 405                                         regulator-always-on;
 406                                         anatop-reg-offset = <0x120>;
 407                                         anatop-vol-bit-shift = <8>;
 408                                         anatop-vol-bit-width = <5>;
 409                                         anatop-min-bit-val = <0>;
 410                                         anatop-min-voltage = <2625000>;
 411                                         anatop-max-voltage = <3400000>;
 412                                 };
 413
 414                                 regulator-2p5@130 {
 415                                         compatible = "fsl,anatop-regulator";
 416                                         regulator-name = "vdd2p5";
 417                                         regulator-min-microvolt = <2000000>;
 418                                         regulator-max-microvolt = <2750000>;
 419                                         regulator-always-on;
 420                                         anatop-reg-offset = <0x130>;
 421                                         anatop-vol-bit-shift = <8>;
 422                                         anatop-vol-bit-width = <5>;
 423                                         anatop-min-bit-val = <0>;
 424                                         anatop-min-voltage = <2000000>;
 425                                         anatop-max-voltage = <2750000>;
 426                                 };
 427
 428                                 regulator-vddcore@140 {
 429                                         compatible = "fsl,anatop-regulator";
 430                                         regulator-name = "cpu";
 431                                         regulator-min-microvolt = <725000>;
 432                                         regulator-max-microvolt = <1450000>;
 433                                         regulator-always-on;
 434                                         anatop-reg-offset = <0x140>;
 435                                         anatop-vol-bit-shift = <0>;
 436                                         anatop-vol-bit-width = <5>;
 437                                         anatop-min-bit-val = <1>;
 438                                         anatop-min-voltage = <725000>;
 439                                         anatop-max-voltage = <1450000>;
 440                                 };
 441
 442                                 regulator-vddpu@140 {
 443                                         compatible = "fsl,anatop-regulator";
 444                                         regulator-name = "vddpu";
 445                                         regulator-min-microvolt = <725000>;
 446                                         regulator-max-microvolt = <1450000>;
 447                                         regulator-always-on;
 448                                         anatop-reg-offset = <0x140>;
 449                                         anatop-vol-bit-shift = <9>;
 450                                         anatop-vol-bit-width = <5>;
 451                                         anatop-min-bit-val = <1>;
 452                                         anatop-min-voltage = <725000>;
 453                                         anatop-max-voltage = <1450000>;
 454                                 };
 455
 456                                 regulator-vddsoc@140 {
 457                                         compatible = "fsl,anatop-regulator";
 458                                         regulator-name = "vddsoc";
 459                                         regulator-min-microvolt = <725000>;
 460                                         regulator-max-microvolt = <1450000>;
 461                                         regulator-always-on;
 462                                         anatop-reg-offset = <0x140>;
 463                                         anatop-vol-bit-shift = <18>;
 464                                         anatop-vol-bit-width = <5>;
 465                                         anatop-min-bit-val = <1>;
 466                                         anatop-min-voltage = <725000>;
 467                                         anatop-max-voltage = <1450000>;
 468                                 };
 469                         };
 470
 471                         usbphy1: usbphy@020c9000 {
 472                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 473                                 reg = <0x020c9000 0x1000>;
 474                                 interrupts = <0 44 0x04>;
 475                         };
 476
 477                         usbphy2: usbphy@020ca000 {
 478                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 479                                 reg = <0x020ca000 0x1000>;
 480                                 interrupts = <0 45 0x04>;
 481                         };
 482
 483                         snvs@020cc000 {
 484                                 reg = <0x020cc000 0x4000>;
 485                                 interrupts = <0 19 0x04 0 20 0x04>;
 486                         };
 487
 488                         epit@020d0000 { /* EPIT1 */
 489                                 reg = <0x020d0000 0x4000>;
 490                                 interrupts = <0 56 0x04>;
 491                         };
 492
 493                         epit@020d4000 { /* EPIT2 */
 494                                 reg = <0x020d4000 0x4000>;
 495                                 interrupts = <0 57 0x04>;
 496                         };
 497
 498                         src@020d8000 {
 499                                 compatible = "fsl,imx6q-src";
 500                                 reg = <0x020d8000 0x4000>;
 501                                 interrupts = <0 91 0x04 0 96 0x04>;
 502                         };
 503
 504                         gpc@020dc000 {
 505                                 compatible = "fsl,imx6q-gpc";
 506                                 reg = <0x020dc000 0x4000>;
 507                                 interrupts = <0 89 0x04 0 90 0x04>;
 508                         };
 509
 510                         iomuxc@020e0000 {
 511                                 compatible = "fsl,imx6q-iomuxc";
 512                                 reg = <0x020e0000 0x4000>;
 513
 514                                 /* shared pinctrl settings */
 515                                 audmux {
 516                                         pinctrl_audmux_1: audmux-1 {
 517                                                 fsl,pins = <18   0x80000000     /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
 518                                                             1586 0x80000000     /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
 519                                                             11   0x80000000     /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
 520                                                             3    0x80000000>;   /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
 521                                         };
 522                                 };
 523
 524                                 gpmi-nand {
 525                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 526                                                 fsl,pins = <1328 0xb0b1         /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
 527                                                             1336 0xb0b1         /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
 528                                                             1344 0xb0b1         /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
 529                                                             1352 0xb000         /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
 530                                                             1360 0xb0b1         /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
 531                                                             1365 0xb0b1         /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
 532                                                             1371 0xb0b1         /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
 533                                                             1378 0xb0b1         /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
 534                                                             1387 0xb0b1         /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
 535                                                             1393 0xb0b1         /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
 536                                                             1397 0xb0b1         /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
 537                                                             1405 0xb0b1         /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
 538                                                             1413 0xb0b1         /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
 539                                                             1421 0xb0b1         /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
 540                                                             1429 0xb0b1         /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
 541                                                             1437 0xb0b1         /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
 542                                                             1445 0xb0b1         /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
 543                                                             1453 0xb0b1         /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
 544                                                             1463 0x00b1>;       /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
 545                                         };
 546                                 };
 547
 548                                 i2c1 {
 549                                         pinctrl_i2c1_1: i2c1grp-1 {
 550                                                 fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
 551                                                             196 0x4001b8b1>;    /* MX6Q_PAD_EIM_D28__I2C1_SDA */
 552                                         };
 553                                 };
 554
 555                                 serial2 {
 556                                         pinctrl_serial2_1: serial2grp-1 {
 557                                                 fsl,pins = <183 0x1b0b1         /* MX6Q_PAD_EIM_D26__UART2_TXD */
 558                                                             191 0x1b0b1>;       /* MX6Q_PAD_EIM_D27__UART2_RXD */
 559                                         };
 560                                 };
 561
 562                                 usdhc3 {
 563                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 564                                                 fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
 565                                                             1281 0x10059        /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
 566                                                             1289 0x17059        /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
 567                                                             1297 0x17059        /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
 568                                                             1305 0x17059        /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
 569                                                             1312 0x17059        /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
 570                                                             1265 0x17059        /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
 571                                                             1257 0x17059        /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
 572                                                             1249 0x17059        /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
 573                                                             1241 0x17059>;      /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
 574                                         };
 575                                 };
 576
 577                                 usdhc4 {
 578                                         pinctrl_usdhc4_1: usdhc4grp-1 {
 579                                                 fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
 580                                                             1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
 581                                                             1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
 582                                                             1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
 583                                                             1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
 584                                                             1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
 585                                                             1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
 586                                                             1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
 587                                                             1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
 588                                                             1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
 589                                         };
 590                                 };
 591
 592                                 ecspi1 {
 593                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 594                                                 fsl,pins = <101 0x100b1         /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
 595                                                             109 0x100b1         /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
 596                                                             94  0x100b1>;       /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
 597                                         };
 598                                 };
 599                         };
 600
 601                         dcic@020e4000 { /* DCIC1 */
 602                                 reg = <0x020e4000 0x4000>;
 603                                 interrupts = <0 124 0x04>;
 604                         };
 605
 606                         dcic@020e8000 { /* DCIC2 */
 607                                 reg = <0x020e8000 0x4000>;
 608                                 interrupts = <0 125 0x04>;
 609                         };
 610
 611                         sdma@020ec000 {
 612                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 613                                 reg = <0x020ec000 0x4000>;
 614                                 interrupts = <0 2 0x04>;
 615                         };
 616                 };
 617
 618                 aips-bus@02100000 { /* AIPS2 */
 619                         compatible = "fsl,aips-bus", "simple-bus";
 620                         #address-cells = <1>;
 621                         #size-cells = <1>;
 622                         reg = <0x02100000 0x100000>;
 623                         ranges;
 624
 625                         caam@02100000 {
 626                                 reg = <0x02100000 0x40000>;
 627                                 interrupts = <0 105 0x04 0 106 0x04>;
 628                         };
 629
 630                         aipstz@0217c000 { /* AIPSTZ2 */
 631                                 reg = <0x0217c000 0x4000>;
 632                         };
 633
 634                         usb@02184000 { /* USB OTG */
 635                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 636                                 reg = <0x02184000 0x200>;
 637                                 interrupts = <0 43 0x04>;
 638                                 fsl,usbphy = <&usbphy1>;
 639                                 status = "disabled";
 640                         };
 641
 642                         usb@02184200 { /* USB1 */
 643                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 644                                 reg = <0x02184200 0x200>;
 645                                 interrupts = <0 40 0x04>;
 646                                 fsl,usbphy = <&usbphy2>;
 647                                 status = "disabled";
 648                         };
 649
 650                         usb@02184400 { /* USB2 */
 651                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 652                                 reg = <0x02184400 0x200>;
 653                                 interrupts = <0 41 0x04>;
 654                                 status = "disabled";
 655                         };
 656
 657                         usb@02184600 { /* USB3 */
 658                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 659                                 reg = <0x02184600 0x200>;
 660                                 interrupts = <0 42 0x04>;
 661                                 status = "disabled";
 662                         };
 663
 664                         ethernet@02188000 {
 665                                 compatible = "fsl,imx6q-fec";
 666                                 reg = <0x02188000 0x4000>;
 667                                 interrupts = <0 118 0x04 0 119 0x04>;
 668                                 status = "disabled";
 669                         };
 670
 671                         mlb@0218c000 {
 672                                 reg = <0x0218c000 0x4000>;
 673                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
 674                         };
 675
 676                         usdhc@02190000 { /* uSDHC1 */
 677                                 compatible = "fsl,imx6q-usdhc";
 678                                 reg = <0x02190000 0x4000>;
 679                                 interrupts = <0 22 0x04>;
 680                                 status = "disabled";
 681                         };
 682
 683                         usdhc@02194000 { /* uSDHC2 */
 684                                 compatible = "fsl,imx6q-usdhc";
 685                                 reg = <0x02194000 0x4000>;
 686                                 interrupts = <0 23 0x04>;
 687                                 status = "disabled";
 688                         };
 689
 690                         usdhc@02198000 { /* uSDHC3 */
 691                                 compatible = "fsl,imx6q-usdhc";
 692                                 reg = <0x02198000 0x4000>;
 693                                 interrupts = <0 24 0x04>;
 694                                 status = "disabled";
 695                         };
 696
 697                         usdhc@0219c000 { /* uSDHC4 */
 698                                 compatible = "fsl,imx6q-usdhc";
 699                                 reg = <0x0219c000 0x4000>;
 700                                 interrupts = <0 25 0x04>;
 701                                 status = "disabled";
 702                         };
 703
 704                         i2c@021a0000 { /* I2C1 */
 705                                 #address-cells = <1>;
 706                                 #size-cells = <0>;
 707                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 708                                 reg = <0x021a0000 0x4000>;
 709                                 interrupts = <0 36 0x04>;
 710                                 status = "disabled";
 711                         };
 712
 713                         i2c@021a4000 { /* I2C2 */
 714                                 #address-cells = <1>;
 715                                 #size-cells = <0>;
 716                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 717                                 reg = <0x021a4000 0x4000>;
 718                                 interrupts = <0 37 0x04>;
 719                                 status = "disabled";
 720                         };
 721
 722                         i2c@021a8000 { /* I2C3 */
 723                                 #address-cells = <1>;
 724                                 #size-cells = <0>;
 725                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 726                                 reg = <0x021a8000 0x4000>;
 727                                 interrupts = <0 38 0x04>;
 728                                 status = "disabled";
 729                         };
 730
 731                         romcp@021ac000 {
 732                                 reg = <0x021ac000 0x4000>;
 733                         };
 734
 735                         mmdc@021b0000 { /* MMDC0 */
 736                                 compatible = "fsl,imx6q-mmdc";
 737                                 reg = <0x021b0000 0x4000>;
 738                         };
 739
 740                         mmdc@021b4000 { /* MMDC1 */
 741                                 reg = <0x021b4000 0x4000>;
 742                         };
 743
 744                         weim@021b8000 {
 745                                 reg = <0x021b8000 0x4000>;
 746                                 interrupts = <0 14 0x04>;
 747                         };
 748
 749                         ocotp@021bc000 {
 750                                 reg = <0x021bc000 0x4000>;
 751                         };
 752
 753                         ocotp@021c0000 {
 754                                 reg = <0x021c0000 0x4000>;
 755                                 interrupts = <0 21 0x04>;
 756                         };
 757
 758                         tzasc@021d0000 { /* TZASC1 */
 759                                 reg = <0x021d0000 0x4000>;
 760                                 interrupts = <0 108 0x04>;
 761                         };
 762
 763                         tzasc@021d4000 { /* TZASC2 */
 764                                 reg = <0x021d4000 0x4000>;
 765                                 interrupts = <0 109 0x04>;
 766                         };
 767
 768                         audmux@021d8000 {
 769                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 770                                 reg = <0x021d8000 0x4000>;
 771                                 status = "disabled";
 772                         };
 773
 774                         mipi@021dc000 { /* MIPI-CSI */
 775                                 reg = <0x021dc000 0x4000>;
 776                         };
 777
 778                         mipi@021e0000 { /* MIPI-DSI */
 779                                 reg = <0x021e0000 0x4000>;
 780                         };
 781
 782                         vdoa@021e4000 {
 783                                 reg = <0x021e4000 0x4000>;
 784                                 interrupts = <0 18 0x04>;
 785                         };
 786
 787                         uart2: serial@021e8000 {
 788                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 789                                 reg = <0x021e8000 0x4000>;
 790                                 interrupts = <0 27 0x04>;
 791                                 status = "disabled";
 792                         };
 793
 794                         uart3: serial@021ec000 {
 795                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 796                                 reg = <0x021ec000 0x4000>;
 797                                 interrupts = <0 28 0x04>;
 798                                 status = "disabled";
 799                         };
 800
 801                         uart4: serial@021f0000 {
 802                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 803                                 reg = <0x021f0000 0x4000>;
 804                                 interrupts = <0 29 0x04>;
 805                                 status = "disabled";
 806                         };
 807
 808                         uart5: serial@021f4000 {
 809                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 810                                 reg = <0x021f4000 0x4000>;
 811                                 interrupts = <0 30 0x04>;
 812                                 status = "disabled";
 813                         };
 814                 };
 815         };
 816 };