arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include "imx6sl-pinfunc.h"
  12 #include <dt-bindings/clock/imx6sl-clock.h>
  13
  14 / {
  15         aliases {
  16                 serial0 = &uart1;
  17                 serial1 = &uart2;
  18                 serial2 = &uart3;
  19                 serial3 = &uart4;
  20                 serial4 = &uart5;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         compatible = "arm,cortex-a9";
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         next-level-cache = <&L2>;
  37                 };
  38         };
  39
  40         intc: interrupt-controller@00a01000 {
  41                 compatible = "arm,cortex-a9-gic";
  42                 #interrupt-cells = <3>;
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 interrupt-controller;
  46                 reg = <0x00a01000 0x1000>,
  47                       <0x00a00100 0x100>;
  48         };
  49
  50         clocks {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 ckil {
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <32768>;
  57                 };
  58
  59                 osc {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <24000000>;
  62                 };
  63         };
  64
  65         soc {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 compatible = "simple-bus";
  69                 interrupt-parent = <&intc>;
  70                 ranges;
  71
  72                 L2: l2-cache@00a02000 {
  73                         compatible = "arm,pl310-cache";
  74                         reg = <0x00a02000 0x1000>;
  75                         interrupts = <0 92 0x04>;
  76                         cache-unified;
  77                         cache-level = <2>;
  78                         arm,tag-latency = <4 2 3>;
  79                         arm,data-latency = <4 2 3>;
  80                 };
  81
  82                 pmu {
  83                         compatible = "arm,cortex-a9-pmu";
  84                         interrupts = <0 94 0x04>;
  85                 };
  86
  87                 aips1: aips-bus@02000000 {
  88                         compatible = "fsl,aips-bus", "simple-bus";
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         reg = <0x02000000 0x100000>;
  92                         ranges;
  93
  94                         spba: spba-bus@02000000 {
  95                                 compatible = "fsl,spba-bus", "simple-bus";
  96                                 #address-cells = <1>;
  97                                 #size-cells = <1>;
  98                                 reg = <0x02000000 0x40000>;
  99                                 ranges;
 100
 101                                 spdif: spdif@02004000 {
 102                                         reg = <0x02004000 0x4000>;
 103                                         interrupts = <0 52 0x04>;
 104                                 };
 105
 106                                 ecspi1: ecspi@02008000 {
 107                                         #address-cells = <1>;
 108                                         #size-cells = <0>;
 109                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 110                                         reg = <0x02008000 0x4000>;
 111                                         interrupts = <0 31 0x04>;
 112                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 113                                                  <&clks IMX6SL_CLK_ECSPI1>;
 114                                         clock-names = "ipg", "per";
 115                                         status = "disabled";
 116                                 };
 117
 118                                 ecspi2: ecspi@0200c000 {
 119                                         #address-cells = <1>;
 120                                         #size-cells = <0>;
 121                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 122                                         reg = <0x0200c000 0x4000>;
 123                                         interrupts = <0 32 0x04>;
 124                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 125                                                  <&clks IMX6SL_CLK_ECSPI2>;
 126                                         clock-names = "ipg", "per";
 127                                         status = "disabled";
 128                                 };
 129
 130                                 ecspi3: ecspi@02010000 {
 131                                         #address-cells = <1>;
 132                                         #size-cells = <0>;
 133                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 134                                         reg = <0x02010000 0x4000>;
 135                                         interrupts = <0 33 0x04>;
 136                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 137                                                  <&clks IMX6SL_CLK_ECSPI3>;
 138                                         clock-names = "ipg", "per";
 139                                         status = "disabled";
 140                                 };
 141
 142                                 ecspi4: ecspi@02014000 {
 143                                         #address-cells = <1>;
 144                                         #size-cells = <0>;
 145                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 146                                         reg = <0x02014000 0x4000>;
 147                                         interrupts = <0 34 0x04>;
 148                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 149                                                  <&clks IMX6SL_CLK_ECSPI4>;
 150                                         clock-names = "ipg", "per";
 151                                         status = "disabled";
 152                                 };
 153
 154                                 uart5: serial@02018000 {
 155                                         compatible = "fsl,imx6sl-uart",
 156                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 157                                         reg = <0x02018000 0x4000>;
 158                                         interrupts = <0 30 0x04>;
 159                                         clocks = <&clks IMX6SL_CLK_UART>,
 160                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 161                                         clock-names = "ipg", "per";
 162                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 163                                         dma-names = "rx", "tx";
 164                                         status = "disabled";
 165                                 };
 166
 167                                 uart1: serial@02020000 {
 168                                         compatible = "fsl,imx6sl-uart",
 169                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 170                                         reg = <0x02020000 0x4000>;
 171                                         interrupts = <0 26 0x04>;
 172                                         clocks = <&clks IMX6SL_CLK_UART>,
 173                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 174                                         clock-names = "ipg", "per";
 175                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 176                                         dma-names = "rx", "tx";
 177                                         status = "disabled";
 178                                 };
 179
 180                                 uart2: serial@02024000 {
 181                                         compatible = "fsl,imx6sl-uart",
 182                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 183                                         reg = <0x02024000 0x4000>;
 184                                         interrupts = <0 27 0x04>;
 185                                         clocks = <&clks IMX6SL_CLK_UART>,
 186                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 187                                         clock-names = "ipg", "per";
 188                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 189                                         dma-names = "rx", "tx";
 190                                         status = "disabled";
 191                                 };
 192
 193                                 ssi1: ssi@02028000 {
 194                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 195                                         reg = <0x02028000 0x4000>;
 196                                         interrupts = <0 46 0x04>;
 197                                         clocks = <&clks IMX6SL_CLK_SSI1>;
 198                                         dmas = <&sdma 37 1 0>,
 199                                                <&sdma 38 1 0>;
 200                                         dma-names = "rx", "tx";
 201                                         fsl,fifo-depth = <15>;
 202                                         status = "disabled";
 203                                 };
 204
 205                                 ssi2: ssi@0202c000 {
 206                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 207                                         reg = <0x0202c000 0x4000>;
 208                                         interrupts = <0 47 0x04>;
 209                                         clocks = <&clks IMX6SL_CLK_SSI2>;
 210                                         dmas = <&sdma 41 1 0>,
 211                                                <&sdma 42 1 0>;
 212                                         dma-names = "rx", "tx";
 213                                         fsl,fifo-depth = <15>;
 214                                         status = "disabled";
 215                                 };
 216
 217                                 ssi3: ssi@02030000 {
 218                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 219                                         reg = <0x02030000 0x4000>;
 220                                         interrupts = <0 48 0x04>;
 221                                         clocks = <&clks IMX6SL_CLK_SSI3>;
 222                                         dmas = <&sdma 45 1 0>,
 223                                                <&sdma 46 1 0>;
 224                                         dma-names = "rx", "tx";
 225                                         fsl,fifo-depth = <15>;
 226                                         status = "disabled";
 227                                 };
 228
 229                                 uart3: serial@02034000 {
 230                                         compatible = "fsl,imx6sl-uart",
 231                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 232                                         reg = <0x02034000 0x4000>;
 233                                         interrupts = <0 28 0x04>;
 234                                         clocks = <&clks IMX6SL_CLK_UART>,
 235                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 236                                         clock-names = "ipg", "per";
 237                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 238                                         dma-names = "rx", "tx";
 239                                         status = "disabled";
 240                                 };
 241
 242                                 uart4: serial@02038000 {
 243                                         compatible = "fsl,imx6sl-uart",
 244                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 245                                         reg = <0x02038000 0x4000>;
 246                                         interrupts = <0 29 0x04>;
 247                                         clocks = <&clks IMX6SL_CLK_UART>,
 248                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 249                                         clock-names = "ipg", "per";
 250                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 251                                         dma-names = "rx", "tx";
 252                                         status = "disabled";
 253                                 };
 254                         };
 255
 256                         pwm1: pwm@02080000 {
 257                                 #pwm-cells = <2>;
 258                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 259                                 reg = <0x02080000 0x4000>;
 260                                 interrupts = <0 83 0x04>;
 261                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 262                                          <&clks IMX6SL_CLK_PWM1>;
 263                                 clock-names = "ipg", "per";
 264                         };
 265
 266                         pwm2: pwm@02084000 {
 267                                 #pwm-cells = <2>;
 268                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 269                                 reg = <0x02084000 0x4000>;
 270                                 interrupts = <0 84 0x04>;
 271                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 272                                          <&clks IMX6SL_CLK_PWM2>;
 273                                 clock-names = "ipg", "per";
 274                         };
 275
 276                         pwm3: pwm@02088000 {
 277                                 #pwm-cells = <2>;
 278                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 279                                 reg = <0x02088000 0x4000>;
 280                                 interrupts = <0 85 0x04>;
 281                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 282                                          <&clks IMX6SL_CLK_PWM3>;
 283                                 clock-names = "ipg", "per";
 284                         };
 285
 286                         pwm4: pwm@0208c000 {
 287                                 #pwm-cells = <2>;
 288                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 289                                 reg = <0x0208c000 0x4000>;
 290                                 interrupts = <0 86 0x04>;
 291                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 292                                          <&clks IMX6SL_CLK_PWM4>;
 293                                 clock-names = "ipg", "per";
 294                         };
 295
 296                         gpt: gpt@02098000 {
 297                                 compatible = "fsl,imx6sl-gpt";
 298                                 reg = <0x02098000 0x4000>;
 299                                 interrupts = <0 55 0x04>;
 300                                 clocks = <&clks IMX6SL_CLK_GPT>,
 301                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 302                                 clock-names = "ipg", "per";
 303                         };
 304
 305                         gpio1: gpio@0209c000 {
 306                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 307                                 reg = <0x0209c000 0x4000>;
 308                                 interrupts = <0 66 0x04 0 67 0x04>;
 309                                 gpio-controller;
 310                                 #gpio-cells = <2>;
 311                                 interrupt-controller;
 312                                 #interrupt-cells = <2>;
 313                         };
 314
 315                         gpio2: gpio@020a0000 {
 316                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 317                                 reg = <0x020a0000 0x4000>;
 318                                 interrupts = <0 68 0x04 0 69 0x04>;
 319                                 gpio-controller;
 320                                 #gpio-cells = <2>;
 321                                 interrupt-controller;
 322                                 #interrupt-cells = <2>;
 323                         };
 324
 325                         gpio3: gpio@020a4000 {
 326                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 327                                 reg = <0x020a4000 0x4000>;
 328                                 interrupts = <0 70 0x04 0 71 0x04>;
 329                                 gpio-controller;
 330                                 #gpio-cells = <2>;
 331                                 interrupt-controller;
 332                                 #interrupt-cells = <2>;
 333                         };
 334
 335                         gpio4: gpio@020a8000 {
 336                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 337                                 reg = <0x020a8000 0x4000>;
 338                                 interrupts = <0 72 0x04 0 73 0x04>;
 339                                 gpio-controller;
 340                                 #gpio-cells = <2>;
 341                                 interrupt-controller;
 342                                 #interrupt-cells = <2>;
 343                         };
 344
 345                         gpio5: gpio@020ac000 {
 346                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 347                                 reg = <0x020ac000 0x4000>;
 348                                 interrupts = <0 74 0x04 0 75 0x04>;
 349                                 gpio-controller;
 350                                 #gpio-cells = <2>;
 351                                 interrupt-controller;
 352                                 #interrupt-cells = <2>;
 353                         };
 354
 355                         kpp: kpp@020b8000 {
 356                                 reg = <0x020b8000 0x4000>;
 357                                 interrupts = <0 82 0x04>;
 358                         };
 359
 360                         wdog1: wdog@020bc000 {
 361                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 362                                 reg = <0x020bc000 0x4000>;
 363                                 interrupts = <0 80 0x04>;
 364                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 365                         };
 366
 367                         wdog2: wdog@020c0000 {
 368                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 369                                 reg = <0x020c0000 0x4000>;
 370                                 interrupts = <0 81 0x04>;
 371                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 372                                 status = "disabled";
 373                         };
 374
 375                         clks: ccm@020c4000 {
 376                                 compatible = "fsl,imx6sl-ccm";
 377                                 reg = <0x020c4000 0x4000>;
 378                                 interrupts = <0 87 0x04 0 88 0x04>;
 379                                 #clock-cells = <1>;
 380                         };
 381
 382                         anatop: anatop@020c8000 {
 383                                 compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
 384                                 reg = <0x020c8000 0x1000>;
 385                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 386
 387                                 regulator-1p1@110 {
 388                                         compatible = "fsl,anatop-regulator";
 389                                         regulator-name = "vdd1p1";
 390                                         regulator-min-microvolt = <800000>;
 391                                         regulator-max-microvolt = <1375000>;
 392                                         regulator-always-on;
 393                                         anatop-reg-offset = <0x110>;
 394                                         anatop-vol-bit-shift = <8>;
 395                                         anatop-vol-bit-width = <5>;
 396                                         anatop-min-bit-val = <4>;
 397                                         anatop-min-voltage = <800000>;
 398                                         anatop-max-voltage = <1375000>;
 399                                 };
 400
 401                                 regulator-3p0@120 {
 402                                         compatible = "fsl,anatop-regulator";
 403                                         regulator-name = "vdd3p0";
 404                                         regulator-min-microvolt = <2800000>;
 405                                         regulator-max-microvolt = <3150000>;
 406                                         regulator-always-on;
 407                                         anatop-reg-offset = <0x120>;
 408                                         anatop-vol-bit-shift = <8>;
 409                                         anatop-vol-bit-width = <5>;
 410                                         anatop-min-bit-val = <0>;
 411                                         anatop-min-voltage = <2625000>;
 412                                         anatop-max-voltage = <3400000>;
 413                                 };
 414
 415                                 regulator-2p5@130 {
 416                                         compatible = "fsl,anatop-regulator";
 417                                         regulator-name = "vdd2p5";
 418                                         regulator-min-microvolt = <2100000>;
 419                                         regulator-max-microvolt = <2850000>;
 420                                         regulator-always-on;
 421                                         anatop-reg-offset = <0x130>;
 422                                         anatop-vol-bit-shift = <8>;
 423                                         anatop-vol-bit-width = <5>;
 424                                         anatop-min-bit-val = <0>;
 425                                         anatop-min-voltage = <2100000>;
 426                                         anatop-max-voltage = <2850000>;
 427                                 };
 428
 429                                 reg_arm: regulator-vddcore@140 {
 430                                         compatible = "fsl,anatop-regulator";
 431                                         regulator-name = "cpu";
 432                                         regulator-min-microvolt = <725000>;
 433                                         regulator-max-microvolt = <1450000>;
 434                                         regulator-always-on;
 435                                         anatop-reg-offset = <0x140>;
 436                                         anatop-vol-bit-shift = <0>;
 437                                         anatop-vol-bit-width = <5>;
 438                                         anatop-delay-reg-offset = <0x170>;
 439                                         anatop-delay-bit-shift = <24>;
 440                                         anatop-delay-bit-width = <2>;
 441                                         anatop-min-bit-val = <1>;
 442                                         anatop-min-voltage = <725000>;
 443                                         anatop-max-voltage = <1450000>;
 444                                 };
 445
 446                                 reg_pu: regulator-vddpu@140 {
 447                                         compatible = "fsl,anatop-regulator";
 448                                         regulator-name = "vddpu";
 449                                         regulator-min-microvolt = <725000>;
 450                                         regulator-max-microvolt = <1450000>;
 451                                         regulator-always-on;
 452                                         anatop-reg-offset = <0x140>;
 453                                         anatop-vol-bit-shift = <9>;
 454                                         anatop-vol-bit-width = <5>;
 455                                         anatop-delay-reg-offset = <0x170>;
 456                                         anatop-delay-bit-shift = <26>;
 457                                         anatop-delay-bit-width = <2>;
 458                                         anatop-min-bit-val = <1>;
 459                                         anatop-min-voltage = <725000>;
 460                                         anatop-max-voltage = <1450000>;
 461                                 };
 462
 463                                 reg_soc: regulator-vddsoc@140 {
 464                                         compatible = "fsl,anatop-regulator";
 465                                         regulator-name = "vddsoc";
 466                                         regulator-min-microvolt = <725000>;
 467                                         regulator-max-microvolt = <1450000>;
 468                                         regulator-always-on;
 469                                         anatop-reg-offset = <0x140>;
 470                                         anatop-vol-bit-shift = <18>;
 471                                         anatop-vol-bit-width = <5>;
 472                                         anatop-delay-reg-offset = <0x170>;
 473                                         anatop-delay-bit-shift = <28>;
 474                                         anatop-delay-bit-width = <2>;
 475                                         anatop-min-bit-val = <1>;
 476                                         anatop-min-voltage = <725000>;
 477                                         anatop-max-voltage = <1450000>;
 478                                 };
 479                         };
 480
 481                         usbphy1: usbphy@020c9000 {
 482                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 483                                 reg = <0x020c9000 0x1000>;
 484                                 interrupts = <0 44 0x04>;
 485                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 486                         };
 487
 488                         usbphy2: usbphy@020ca000 {
 489                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 490                                 reg = <0x020ca000 0x1000>;
 491                                 interrupts = <0 45 0x04>;
 492                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 493                         };
 494
 495                         snvs@020cc000 {
 496                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 497                                 #address-cells = <1>;
 498                                 #size-cells = <1>;
 499                                 ranges = <0 0x020cc000 0x4000>;
 500
 501                                 snvs-rtc-lp@34 {
 502                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 503                                         reg = <0x34 0x58>;
 504                                         interrupts = <0 19 0x04 0 20 0x04>;
 505                                 };
 506                         };
 507
 508                         epit1: epit@020d0000 {
 509                                 reg = <0x020d0000 0x4000>;
 510                                 interrupts = <0 56 0x04>;
 511                         };
 512
 513                         epit2: epit@020d4000 {
 514                                 reg = <0x020d4000 0x4000>;
 515                                 interrupts = <0 57 0x04>;
 516                         };
 517
 518                         src: src@020d8000 {
 519                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 520                                 reg = <0x020d8000 0x4000>;
 521                                 interrupts = <0 91 0x04 0 96 0x04>;
 522                                 #reset-cells = <1>;
 523                         };
 524
 525                         gpc: gpc@020dc000 {
 526                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 527                                 reg = <0x020dc000 0x4000>;
 528                                 interrupts = <0 89 0x04>;
 529                         };
 530
 531                         gpr: iomuxc-gpr@020e0000 {
 532                                 compatible = "fsl,imx6sl-iomuxc-gpr", "syscon";
 533                                 reg = <0x020e0000 0x38>;
 534                         };
 535
 536                         iomuxc: iomuxc@020e0000 {
 537                                 compatible = "fsl,imx6sl-iomuxc";
 538                                 reg = <0x020e0000 0x4000>;
 539
 540                                 fec {
 541                                         pinctrl_fec_1: fecgrp-1 {
 542                                                 fsl,pins = <
 543                                                         MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
 544                                                         MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
 545                                                         MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
 546                                                         MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
 547                                                         MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
 548                                                         MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
 549                                                         MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
 550                                                         MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
 551                                                         MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
 552                                                 >;
 553                                         };
 554                                 };
 555
 556                                 uart1 {
 557                                         pinctrl_uart1_1: uart1grp-1 {
 558                                                 fsl,pins = <
 559                                                         MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
 560                                                         MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
 561                                                 >;
 562                                         };
 563                                 };
 564
 565                                 usdhc1 {
 566                                         pinctrl_usdhc1_1: usdhc1grp-1 {
 567                                                 fsl,pins = <
 568                                                         MX6SL_PAD_SD1_CMD__SD1_CMD    0x17059
 569                                                         MX6SL_PAD_SD1_CLK__SD1_CLK    0x10059
 570                                                         MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
 571                                                         MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
 572                                                         MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
 573                                                         MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
 574                                                         MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
 575                                                         MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
 576                                                         MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
 577                                                         MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
 578                                                 >;
 579                                         };
 580                                 };
 581
 582                                 usdhc2 {
 583                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 584                                                 fsl,pins = <
 585                                                         MX6SL_PAD_SD2_CMD__SD2_CMD    0x17059
 586                                                         MX6SL_PAD_SD2_CLK__SD2_CLK    0x10059
 587                                                         MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 588                                                         MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 589                                                         MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 590                                                         MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 591                                                 >;
 592                                         };
 593                                 };
 594
 595                                 usdhc3 {
 596                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 597                                                 fsl,pins = <
 598                                                         MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
 599                                                         MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
 600                                                         MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 601                                                         MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 602                                                         MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 603                                                         MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 604                                                 >;
 605                                         };
 606                                 };
 607                         };
 608
 609                         csi: csi@020e4000 {
 610                                 reg = <0x020e4000 0x4000>;
 611                                 interrupts = <0 7 0x04>;
 612                         };
 613
 614                         spdc: spdc@020e8000 {
 615                                 reg = <0x020e8000 0x4000>;
 616                                 interrupts = <0 6 0x04>;
 617                         };
 618
 619                         sdma: sdma@020ec000 {
 620                                 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
 621                                 reg = <0x020ec000 0x4000>;
 622                                 interrupts = <0 2 0x04>;
 623                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 624                                          <&clks IMX6SL_CLK_SDMA>;
 625                                 clock-names = "ipg", "ahb";
 626                                 #dma-cells = <3>;
 627                                 /* imx6sl reuses imx6q sdma firmware */
 628                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 629                         };
 630
 631                         pxp: pxp@020f0000 {
 632                                 reg = <0x020f0000 0x4000>;
 633                                 interrupts = <0 98 0x04>;
 634                         };
 635
 636                         epdc: epdc@020f4000 {
 637                                 reg = <0x020f4000 0x4000>;
 638                                 interrupts = <0 97 0x04>;
 639                         };
 640
 641                         lcdif: lcdif@020f8000 {
 642                                 reg = <0x020f8000 0x4000>;
 643                                 interrupts = <0 39 0x04>;
 644                         };
 645
 646                         dcp: dcp@020fc000 {
 647                                 reg = <0x020fc000 0x4000>;
 648                                 interrupts = <0 99 0x04>;
 649                         };
 650                 };
 651
 652                 aips2: aips-bus@02100000 {
 653                         compatible = "fsl,aips-bus", "simple-bus";
 654                         #address-cells = <1>;
 655                         #size-cells = <1>;
 656                         reg = <0x02100000 0x100000>;
 657                         ranges;
 658
 659                         usbotg1: usb@02184000 {
 660                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 661                                 reg = <0x02184000 0x200>;
 662                                 interrupts = <0 43 0x04>;
 663                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 664                                 fsl,usbphy = <&usbphy1>;
 665                                 fsl,usbmisc = <&usbmisc 0>;
 666                                 status = "disabled";
 667                         };
 668
 669                         usbotg2: usb@02184200 {
 670                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 671                                 reg = <0x02184200 0x200>;
 672                                 interrupts = <0 40 0x04>;
 673                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 674                                 fsl,usbphy = <&usbphy2>;
 675                                 fsl,usbmisc = <&usbmisc 1>;
 676                                 status = "disabled";
 677                         };
 678
 679                         usbh: usb@02184400 {
 680                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 681                                 reg = <0x02184400 0x200>;
 682                                 interrupts = <0 42 0x04>;
 683                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 684                                 fsl,usbmisc = <&usbmisc 2>;
 685                                 status = "disabled";
 686                         };
 687
 688                         usbmisc: usbmisc@02184800 {
 689                                 #index-cells = <1>;
 690                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 691                                 reg = <0x02184800 0x200>;
 692                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 693                         };
 694
 695                         fec: ethernet@02188000 {
 696                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 697                                 reg = <0x02188000 0x4000>;
 698                                 interrupts = <0 114 0x04>;
 699                                 clocks = <&clks IMX6SL_CLK_ENET_REF>,
 700                                          <&clks IMX6SL_CLK_ENET_REF>;
 701                                 clock-names = "ipg", "ahb";
 702                                 status = "disabled";
 703                         };
 704
 705                         usdhc1: usdhc@02190000 {
 706                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 707                                 reg = <0x02190000 0x4000>;
 708                                 interrupts = <0 22 0x04>;
 709                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 710                                          <&clks IMX6SL_CLK_USDHC1>,
 711                                          <&clks IMX6SL_CLK_USDHC1>;
 712                                 clock-names = "ipg", "ahb", "per";
 713                                 bus-width = <4>;
 714                                 status = "disabled";
 715                         };
 716
 717                         usdhc2: usdhc@02194000 {
 718                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 719                                 reg = <0x02194000 0x4000>;
 720                                 interrupts = <0 23 0x04>;
 721                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 722                                          <&clks IMX6SL_CLK_USDHC2>,
 723                                          <&clks IMX6SL_CLK_USDHC2>;
 724                                 clock-names = "ipg", "ahb", "per";
 725                                 bus-width = <4>;
 726                                 status = "disabled";
 727                         };
 728
 729                         usdhc3: usdhc@02198000 {
 730                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 731                                 reg = <0x02198000 0x4000>;
 732                                 interrupts = <0 24 0x04>;
 733                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 734                                          <&clks IMX6SL_CLK_USDHC3>,
 735                                          <&clks IMX6SL_CLK_USDHC3>;
 736                                 clock-names = "ipg", "ahb", "per";
 737                                 bus-width = <4>;
 738                                 status = "disabled";
 739                         };
 740
 741                         usdhc4: usdhc@0219c000 {
 742                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 743                                 reg = <0x0219c000 0x4000>;
 744                                 interrupts = <0 25 0x04>;
 745                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 746                                          <&clks IMX6SL_CLK_USDHC4>,
 747                                          <&clks IMX6SL_CLK_USDHC4>;
 748                                 clock-names = "ipg", "ahb", "per";
 749                                 bus-width = <4>;
 750                                 status = "disabled";
 751                         };
 752
 753                         i2c1: i2c@021a0000 {
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 757                                 reg = <0x021a0000 0x4000>;
 758                                 interrupts = <0 36 0x04>;
 759                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 760                                 status = "disabled";
 761                         };
 762
 763                         i2c2: i2c@021a4000 {
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 767                                 reg = <0x021a4000 0x4000>;
 768                                 interrupts = <0 37 0x04>;
 769                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 770                                 status = "disabled";
 771                         };
 772
 773                         i2c3: i2c@021a8000 {
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 777                                 reg = <0x021a8000 0x4000>;
 778                                 interrupts = <0 38 0x04>;
 779                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 780                                 status = "disabled";
 781                         };
 782
 783                         mmdc: mmdc@021b0000 {
 784                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 785                                 reg = <0x021b0000 0x4000>;
 786                         };
 787
 788                         rngb: rngb@021b4000 {
 789                                 reg = <0x021b4000 0x4000>;
 790                                 interrupts = <0 5 0x04>;
 791                         };
 792
 793                         weim: weim@021b8000 {
 794                                 reg = <0x021b8000 0x4000>;
 795                                 interrupts = <0 14 0x04>;
 796                         };
 797
 798                         ocotp: ocotp@021bc000 {
 799                                 compatible = "fsl,imx6sl-ocotp";
 800                                 reg = <0x021bc000 0x4000>;
 801                         };
 802
 803                         audmux: audmux@021d8000 {
 804                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 805                                 reg = <0x021d8000 0x4000>;
 806                                 status = "disabled";
 807                         };
 808                 };
 809         };
 810 };