arch/arm/boot/dts/imx6ul-14x14-evk.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "imx6ul.dtsi"
  12
  13 / {
  14         model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
  15         compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
  16
  17         chosen {
  18                 stdout-path = &uart1;
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x20000000>;
  23         };
  24
  25         backlight {
  26                 compatible = "pwm-backlight";
  27                 pwms = <&pwm1 0 5000000>;
  28                 brightness-levels = <0 4 8 16 32 64 128 255>;
  29                 default-brightness-level = <6>;
  30                 status = "okay";
  31         };
  32
  33         regulators {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 reg_sd1_vmmc: sd1_regulator {
  39                         compatible = "regulator-fixed";
  40                         regulator-name = "VSD_3V3";
  41                         regulator-min-microvolt = <3300000>;
  42                         regulator-max-microvolt = <3300000>;
  43                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  44                         enable-active-high;
  45                 };
  46         };
  47
  48         sound {
  49                 compatible = "simple-audio-card";
  50                 simple-audio-card,name = "mx6ul-wm8960";
  51                 simple-audio-card,format = "i2s";
  52                 simple-audio-card,bitclock-master = <&dailink_master>;
  53                 simple-audio-card,frame-master = <&dailink_master>;
  54                 simple-audio-card,widgets =
  55                         "Microphone", "Mic Jack",
  56                         "Line", "Line In",
  57                         "Line", "Line Out",
  58                         "Speaker", "Speaker",
  59                         "Headphone", "Headphone Jack";
  60                 simple-audio-card,routing =
  61                         "Headphone Jack", "HP_L",
  62                         "Headphone Jack", "HP_R",
  63                         "Speaker", "SPK_LP",
  64                         "Speaker", "SPK_LN",
  65                         "Speaker", "SPK_RP",
  66                         "Speaker", "SPK_RN",
  67                         "LINPUT1", "Mic Jack",
  68                         "LINPUT3", "Mic Jack",
  69                         "RINPUT1", "Mic Jack",
  70                         "RINPUT2", "Mic Jack";
  71
  72                 simple-audio-card,cpu {
  73                         sound-dai = <&sai2>;
  74                 };
  75
  76                 dailink_master: simple-audio-card,codec {
  77                         sound-dai = <&codec>;
  78                         clocks = <&clks IMX6UL_CLK_SAI2>;
  79                 };
  80         };
  81 };
  82
  83 &clks {
  84         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  85         assigned-clock-rates = <786432000>;
  86 };
  87
  88 &cpu0 {
  89         arm-supply = <&reg_arm>;
  90         soc-supply = <&reg_soc>;
  91 };
  92
  93 &i2c2 {
  94         clock_frequency = <100000>;
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_i2c2>;
  97         status = "okay";
  98
  99         codec: wm8960@1a {
 100                 #sound-dai-cells = <0>;
 101                 compatible = "wlf,wm8960";
 102                 reg = <0x1a>;
 103                 wlf,shared-lrclk;
 104         };
 105 };
 106
 107 &fec1 {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_enet1>;
 110         phy-mode = "rmii";
 111         phy-handle = <&ethphy0>;
 112         status = "okay";
 113 };
 114
 115 &fec2 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_enet2>;
 118         phy-mode = "rmii";
 119         phy-handle = <&ethphy1>;
 120         status = "okay";
 121
 122         mdio {
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125
 126                 ethphy0: ethernet-phy@2 {
 127                         reg = <2>;
 128                 };
 129
 130                 ethphy1: ethernet-phy@1 {
 131                         reg = <1>;
 132                 };
 133         };
 134 };
 135
 136
 137 &lcdif {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_lcdif_dat
 140                      &pinctrl_lcdif_ctrl>;
 141         display = <&display0>;
 142         status = "okay";
 143
 144         display0: display {
 145                 bits-per-pixel = <16>;
 146                 bus-width = <24>;
 147
 148                 display-timings {
 149                         native-mode = <&timing0>;
 150
 151                         timing0: timing0 {
 152                                 clock-frequency = <9200000>;
 153                                 hactive = <480>;
 154                                 vactive = <272>;
 155                                 hfront-porch = <8>;
 156                                 hback-porch = <4>;
 157                                 hsync-len = <41>;
 158                                 vback-porch = <2>;
 159                                 vfront-porch = <4>;
 160                                 vsync-len = <10>;
 161                                 hsync-active = <0>;
 162                                 vsync-active = <0>;
 163                                 de-active = <1>;
 164                                 pixelclk-active = <0>;
 165                         };
 166                 };
 167         };
 168 };
 169
 170 &pwm1 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_pwm1>;
 173         status = "okay";
 174 };
 175
 176 &qspi {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_qspi>;
 179         status = "okay";
 180
 181         flash0: n25q256a@0 {
 182                 #address-cells = <1>;
 183                 #size-cells = <1>;
 184                 compatible = "micron,n25q256a";
 185                 spi-max-frequency = <29000000>;
 186                 reg = <0>;
 187         };
 188 };
 189
 190 &sai2 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_sai2>;
 193         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 194                           <&clks IMX6UL_CLK_SAI2>;
 195         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 196         assigned-clock-rates = <0>, <12288000>;
 197         fsl,sai-mclk-direction-output;
 198         status = "okay";
 199 };
 200
 201 &snvs_poweroff {
 202         status = "okay";
 203 };
 204
 205 &tsc {
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_tsc>;
 208         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 209         measure-delay-time = <0xffff>;
 210         pre-charge-time = <0xfff>;
 211         status = "okay";
 212 };
 213
 214 &uart1 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_uart1>;
 217         status = "okay";
 218 };
 219
 220 &uart2 {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_uart2>;
 223         uart-has-rtscts;
 224         status = "okay";
 225 };
 226
 227 &usbotg1 {
 228         dr_mode = "peripheral";
 229         status = "okay";
 230 };
 231
 232 &usbotg2 {
 233         dr_mode = "host";
 234         disable-over-current;
 235         status = "okay";
 236 };
 237
 238 &usdhc1 {
 239         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 240         pinctrl-0 = <&pinctrl_usdhc1>;
 241         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 242         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 243         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 244         keep-power-in-suspend;
 245         wakeup-source;
 246         vmmc-supply = <&reg_sd1_vmmc>;
 247         status = "okay";
 248 };
 249
 250 &usdhc2 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_usdhc2>;
 253         no-1-8-v;
 254         keep-power-in-suspend;
 255         wakeup-source;
 256         status = "okay";
 257 };
 258
 259 &iomuxc {
 260         pinctrl-names = "default";
 261
 262         pinctrl_csi1: csi1grp {
 263                 fsl,pins = <
 264                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 265                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 266                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 267                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 268                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 269                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 270                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 271                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 272                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 273                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 274                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 275                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 276                 >;
 277         };
 278
 279         pinctrl_enet1: enet1grp {
 280                 fsl,pins = <
 281                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 282                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 283                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 284                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 285                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 286                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 287                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 288                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 289                 >;
 290         };
 291
 292         pinctrl_enet2: enet2grp {
 293                 fsl,pins = <
 294                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 295                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 296                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 297                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 298                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 299                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 300                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 301                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 302                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 303                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 304                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x17059
 305                 >;
 306         };
 307
 308         pinctrl_flexcan1: flexcan1grp{
 309                 fsl,pins = <
 310                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 311                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 312                 >;
 313         };
 314
 315         pinctrl_flexcan2: flexcan2grp{
 316                 fsl,pins = <
 317                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 318                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 319                 >;
 320         };
 321
 322         pinctrl_i2c1: i2c1grp {
 323                 fsl,pins = <
 324                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 325                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 326                 >;
 327         };
 328
 329         pinctrl_i2c2: i2c2grp {
 330                 fsl,pins = <
 331                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 332                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 333                 >;
 334         };
 335
 336         pinctrl_lcdif_dat: lcdifdatgrp {
 337                 fsl,pins = <
 338                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 339                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 340                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 341                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 342                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 343                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 344                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 345                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 346                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 347                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 348                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 349                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 350                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 351                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 352                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 353                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 354                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 355                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 356                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 357                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 358                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 359                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 360                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 361                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 362                 >;
 363         };
 364
 365         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 366                 fsl,pins = <
 367                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 368                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 369                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 370                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 371                         /* used for lcd reset */
 372                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 373                 >;
 374         };
 375
 376         pinctrl_qspi: qspigrp {
 377                 fsl,pins = <
 378                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 379                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 380                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 381                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 382                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 383                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 384                 >;
 385         };
 386
 387         pinctrl_sai2: sai2grp {
 388                 fsl,pins = <
 389                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 390                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 391                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 392                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 393                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 394                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
 395                 >;
 396         };
 397
 398         pinctrl_pwm1: pwm1grp {
 399                 fsl,pins = <
 400                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 401                 >;
 402         };
 403
 404         pinctrl_sim2: sim2grp {
 405                 fsl,pins = <
 406                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 407                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 408                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 409                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 410                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 411                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 412                 >;
 413         };
 414
 415         pinctrl_tsc: tscgrp {
 416                 fsl,pins = <
 417                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
 418                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
 419                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
 420                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
 421                 >;
 422         };
 423
 424         pinctrl_uart1: uart1grp {
 425                 fsl,pins = <
 426                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 427                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 428                 >;
 429         };
 430
 431         pinctrl_uart2: uart2grp {
 432                 fsl,pins = <
 433                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 434                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 435                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 436                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 437                 >;
 438         };
 439
 440         pinctrl_usdhc1: usdhc1grp {
 441                 fsl,pins = <
 442                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 443                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 444                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 445                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 446                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 447                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 448                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 449                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 450                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 451                 >;
 452         };
 453
 454         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 455                 fsl,pins = <
 456                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 457                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 458                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 459                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 460                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 461                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 462
 463                 >;
 464         };
 465
 466         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 467                 fsl,pins = <
 468                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 469                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 470                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 471                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 472                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 473                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 474                 >;
 475         };
 476
 477         pinctrl_usdhc2: usdhc2grp {
 478                 fsl,pins = <
 479                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 480                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 481                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 482                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 483                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 484                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 485                 >;
 486         };
 487 };