arch/arm/boot/dts/integratorcp.dts

   1 /*
   2  * Device Tree for the ARM Integrator/CP platform
   3  */
   4
   5 /dts-v1/;
   6 /include/ "integrator.dtsi"
   7
   8 / {
   9         model = "ARM Integrator/CP";
  10         compatible = "arm,integrator-cp";
  11
  12         aliases {
  13                 arm,timer-primary = &timer2;
  14                 arm,timer-secondary = &timer1;
  15         };
  16
  17         chosen {
  18                 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
  19         };
  20
  21         cpcon {
  22                 /* CP controller registers */
  23                 reg = <0xcb000000 0x100>;
  24         };
  25
  26         timer0: timer@13000000 {
  27                 compatible = "arm,integrator-cp-timer";
  28         };
  29
  30         timer1: timer@13000100 {
  31                 compatible = "arm,integrator-cp-timer";
  32         };
  33
  34         timer2: timer@13000200 {
  35                 compatible = "arm,integrator-cp-timer";
  36         };
  37
  38         pic: pic@14000000 {
  39                 valid-mask = <0x1fc003ff>;
  40         };
  41
  42         cic: cic@10000040 {
  43                 compatible = "arm,versatile-fpga-irq";
  44                 #interrupt-cells = <1>;
  45                 interrupt-controller;
  46                 reg = <0x10000040 0x100>;
  47                 clear-mask = <0xffffffff>;
  48                 valid-mask = <0x00000007>;
  49         };
  50
  51         sic: sic@ca000000 {
  52                 compatible = "arm,versatile-fpga-irq";
  53                 #interrupt-cells = <1>;
  54                 interrupt-controller;
  55                 reg = <0xca000000 0x100>;
  56                 clear-mask = <0x00000fff>;
  57                 valid-mask = <0x00000fff>;
  58         };
  59
  60         ethernet@c8000000 {
  61                 compatible = "smsc,lan91c111";
  62                 reg = <0xc8000000 0x10>;
  63                 interrupt-parent = <&pic>;
  64                 interrupts = <27>;
  65         };
  66
  67         fpga {
  68                 /*
  69                  * These PrimeCells are at the same location and using
  70                  * the same interrupts in all Integrators, but in the CP
  71                  * slightly newer versions are deployed.
  72                  */
  73                 rtc@15000000 {
  74                         compatible = "arm,pl031", "arm,primecell";
  75                 };
  76
  77                 uart@16000000 {
  78                         compatible = "arm,pl011", "arm,primecell";
  79                 };
  80
  81                 uart@17000000 {
  82                         compatible = "arm,pl011", "arm,primecell";
  83                 };
  84
  85                 kmi@18000000 {
  86                         compatible = "arm,pl050", "arm,primecell";
  87                 };
  88
  89                 kmi@19000000 {
  90                         compatible = "arm,pl050", "arm,primecell";
  91                 };
  92
  93                 /*
  94                  * These PrimeCells are only available on the Integrator/CP
  95                  */
  96                 mmc@1c000000 {
  97                         compatible = "arm,pl180", "arm,primecell";
  98                         reg = <0x1c000000 0x1000>;
  99                         interrupts = <23 24>;
 100                         max-frequency = <515633>;
 101                 };
 102
 103                 aaci@1d000000 {
 104                         compatible = "arm,pl041", "arm,primecell";
 105                         reg = <0x1d000000 0x1000>;
 106                         interrupts = <25>;
 107                 };
 108
 109                 clcd@c0000000 {
 110                         compatible = "arm,pl110", "arm,primecell";
 111                         reg = <0xC0000000 0x1000>;
 112                         interrupts = <22>;
 113                 };
 114         };
 115 };