arch/arm/boot/dts/mmp2.dtsi

   1 /*
   2  *  Copyright (C) 2012 Marvell Technology Group Ltd.
   3  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License version 2 as
   7  *  publishhed by the Free Software Foundation.
   8  */
   9
  10 /include/ "skeleton.dtsi"
  11
  12 / {
  13         aliases {
  14                 serial0 = &uart1;
  15                 serial1 = &uart2;
  16                 serial2 = &uart3;
  17                 serial3 = &uart4;
  18                 i2c0 = &twsi1;
  19                 i2c1 = &twsi2;
  20         };
  21
  22         soc {
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 compatible = "simple-bus";
  26                 interrupt-parent = <&intc>;
  27                 ranges;
  28
  29                 axi@d4200000 {  /* AXI */
  30                         compatible = "mrvl,axi-bus", "simple-bus";
  31                         #address-cells = <1>;
  32                         #size-cells = <1>;
  33                         reg = <0xd4200000 0x00200000>;
  34                         ranges;
  35
  36                         intc: interrupt-controller@d4282000 {
  37                                 compatible = "mrvl,mmp2-intc";
  38                                 interrupt-controller;
  39                                 #interrupt-cells = <1>;
  40                                 reg = <0xd4282000 0x1000>;
  41                                 mrvl,intc-nr-irqs = <64>;
  42                         };
  43
  44                         intcmux4@d4282150 {
  45                                 compatible = "mrvl,mmp2-mux-intc";
  46                                 interrupts = <4>;
  47                                 interrupt-controller;
  48                                 #interrupt-cells = <1>;
  49                                 reg = <0x150 0x4>, <0x168 0x4>;
  50                                 reg-names = "mux status", "mux mask";
  51                                 mrvl,intc-nr-irqs = <2>;
  52                         };
  53
  54                         intcmux5: interrupt-controller@d4282154 {
  55                                 compatible = "mrvl,mmp2-mux-intc";
  56                                 interrupts = <5>;
  57                                 interrupt-controller;
  58                                 #interrupt-cells = <1>;
  59                                 reg = <0x154 0x4>, <0x16c 0x4>;
  60                                 reg-names = "mux status", "mux mask";
  61                                 mrvl,intc-nr-irqs = <2>;
  62                                 mrvl,clr-mfp-irq = <1>;
  63                         };
  64
  65                         intcmux9: interrupt-controller@d4282180 {
  66                                 compatible = "mrvl,mmp2-mux-intc";
  67                                 interrupts = <9>;
  68                                 interrupt-controller;
  69                                 #interrupt-cells = <1>;
  70                                 reg = <0x180 0x4>, <0x17c 0x4>;
  71                                 reg-names = "mux status", "mux mask";
  72                                 mrvl,intc-nr-irqs = <3>;
  73                         };
  74
  75                         intcmux17: interrupt-controller@d4282158 {
  76                                 compatible = "mrvl,mmp2-mux-intc";
  77                                 interrupts = <17>;
  78                                 interrupt-controller;
  79                                 #interrupt-cells = <1>;
  80                                 reg = <0x158 0x4>, <0x170 0x4>;
  81                                 reg-names = "mux status", "mux mask";
  82                                 mrvl,intc-nr-irqs = <5>;
  83                         };
  84
  85                         intcmux35: interrupt-controller@d428215c {
  86                                 compatible = "mrvl,mmp2-mux-intc";
  87                                 interrupts = <35>;
  88                                 interrupt-controller;
  89                                 #interrupt-cells = <1>;
  90                                 reg = <0x15c 0x4>, <0x174 0x4>;
  91                                 reg-names = "mux status", "mux mask";
  92                                 mrvl,intc-nr-irqs = <15>;
  93                         };
  94
  95                         intcmux51: interrupt-controller@d4282160 {
  96                                 compatible = "mrvl,mmp2-mux-intc";
  97                                 interrupts = <51>;
  98                                 interrupt-controller;
  99                                 #interrupt-cells = <1>;
 100                                 reg = <0x160 0x4>, <0x178 0x4>;
 101                                 reg-names = "mux status", "mux mask";
 102                                 mrvl,intc-nr-irqs = <2>;
 103                         };
 104
 105                         intcmux55: interrupt-controller@d4282188 {
 106                                 compatible = "mrvl,mmp2-mux-intc";
 107                                 interrupts = <55>;
 108                                 interrupt-controller;
 109                                 #interrupt-cells = <1>;
 110                                 reg = <0x188 0x4>, <0x184 0x4>;
 111                                 reg-names = "mux status", "mux mask";
 112                                 mrvl,intc-nr-irqs = <2>;
 113                         };
 114                 };
 115
 116                 apb@d4000000 {  /* APB */
 117                         compatible = "mrvl,apb-bus", "simple-bus";
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120                         reg = <0xd4000000 0x00200000>;
 121                         ranges;
 122
 123                         timer0: timer@d4014000 {
 124                                 compatible = "mrvl,mmp-timer";
 125                                 reg = <0xd4014000 0x100>;
 126                                 interrupts = <13>;
 127                         };
 128
 129                         uart1: uart@d4030000 {
 130                                 compatible = "mrvl,mmp-uart";
 131                                 reg = <0xd4030000 0x1000>;
 132                                 interrupts = <27>;
 133                                 status = "disabled";
 134                         };
 135
 136                         uart2: uart@d4017000 {
 137                                 compatible = "mrvl,mmp-uart";
 138                                 reg = <0xd4017000 0x1000>;
 139                                 interrupts = <28>;
 140                                 status = "disabled";
 141                         };
 142
 143                         uart3: uart@d4018000 {
 144                                 compatible = "mrvl,mmp-uart";
 145                                 reg = <0xd4018000 0x1000>;
 146                                 interrupts = <24>;
 147                                 status = "disabled";
 148                         };
 149
 150                         uart4: uart@d4016000 {
 151                                 compatible = "mrvl,mmp-uart";
 152                                 reg = <0xd4016000 0x1000>;
 153                                 interrupts = <46>;
 154                                 status = "disabled";
 155                         };
 156
 157                         gpio@d4019000 {
 158                                 compatible = "mrvl,mmp-gpio";
 159                                 #address-cells = <1>;
 160                                 #size-cells = <1>;
 161                                 reg = <0xd4019000 0x1000>;
 162                                 gpio-controller;
 163                                 #gpio-cells = <2>;
 164                                 interrupts = <49>;
 165                                 interrupt-names = "gpio_mux";
 166                                 interrupt-controller;
 167                                 #interrupt-cells = <1>;
 168                                 ranges;
 169
 170                                 gcb0: gpio@d4019000 {
 171                                         reg = <0xd4019000 0x4>;
 172                                 };
 173
 174                                 gcb1: gpio@d4019004 {
 175                                         reg = <0xd4019004 0x4>;
 176                                 };
 177
 178                                 gcb2: gpio@d4019008 {
 179                                         reg = <0xd4019008 0x4>;
 180                                 };
 181
 182                                 gcb3: gpio@d4019100 {
 183                                         reg = <0xd4019100 0x4>;
 184                                 };
 185
 186                                 gcb4: gpio@d4019104 {
 187                                         reg = <0xd4019104 0x4>;
 188                                 };
 189
 190                                 gcb5: gpio@d4019108 {
 191                                         reg = <0xd4019108 0x4>;
 192                                 };
 193                         };
 194
 195                         twsi1: i2c@d4011000 {
 196                                 compatible = "mrvl,mmp-twsi";
 197                                 reg = <0xd4011000 0x1000>;
 198                                 interrupts = <7>;
 199                                 mrvl,i2c-fast-mode;
 200                                 status = "disabled";
 201                         };
 202
 203                         twsi2: i2c@d4025000 {
 204                                 compatible = "mrvl,mmp-twsi";
 205                                 reg = <0xd4025000 0x1000>;
 206                                 interrupts = <58>;
 207                                 status = "disabled";
 208                         };
 209
 210                         rtc: rtc@d4010000 {
 211                                 compatible = "mrvl,mmp-rtc";
 212                                 reg = <0xd4010000 0x1000>;
 213                                 interrupts = <1 0>;
 214                                 interrupt-names = "rtc 1Hz", "rtc alarm";
 215                                 interrupt-parent = <&intcmux5>;
 216                                 status = "disabled";
 217                         };
 218                 };
 219         };
 220 };