arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59         };
  60
  61         L2: l2-cache-controller@48242000 {
  62                 compatible = "arm,pl310-cache";
  63                 reg = <0x48242000 0x1000>;
  64                 cache-unified;
  65                 cache-level = <2>;
  66         };
  67
  68         local-timer@48240600 {
  69                 compatible = "arm,cortex-a9-twd-timer";
  70                 clocks = <&mpu_periphclk>;
  71                 reg = <0x48240600 0x20>;
  72                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  73         };
  74
  75         /*
  76          * The soc node represents the soc top level view. It is used for IPs
  77          * that are not memory mapped in the MPU view or for the MPU itself.
  78          */
  79         soc {
  80                 compatible = "ti,omap-infra";
  81                 mpu {
  82                         compatible = "ti,omap4-mpu";
  83                         ti,hwmods = "mpu";
  84                         sram = <&ocmcram>;
  85                 };
  86
  87                 dsp {
  88                         compatible = "ti,omap3-c64";
  89                         ti,hwmods = "dsp";
  90                 };
  91
  92                 iva {
  93                         compatible = "ti,ivahd";
  94                         ti,hwmods = "iva";
  95                 };
  96         };
  97
  98         /*
  99          * XXX: Use a flat representation of the OMAP4 interconnect.
 100          * The real OMAP interconnect network is quite complex.
 101          * Since it will not bring real advantage to represent that in DT for
 102          * the moment, just use a fake OCP bus entry to represent the whole bus
 103          * hierarchy.
 104          */
 105         ocp {
 106                 compatible = "ti,omap4-l3-noc", "simple-bus";
 107                 #address-cells = <1>;
 108                 #size-cells = <1>;
 109                 ranges;
 110                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 111                 reg = <0x44000000 0x1000>,
 112                       <0x44800000 0x2000>,
 113                       <0x45000000 0x1000>;
 114                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 115                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 116
 117                 cm1: cm1@4a004000 {
 118                         compatible = "ti,omap4-cm1";
 119                         reg = <0x4a004000 0x2000>;
 120
 121                         cm1_clocks: clocks {
 122                                 #address-cells = <1>;
 123                                 #size-cells = <0>;
 124                         };
 125
 126                         cm1_clockdomains: clockdomains {
 127                         };
 128                 };
 129
 130                 prm: prm@4a306000 {
 131                         compatible = "ti,omap4-prm";
 132                         reg = <0x4a306000 0x3000>;
 133                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 134
 135                         prm_clocks: clocks {
 136                                 #address-cells = <1>;
 137                                 #size-cells = <0>;
 138                         };
 139
 140                         prm_clockdomains: clockdomains {
 141                         };
 142                 };
 143
 144                 cm2: cm2@4a008000 {
 145                         compatible = "ti,omap4-cm2";
 146                         reg = <0x4a008000 0x3000>;
 147
 148                         cm2_clocks: clocks {
 149                                 #address-cells = <1>;
 150                                 #size-cells = <0>;
 151                         };
 152
 153                         cm2_clockdomains: clockdomains {
 154                         };
 155                 };
 156
 157                 scrm: scrm@4a30a000 {
 158                         compatible = "ti,omap4-scrm";
 159                         reg = <0x4a30a000 0x2000>;
 160
 161                         scrm_clocks: clocks {
 162                                 #address-cells = <1>;
 163                                 #size-cells = <0>;
 164                         };
 165
 166                         scrm_clockdomains: clockdomains {
 167                         };
 168                 };
 169
 170                 counter32k: counter@4a304000 {
 171                         compatible = "ti,omap-counter32k";
 172                         reg = <0x4a304000 0x20>;
 173                         ti,hwmods = "counter_32k";
 174                 };
 175
 176                 omap4_pmx_core: pinmux@4a100040 {
 177                         compatible = "ti,omap4-padconf", "pinctrl-single";
 178                         reg = <0x4a100040 0x0196>;
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         #interrupt-cells = <1>;
 182                         interrupt-controller;
 183                         pinctrl-single,register-width = <16>;
 184                         pinctrl-single,function-mask = <0x7fff>;
 185                 };
 186                 omap4_pmx_wkup: pinmux@4a31e040 {
 187                         compatible = "ti,omap4-padconf", "pinctrl-single";
 188                         reg = <0x4a31e040 0x0038>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         #interrupt-cells = <1>;
 192                         interrupt-controller;
 193                         pinctrl-single,register-width = <16>;
 194                         pinctrl-single,function-mask = <0x7fff>;
 195                 };
 196
 197                 omap4_padconf_global: tisyscon@4a1005a0 {
 198                         compatible = "syscon";
 199                         reg = <0x4a1005a0 0x170>;
 200                 };
 201
 202                 pbias_regulator: pbias_regulator {
 203                         compatible = "ti,pbias-omap";
 204                         reg = <0x60 0x4>;
 205                         syscon = <&omap4_padconf_global>;
 206                         pbias_mmc_reg: pbias_mmc_omap4 {
 207                                 regulator-name = "pbias_mmc_omap4";
 208                                 regulator-min-microvolt = <1800000>;
 209                                 regulator-max-microvolt = <3000000>;
 210                         };
 211                 };
 212
 213                 ocmcram: ocmcram@40304000 {
 214                         compatible = "mmio-sram";
 215                         reg = <0x40304000 0xa000>; /* 40k */
 216                 };
 217
 218                 sdma: dma-controller@4a056000 {
 219                         compatible = "ti,omap4430-sdma";
 220                         reg = <0x4a056000 0x1000>;
 221                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 225                         #dma-cells = <1>;
 226                         #dma-channels = <32>;
 227                         #dma-requests = <127>;
 228                 };
 229
 230                 gpio1: gpio@4a310000 {
 231                         compatible = "ti,omap4-gpio";
 232                         reg = <0x4a310000 0x200>;
 233                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 234                         ti,hwmods = "gpio1";
 235                         ti,gpio-always-on;
 236                         gpio-controller;
 237                         #gpio-cells = <2>;
 238                         interrupt-controller;
 239                         #interrupt-cells = <2>;
 240                 };
 241
 242                 gpio2: gpio@48055000 {
 243                         compatible = "ti,omap4-gpio";
 244                         reg = <0x48055000 0x200>;
 245                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 246                         ti,hwmods = "gpio2";
 247                         gpio-controller;
 248                         #gpio-cells = <2>;
 249                         interrupt-controller;
 250                         #interrupt-cells = <2>;
 251                 };
 252
 253                 gpio3: gpio@48057000 {
 254                         compatible = "ti,omap4-gpio";
 255                         reg = <0x48057000 0x200>;
 256                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 257                         ti,hwmods = "gpio3";
 258                         gpio-controller;
 259                         #gpio-cells = <2>;
 260                         interrupt-controller;
 261                         #interrupt-cells = <2>;
 262                 };
 263
 264                 gpio4: gpio@48059000 {
 265                         compatible = "ti,omap4-gpio";
 266                         reg = <0x48059000 0x200>;
 267                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 268                         ti,hwmods = "gpio4";
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271                         interrupt-controller;
 272                         #interrupt-cells = <2>;
 273                 };
 274
 275                 gpio5: gpio@4805b000 {
 276                         compatible = "ti,omap4-gpio";
 277                         reg = <0x4805b000 0x200>;
 278                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 279                         ti,hwmods = "gpio5";
 280                         gpio-controller;
 281                         #gpio-cells = <2>;
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                 };
 285
 286                 gpio6: gpio@4805d000 {
 287                         compatible = "ti,omap4-gpio";
 288                         reg = <0x4805d000 0x200>;
 289                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 290                         ti,hwmods = "gpio6";
 291                         gpio-controller;
 292                         #gpio-cells = <2>;
 293                         interrupt-controller;
 294                         #interrupt-cells = <2>;
 295                 };
 296
 297                 gpmc: gpmc@50000000 {
 298                         compatible = "ti,omap4430-gpmc";
 299                         reg = <0x50000000 0x1000>;
 300                         #address-cells = <2>;
 301                         #size-cells = <1>;
 302                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 303                         gpmc,num-cs = <8>;
 304                         gpmc,num-waitpins = <4>;
 305                         ti,hwmods = "gpmc";
 306                         ti,no-idle-on-init;
 307                         clocks = <&l3_div_ck>;
 308                         clock-names = "fck";
 309                 };
 310
 311                 uart1: serial@4806a000 {
 312                         compatible = "ti,omap4-uart";
 313                         reg = <0x4806a000 0x100>;
 314                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 315                         ti,hwmods = "uart1";
 316                         clock-frequency = <48000000>;
 317                 };
 318
 319                 uart2: serial@4806c000 {
 320                         compatible = "ti,omap4-uart";
 321                         reg = <0x4806c000 0x100>;
 322                         interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 323                         ti,hwmods = "uart2";
 324                         clock-frequency = <48000000>;
 325                 };
 326
 327                 uart3: serial@48020000 {
 328                         compatible = "ti,omap4-uart";
 329                         reg = <0x48020000 0x100>;
 330                         interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 331                         ti,hwmods = "uart3";
 332                         clock-frequency = <48000000>;
 333                 };
 334
 335                 uart4: serial@4806e000 {
 336                         compatible = "ti,omap4-uart";
 337                         reg = <0x4806e000 0x100>;
 338                         interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 339                         ti,hwmods = "uart4";
 340                         clock-frequency = <48000000>;
 341                 };
 342
 343                 hwspinlock: spinlock@4a0f6000 {
 344                         compatible = "ti,omap4-hwspinlock";
 345                         reg = <0x4a0f6000 0x1000>;
 346                         ti,hwmods = "spinlock";
 347                         #hwlock-cells = <1>;
 348                 };
 349
 350                 i2c1: i2c@48070000 {
 351                         compatible = "ti,omap4-i2c";
 352                         reg = <0x48070000 0x100>;
 353                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         ti,hwmods = "i2c1";
 357                 };
 358
 359                 i2c2: i2c@48072000 {
 360                         compatible = "ti,omap4-i2c";
 361                         reg = <0x48072000 0x100>;
 362                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         ti,hwmods = "i2c2";
 366                 };
 367
 368                 i2c3: i2c@48060000 {
 369                         compatible = "ti,omap4-i2c";
 370                         reg = <0x48060000 0x100>;
 371                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         ti,hwmods = "i2c3";
 375                 };
 376
 377                 i2c4: i2c@48350000 {
 378                         compatible = "ti,omap4-i2c";
 379                         reg = <0x48350000 0x100>;
 380                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         ti,hwmods = "i2c4";
 384                 };
 385
 386                 mcspi1: spi@48098000 {
 387                         compatible = "ti,omap4-mcspi";
 388                         reg = <0x48098000 0x200>;
 389                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         ti,hwmods = "mcspi1";
 393                         ti,spi-num-cs = <4>;
 394                         dmas = <&sdma 35>,
 395                                <&sdma 36>,
 396                                <&sdma 37>,
 397                                <&sdma 38>,
 398                                <&sdma 39>,
 399                                <&sdma 40>,
 400                                <&sdma 41>,
 401                                <&sdma 42>;
 402                         dma-names = "tx0", "rx0", "tx1", "rx1",
 403                                     "tx2", "rx2", "tx3", "rx3";
 404                 };
 405
 406                 mcspi2: spi@4809a000 {
 407                         compatible = "ti,omap4-mcspi";
 408                         reg = <0x4809a000 0x200>;
 409                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         ti,hwmods = "mcspi2";
 413                         ti,spi-num-cs = <2>;
 414                         dmas = <&sdma 43>,
 415                                <&sdma 44>,
 416                                <&sdma 45>,
 417                                <&sdma 46>;
 418                         dma-names = "tx0", "rx0", "tx1", "rx1";
 419                 };
 420
 421                 mcspi3: spi@480b8000 {
 422                         compatible = "ti,omap4-mcspi";
 423                         reg = <0x480b8000 0x200>;
 424                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         ti,hwmods = "mcspi3";
 428                         ti,spi-num-cs = <2>;
 429                         dmas = <&sdma 15>, <&sdma 16>;
 430                         dma-names = "tx0", "rx0";
 431                 };
 432
 433                 mcspi4: spi@480ba000 {
 434                         compatible = "ti,omap4-mcspi";
 435                         reg = <0x480ba000 0x200>;
 436                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         ti,hwmods = "mcspi4";
 440                         ti,spi-num-cs = <1>;
 441                         dmas = <&sdma 70>, <&sdma 71>;
 442                         dma-names = "tx0", "rx0";
 443                 };
 444
 445                 mmc1: mmc@4809c000 {
 446                         compatible = "ti,omap4-hsmmc";
 447                         reg = <0x4809c000 0x400>;
 448                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 449                         ti,hwmods = "mmc1";
 450                         ti,dual-volt;
 451                         ti,needs-special-reset;
 452                         dmas = <&sdma 61>, <&sdma 62>;
 453                         dma-names = "tx", "rx";
 454                         pbias-supply = <&pbias_mmc_reg>;
 455                 };
 456
 457                 mmc2: mmc@480b4000 {
 458                         compatible = "ti,omap4-hsmmc";
 459                         reg = <0x480b4000 0x400>;
 460                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 461                         ti,hwmods = "mmc2";
 462                         ti,needs-special-reset;
 463                         dmas = <&sdma 47>, <&sdma 48>;
 464                         dma-names = "tx", "rx";
 465                 };
 466
 467                 mmc3: mmc@480ad000 {
 468                         compatible = "ti,omap4-hsmmc";
 469                         reg = <0x480ad000 0x400>;
 470                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 471                         ti,hwmods = "mmc3";
 472                         ti,needs-special-reset;
 473                         dmas = <&sdma 77>, <&sdma 78>;
 474                         dma-names = "tx", "rx";
 475                 };
 476
 477                 mmc4: mmc@480d1000 {
 478                         compatible = "ti,omap4-hsmmc";
 479                         reg = <0x480d1000 0x400>;
 480                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 481                         ti,hwmods = "mmc4";
 482                         ti,needs-special-reset;
 483                         dmas = <&sdma 57>, <&sdma 58>;
 484                         dma-names = "tx", "rx";
 485                 };
 486
 487                 mmc5: mmc@480d5000 {
 488                         compatible = "ti,omap4-hsmmc";
 489                         reg = <0x480d5000 0x400>;
 490                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 491                         ti,hwmods = "mmc5";
 492                         ti,needs-special-reset;
 493                         dmas = <&sdma 59>, <&sdma 60>;
 494                         dma-names = "tx", "rx";
 495                 };
 496
 497                 mmu_dsp: mmu@4a066000 {
 498                         compatible = "ti,omap4-iommu";
 499                         reg = <0x4a066000 0x100>;
 500                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 501                         ti,hwmods = "mmu_dsp";
 502                 };
 503
 504                 mmu_ipu: mmu@55082000 {
 505                         compatible = "ti,omap4-iommu";
 506                         reg = <0x55082000 0x100>;
 507                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 508                         ti,hwmods = "mmu_ipu";
 509                         ti,iommu-bus-err-back;
 510                 };
 511
 512                 wdt2: wdt@4a314000 {
 513                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 514                         reg = <0x4a314000 0x80>;
 515                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 516                         ti,hwmods = "wd_timer2";
 517                 };
 518
 519                 mcpdm: mcpdm@40132000 {
 520                         compatible = "ti,omap4-mcpdm";
 521                         reg = <0x40132000 0x7f>, /* MPU private access */
 522                               <0x49032000 0x7f>; /* L3 Interconnect */
 523                         reg-names = "mpu", "dma";
 524                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 525                         ti,hwmods = "mcpdm";
 526                         dmas = <&sdma 65>,
 527                                <&sdma 66>;
 528                         dma-names = "up_link", "dn_link";
 529                         status = "disabled";
 530                 };
 531
 532                 dmic: dmic@4012e000 {
 533                         compatible = "ti,omap4-dmic";
 534                         reg = <0x4012e000 0x7f>, /* MPU private access */
 535                               <0x4902e000 0x7f>; /* L3 Interconnect */
 536                         reg-names = "mpu", "dma";
 537                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 538                         ti,hwmods = "dmic";
 539                         dmas = <&sdma 67>;
 540                         dma-names = "up_link";
 541                         status = "disabled";
 542                 };
 543
 544                 mcbsp1: mcbsp@40122000 {
 545                         compatible = "ti,omap4-mcbsp";
 546                         reg = <0x40122000 0xff>, /* MPU private access */
 547                               <0x49022000 0xff>; /* L3 Interconnect */
 548                         reg-names = "mpu", "dma";
 549                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 550                         interrupt-names = "common";
 551                         ti,buffer-size = <128>;
 552                         ti,hwmods = "mcbsp1";
 553                         dmas = <&sdma 33>,
 554                                <&sdma 34>;
 555                         dma-names = "tx", "rx";
 556                         status = "disabled";
 557                 };
 558
 559                 mcbsp2: mcbsp@40124000 {
 560                         compatible = "ti,omap4-mcbsp";
 561                         reg = <0x40124000 0xff>, /* MPU private access */
 562                               <0x49024000 0xff>; /* L3 Interconnect */
 563                         reg-names = "mpu", "dma";
 564                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 565                         interrupt-names = "common";
 566                         ti,buffer-size = <128>;
 567                         ti,hwmods = "mcbsp2";
 568                         dmas = <&sdma 17>,
 569                                <&sdma 18>;
 570                         dma-names = "tx", "rx";
 571                         status = "disabled";
 572                 };
 573
 574                 mcbsp3: mcbsp@40126000 {
 575                         compatible = "ti,omap4-mcbsp";
 576                         reg = <0x40126000 0xff>, /* MPU private access */
 577                               <0x49026000 0xff>; /* L3 Interconnect */
 578                         reg-names = "mpu", "dma";
 579                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 580                         interrupt-names = "common";
 581                         ti,buffer-size = <128>;
 582                         ti,hwmods = "mcbsp3";
 583                         dmas = <&sdma 19>,
 584                                <&sdma 20>;
 585                         dma-names = "tx", "rx";
 586                         status = "disabled";
 587                 };
 588
 589                 mcbsp4: mcbsp@48096000 {
 590                         compatible = "ti,omap4-mcbsp";
 591                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 592                         reg-names = "mpu";
 593                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 594                         interrupt-names = "common";
 595                         ti,buffer-size = <128>;
 596                         ti,hwmods = "mcbsp4";
 597                         dmas = <&sdma 31>,
 598                                <&sdma 32>;
 599                         dma-names = "tx", "rx";
 600                         status = "disabled";
 601                 };
 602
 603                 keypad: keypad@4a31c000 {
 604                         compatible = "ti,omap4-keypad";
 605                         reg = <0x4a31c000 0x80>;
 606                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 607                         reg-names = "mpu";
 608                         ti,hwmods = "kbd";
 609                 };
 610
 611                 dmm@4e000000 {
 612                         compatible = "ti,omap4-dmm";
 613                         reg = <0x4e000000 0x800>;
 614                         interrupts = <0 113 0x4>;
 615                         ti,hwmods = "dmm";
 616                 };
 617
 618                 emif1: emif@4c000000 {
 619                         compatible = "ti,emif-4d";
 620                         reg = <0x4c000000 0x100>;
 621                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 622                         ti,hwmods = "emif1";
 623                         ti,no-idle-on-init;
 624                         phy-type = <1>;
 625                         hw-caps-read-idle-ctrl;
 626                         hw-caps-ll-interface;
 627                         hw-caps-temp-alert;
 628                 };
 629
 630                 emif2: emif@4d000000 {
 631                         compatible = "ti,emif-4d";
 632                         reg = <0x4d000000 0x100>;
 633                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 634                         ti,hwmods = "emif2";
 635                         ti,no-idle-on-init;
 636                         phy-type = <1>;
 637                         hw-caps-read-idle-ctrl;
 638                         hw-caps-ll-interface;
 639                         hw-caps-temp-alert;
 640                 };
 641
 642                 ocp2scp@4a0ad000 {
 643                         compatible = "ti,omap-ocp2scp";
 644                         reg = <0x4a0ad000 0x1f>;
 645                         #address-cells = <1>;
 646                         #size-cells = <1>;
 647                         ranges;
 648                         ti,hwmods = "ocp2scp_usb_phy";
 649                         usb2_phy: usb2phy@4a0ad080 {
 650                                 compatible = "ti,omap-usb2";
 651                                 reg = <0x4a0ad080 0x58>;
 652                                 ctrl-module = <&omap_control_usb2phy>;
 653                                 clocks = <&usb_phy_cm_clk32k>;
 654                                 clock-names = "wkupclk";
 655                                 #phy-cells = <0>;
 656                         };
 657                 };
 658
 659                 mailbox: mailbox@4a0f4000 {
 660                         compatible = "ti,omap4-mailbox";
 661                         reg = <0x4a0f4000 0x200>;
 662                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 663                         ti,hwmods = "mailbox";
 664                         ti,mbox-num-users = <3>;
 665                         ti,mbox-num-fifos = <8>;
 666                         mbox_ipu: mbox_ipu {
 667                                 ti,mbox-tx = <0 0 0>;
 668                                 ti,mbox-rx = <1 0 0>;
 669                         };
 670                         mbox_dsp: mbox_dsp {
 671                                 ti,mbox-tx = <3 0 0>;
 672                                 ti,mbox-rx = <2 0 0>;
 673                         };
 674                 };
 675
 676                 timer1: timer@4a318000 {
 677                         compatible = "ti,omap3430-timer";
 678                         reg = <0x4a318000 0x80>;
 679                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "timer1";
 681                         ti,timer-alwon;
 682                 };
 683
 684                 timer2: timer@48032000 {
 685                         compatible = "ti,omap3430-timer";
 686                         reg = <0x48032000 0x80>;
 687                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 688                         ti,hwmods = "timer2";
 689                 };
 690
 691                 timer3: timer@48034000 {
 692                         compatible = "ti,omap4430-timer";
 693                         reg = <0x48034000 0x80>;
 694                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "timer3";
 696                 };
 697
 698                 timer4: timer@48036000 {
 699                         compatible = "ti,omap4430-timer";
 700                         reg = <0x48036000 0x80>;
 701                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 702                         ti,hwmods = "timer4";
 703                 };
 704
 705                 timer5: timer@40138000 {
 706                         compatible = "ti,omap4430-timer";
 707                         reg = <0x40138000 0x80>,
 708                               <0x49038000 0x80>;
 709                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "timer5";
 711                         ti,timer-dsp;
 712                 };
 713
 714                 timer6: timer@4013a000 {
 715                         compatible = "ti,omap4430-timer";
 716                         reg = <0x4013a000 0x80>,
 717                               <0x4903a000 0x80>;
 718                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 719                         ti,hwmods = "timer6";
 720                         ti,timer-dsp;
 721                 };
 722
 723                 timer7: timer@4013c000 {
 724                         compatible = "ti,omap4430-timer";
 725                         reg = <0x4013c000 0x80>,
 726                               <0x4903c000 0x80>;
 727                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "timer7";
 729                         ti,timer-dsp;
 730                 };
 731
 732                 timer8: timer@4013e000 {
 733                         compatible = "ti,omap4430-timer";
 734                         reg = <0x4013e000 0x80>,
 735                               <0x4903e000 0x80>;
 736                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 737                         ti,hwmods = "timer8";
 738                         ti,timer-pwm;
 739                         ti,timer-dsp;
 740                 };
 741
 742                 timer9: timer@4803e000 {
 743                         compatible = "ti,omap4430-timer";
 744                         reg = <0x4803e000 0x80>;
 745                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "timer9";
 747                         ti,timer-pwm;
 748                 };
 749
 750                 timer10: timer@48086000 {
 751                         compatible = "ti,omap3430-timer";
 752                         reg = <0x48086000 0x80>;
 753                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 754                         ti,hwmods = "timer10";
 755                         ti,timer-pwm;
 756                 };
 757
 758                 timer11: timer@48088000 {
 759                         compatible = "ti,omap4430-timer";
 760                         reg = <0x48088000 0x80>;
 761                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "timer11";
 763                         ti,timer-pwm;
 764                 };
 765
 766                 usbhstll: usbhstll@4a062000 {
 767                         compatible = "ti,usbhs-tll";
 768                         reg = <0x4a062000 0x1000>;
 769                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 770                         ti,hwmods = "usb_tll_hs";
 771                 };
 772
 773                 usbhshost: usbhshost@4a064000 {
 774                         compatible = "ti,usbhs-host";
 775                         reg = <0x4a064000 0x800>;
 776                         ti,hwmods = "usb_host_hs";
 777                         #address-cells = <1>;
 778                         #size-cells = <1>;
 779                         ranges;
 780                         clocks = <&init_60m_fclk>,
 781                                  <&xclk60mhsp1_ck>,
 782                                  <&xclk60mhsp2_ck>;
 783                         clock-names = "refclk_60m_int",
 784                                       "refclk_60m_ext_p1",
 785                                       "refclk_60m_ext_p2";
 786
 787                         usbhsohci: ohci@4a064800 {
 788                                 compatible = "ti,ohci-omap3";
 789                                 reg = <0x4a064800 0x400>;
 790                                 interrupt-parent = <&gic>;
 791                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 792                         };
 793
 794                         usbhsehci: ehci@4a064c00 {
 795                                 compatible = "ti,ehci-omap";
 796                                 reg = <0x4a064c00 0x400>;
 797                                 interrupt-parent = <&gic>;
 798                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 799                         };
 800                 };
 801
 802                 omap_control_usb2phy: control-phy@4a002300 {
 803                         compatible = "ti,control-phy-usb2";
 804                         reg = <0x4a002300 0x4>;
 805                         reg-names = "power";
 806                 };
 807
 808                 omap_control_usbotg: control-phy@4a00233c {
 809                         compatible = "ti,control-phy-otghs";
 810                         reg = <0x4a00233c 0x4>;
 811                         reg-names = "otghs_control";
 812                 };
 813
 814                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 815                         compatible = "ti,omap4-musb";
 816                         reg = <0x4a0ab000 0x7ff>;
 817                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 818                         interrupt-names = "mc", "dma";
 819                         ti,hwmods = "usb_otg_hs";
 820                         usb-phy = <&usb2_phy>;
 821                         phys = <&usb2_phy>;
 822                         phy-names = "usb2-phy";
 823                         multipoint = <1>;
 824                         num-eps = <16>;
 825                         ram-bits = <12>;
 826                         ctrl-module = <&omap_control_usbotg>;
 827                 };
 828
 829                 aes: aes@4b501000 {
 830                         compatible = "ti,omap4-aes";
 831                         ti,hwmods = "aes";
 832                         reg = <0x4b501000 0xa0>;
 833                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 834                         dmas = <&sdma 111>, <&sdma 110>;
 835                         dma-names = "tx", "rx";
 836                 };
 837
 838                 des: des@480a5000 {
 839                         compatible = "ti,omap4-des";
 840                         ti,hwmods = "des";
 841                         reg = <0x480a5000 0xa0>;
 842                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 843                         dmas = <&sdma 117>, <&sdma 116>;
 844                         dma-names = "tx", "rx";
 845                 };
 846
 847                 abb_mpu: regulator-abb-mpu {
 848                         compatible = "ti,abb-v2";
 849                         regulator-name = "abb_mpu";
 850                         #address-cells = <0>;
 851                         #size-cells = <0>;
 852                         ti,tranxdone-status-mask = <0x80>;
 853                         clocks = <&sys_clkin_ck>;
 854                         ti,settling-time = <50>;
 855                         ti,clock-cycles = <16>;
 856
 857                         status = "disabled";
 858                 };
 859
 860                 abb_iva: regulator-abb-iva {
 861                         compatible = "ti,abb-v2";
 862                         regulator-name = "abb_iva";
 863                         #address-cells = <0>;
 864                         #size-cells = <0>;
 865                         ti,tranxdone-status-mask = <0x80000000>;
 866                         clocks = <&sys_clkin_ck>;
 867                         ti,settling-time = <50>;
 868                         ti,clock-cycles = <16>;
 869
 870                         status = "disabled";
 871                 };
 872
 873                 dss: dss@58000000 {
 874                         compatible = "ti,omap4-dss";
 875                         reg = <0x58000000 0x80>;
 876                         status = "disabled";
 877                         ti,hwmods = "dss_core";
 878                         clocks = <&dss_dss_clk>;
 879                         clock-names = "fck";
 880                         #address-cells = <1>;
 881                         #size-cells = <1>;
 882                         ranges;
 883
 884                         dispc@58001000 {
 885                                 compatible = "ti,omap4-dispc";
 886                                 reg = <0x58001000 0x1000>;
 887                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 888                                 ti,hwmods = "dss_dispc";
 889                                 clocks = <&dss_dss_clk>;
 890                                 clock-names = "fck";
 891                         };
 892
 893                         rfbi: encoder@58002000  {
 894                                 compatible = "ti,omap4-rfbi";
 895                                 reg = <0x58002000 0x1000>;
 896                                 status = "disabled";
 897                                 ti,hwmods = "dss_rfbi";
 898                                 clocks = <&dss_dss_clk>, <&dss_fck>;
 899                                 clock-names = "fck", "ick";
 900                         };
 901
 902                         venc: encoder@58003000 {
 903                                 compatible = "ti,omap4-venc";
 904                                 reg = <0x58003000 0x1000>;
 905                                 status = "disabled";
 906                                 ti,hwmods = "dss_venc";
 907                                 clocks = <&dss_tv_clk>;
 908                                 clock-names = "fck";
 909                         };
 910
 911                         dsi1: encoder@58004000 {
 912                                 compatible = "ti,omap4-dsi";
 913                                 reg = <0x58004000 0x200>,
 914                                       <0x58004200 0x40>,
 915                                       <0x58004300 0x20>;
 916                                 reg-names = "proto", "phy", "pll";
 917                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 918                                 status = "disabled";
 919                                 ti,hwmods = "dss_dsi1";
 920                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 921                                 clock-names = "fck", "sys_clk";
 922                         };
 923
 924                         dsi2: encoder@58005000 {
 925                                 compatible = "ti,omap4-dsi";
 926                                 reg = <0x58005000 0x200>,
 927                                       <0x58005200 0x40>,
 928                                       <0x58005300 0x20>;
 929                                 reg-names = "proto", "phy", "pll";
 930                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 931                                 status = "disabled";
 932                                 ti,hwmods = "dss_dsi2";
 933                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 934                                 clock-names = "fck", "sys_clk";
 935                         };
 936
 937                         hdmi: encoder@58006000 {
 938                                 compatible = "ti,omap4-hdmi";
 939                                 reg = <0x58006000 0x200>,
 940                                       <0x58006200 0x100>,
 941                                       <0x58006300 0x100>,
 942                                       <0x58006400 0x1000>;
 943                                 reg-names = "wp", "pll", "phy", "core";
 944                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 945                                 status = "disabled";
 946                                 ti,hwmods = "dss_hdmi";
 947                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 948                                 clock-names = "fck", "sys_clk";
 949                                 dmas = <&sdma 76>;
 950                                 dma-names = "audio_tx";
 951                         };
 952                 };
 953         };
 954 };
 955
 956 /include/ "omap44xx-clocks.dtsi"