arch/arm/boot/dts/r8a7740.dtsi

   1 /*
   2  * Device Tree Source for the r8a7740 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 #include <dt-bindings/clock/r8a7740-clock.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7740";
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a9";
  25                         device_type = "cpu";
  26                         reg = <0x0>;
  27                         clock-frequency = <800000000>;
  28                 };
  29         };
  30
  31         gic: interrupt-controller@c2800000 {
  32                 compatible = "arm,cortex-a9-gic";
  33                 #interrupt-cells = <3>;
  34                 interrupt-controller;
  35                 reg = <0xc2800000 0x1000>,
  36                       <0xc2000000 0x1000>;
  37         };
  38
  39         pmu {
  40                 compatible = "arm,cortex-a9-pmu";
  41                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
  42         };
  43
  44         /* irqpin0: IRQ0 - IRQ7 */
  45         irqpin0: irqpin@e6900000 {
  46                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  47                 #interrupt-cells = <2>;
  48                 interrupt-controller;
  49                 reg = <0xe6900000 4>,
  50                         <0xe6900010 4>,
  51                         <0xe6900020 1>,
  52                         <0xe6900040 1>,
  53                         <0xe6900060 1>;
  54                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  55                               0 149 IRQ_TYPE_LEVEL_HIGH
  56                               0 149 IRQ_TYPE_LEVEL_HIGH
  57                               0 149 IRQ_TYPE_LEVEL_HIGH
  58                               0 149 IRQ_TYPE_LEVEL_HIGH
  59                               0 149 IRQ_TYPE_LEVEL_HIGH
  60                               0 149 IRQ_TYPE_LEVEL_HIGH
  61                               0 149 IRQ_TYPE_LEVEL_HIGH>;
  62         };
  63
  64         /* irqpin1: IRQ8 - IRQ15 */
  65         irqpin1: irqpin@e6900004 {
  66                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  67                 #interrupt-cells = <2>;
  68                 interrupt-controller;
  69                 reg = <0xe6900004 4>,
  70                         <0xe6900014 4>,
  71                         <0xe6900024 1>,
  72                         <0xe6900044 1>,
  73                         <0xe6900064 1>;
  74                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  75                               0 149 IRQ_TYPE_LEVEL_HIGH
  76                               0 149 IRQ_TYPE_LEVEL_HIGH
  77                               0 149 IRQ_TYPE_LEVEL_HIGH
  78                               0 149 IRQ_TYPE_LEVEL_HIGH
  79                               0 149 IRQ_TYPE_LEVEL_HIGH
  80                               0 149 IRQ_TYPE_LEVEL_HIGH
  81                               0 149 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83
  84         /* irqpin2: IRQ16 - IRQ23 */
  85         irqpin2: irqpin@e6900008 {
  86                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 reg = <0xe6900008 4>,
  90                         <0xe6900018 4>,
  91                         <0xe6900028 1>,
  92                         <0xe6900048 1>,
  93                         <0xe6900068 1>;
  94                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  95                               0 149 IRQ_TYPE_LEVEL_HIGH
  96                               0 149 IRQ_TYPE_LEVEL_HIGH
  97                               0 149 IRQ_TYPE_LEVEL_HIGH
  98                               0 149 IRQ_TYPE_LEVEL_HIGH
  99                               0 149 IRQ_TYPE_LEVEL_HIGH
 100                               0 149 IRQ_TYPE_LEVEL_HIGH
 101                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 102         };
 103
 104         /* irqpin3: IRQ24 - IRQ31 */
 105         irqpin3: irqpin@e690000c {
 106                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109                 reg = <0xe690000c 4>,
 110                         <0xe690001c 4>,
 111                         <0xe690002c 1>,
 112                         <0xe690004c 1>,
 113                         <0xe690006c 1>;
 114                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
 115                               0 149 IRQ_TYPE_LEVEL_HIGH
 116                               0 149 IRQ_TYPE_LEVEL_HIGH
 117                               0 149 IRQ_TYPE_LEVEL_HIGH
 118                               0 149 IRQ_TYPE_LEVEL_HIGH
 119                               0 149 IRQ_TYPE_LEVEL_HIGH
 120                               0 149 IRQ_TYPE_LEVEL_HIGH
 121                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 122         };
 123
 124         ether: ethernet@e9a00000 {
 125                 compatible = "renesas,gether-r8a7740";
 126                 reg = <0xe9a00000 0x800>,
 127                       <0xe9a01800 0x800>;
 128                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 129                 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
 130                 phy-mode = "mii";
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 status = "disabled";
 134         };
 135
 136         i2c0: i2c@fff20000 {
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 140                 reg = <0xfff20000 0x425>;
 141                 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
 142                               0 202 IRQ_TYPE_LEVEL_HIGH
 143                               0 203 IRQ_TYPE_LEVEL_HIGH
 144                               0 204 IRQ_TYPE_LEVEL_HIGH>;
 145                 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
 146                 status = "disabled";
 147         };
 148
 149         i2c1: i2c@e6c20000 {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 153                 reg = <0xe6c20000 0x425>;
 154                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
 155                               0 71 IRQ_TYPE_LEVEL_HIGH
 156                               0 72 IRQ_TYPE_LEVEL_HIGH
 157                               0 73 IRQ_TYPE_LEVEL_HIGH>;
 158                 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
 159                 status = "disabled";
 160         };
 161
 162         scifa0: serial@e6c40000 {
 163                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 164                 reg = <0xe6c40000 0x100>;
 165                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
 167                 clock-names = "sci_ick";
 168                 status = "disabled";
 169         };
 170
 171         scifa1: serial@e6c50000 {
 172                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 173                 reg = <0xe6c50000 0x100>;
 174                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
 176                 clock-names = "sci_ick";
 177                 status = "disabled";
 178         };
 179
 180         scifa2: serial@e6c60000 {
 181                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 182                 reg = <0xe6c60000 0x100>;
 183                 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
 185                 clock-names = "sci_ick";
 186                 status = "disabled";
 187         };
 188
 189         scifa3: serial@e6c70000 {
 190                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 191                 reg = <0xe6c70000 0x100>;
 192                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
 194                 clock-names = "sci_ick";
 195                 status = "disabled";
 196         };
 197
 198         scifa4: serial@e6c80000 {
 199                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 200                 reg = <0xe6c80000 0x100>;
 201                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
 203                 clock-names = "sci_ick";
 204                 status = "disabled";
 205         };
 206
 207         scifa5: serial@e6cb0000 {
 208                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 209                 reg = <0xe6cb0000 0x100>;
 210                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
 212                 clock-names = "sci_ick";
 213                 status = "disabled";
 214         };
 215
 216         scifa6: serial@e6cc0000 {
 217                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 218                 reg = <0xe6cc0000 0x100>;
 219                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
 221                 clock-names = "sci_ick";
 222                 status = "disabled";
 223         };
 224
 225         scifa7: serial@e6cd0000 {
 226                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 227                 reg = <0xe6cd0000 0x100>;
 228                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
 230                 clock-names = "sci_ick";
 231                 status = "disabled";
 232         };
 233
 234         scifb8: serial@e6c30000 {
 235                 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
 236                 reg = <0xe6c30000 0x100>;
 237                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
 239                 clock-names = "sci_ick";
 240                 status = "disabled";
 241         };
 242
 243         pfc: pfc@e6050000 {
 244                 compatible = "renesas,pfc-r8a7740";
 245                 reg = <0xe6050000 0x8000>,
 246                       <0xe605800c 0x20>;
 247                 gpio-controller;
 248                 #gpio-cells = <2>;
 249                 interrupts-extended =
 250                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 251                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 252                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 253                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 254                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 255                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 256                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 257                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 258         };
 259
 260         tpu: pwm@e6600000 {
 261                 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
 262                 reg = <0xe6600000 0x100>;
 263                 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
 264                 status = "disabled";
 265                 #pwm-cells = <3>;
 266         };
 267
 268         mmcif0: mmc@e6bd0000 {
 269                 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
 270                 reg = <0xe6bd0000 0x100>;
 271                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
 272                               0 57 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
 274                 status = "disabled";
 275         };
 276
 277         sdhi0: sd@e6850000 {
 278                 compatible = "renesas,sdhi-r8a7740";
 279                 reg = <0xe6850000 0x100>;
 280                 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
 281                               0 118 IRQ_TYPE_LEVEL_HIGH
 282                               0 119 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
 284                 cap-sd-highspeed;
 285                 cap-sdio-irq;
 286                 status = "disabled";
 287         };
 288
 289         sdhi1: sd@e6860000 {
 290                 compatible = "renesas,sdhi-r8a7740";
 291                 reg = <0xe6860000 0x100>;
 292                 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
 293                               0 122 IRQ_TYPE_LEVEL_HIGH
 294                               0 123 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
 296                 cap-sd-highspeed;
 297                 cap-sdio-irq;
 298                 status = "disabled";
 299         };
 300
 301         sdhi2: sd@e6870000 {
 302                 compatible = "renesas,sdhi-r8a7740";
 303                 reg = <0xe6870000 0x100>;
 304                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
 305                               0 126 IRQ_TYPE_LEVEL_HIGH
 306                               0 127 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
 308                 cap-sd-highspeed;
 309                 cap-sdio-irq;
 310                 status = "disabled";
 311         };
 312
 313         sh_fsi2: sound@fe1f0000 {
 314                 #sound-dai-cells = <1>;
 315                 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
 316                 reg = <0xfe1f0000 0x400>;
 317                 interrupts = <0 9 0x4>;
 318                 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
 319                 status = "disabled";
 320         };
 321
 322         clocks {
 323                 #address-cells = <1>;
 324                 #size-cells = <1>;
 325                 ranges;
 326
 327                 /* External root clock */
 328                 extalr_clk: extalr_clk {
 329                         compatible = "fixed-clock";
 330                         #clock-cells = <0>;
 331                         clock-frequency = <32768>;
 332                         clock-output-names = "extalr";
 333                 };
 334                 extal1_clk: extal1_clk {
 335                         compatible = "fixed-clock";
 336                         #clock-cells = <0>;
 337                         clock-frequency = <0>;
 338                         clock-output-names = "extal1";
 339                 };
 340                 extal2_clk: extal2_clk {
 341                         compatible = "fixed-clock";
 342                         #clock-cells = <0>;
 343                         clock-frequency = <0>;
 344                         clock-output-names = "extal2";
 345                 };
 346                 dv_clk: dv_clk {
 347                         compatible = "fixed-clock";
 348                         #clock-cells = <0>;
 349                         clock-frequency = <27000000>;
 350                         clock-output-names = "dv";
 351                 };
 352                 fsiack_clk: fsiack_clk {
 353                         compatible = "fixed-clock";
 354                         #clock-cells = <0>;
 355                         clock-frequency = <0>;
 356                         clock-output-names = "fsiack";
 357                 };
 358                 fsibck_clk: fsibck_clk {
 359                         compatible = "fixed-clock";
 360                         #clock-cells = <0>;
 361                         clock-frequency = <0>;
 362                         clock-output-names = "fsibck";
 363                 };
 364
 365                 /* Special CPG clocks */
 366                 cpg_clocks: cpg_clocks@e6150000 {
 367                         compatible = "renesas,r8a7740-cpg-clocks";
 368                         reg = <0xe6150000 0x10000>;
 369                         clocks = <&extal1_clk>, <&extalr_clk>;
 370                         #clock-cells = <1>;
 371                         clock-output-names = "system", "pllc0", "pllc1",
 372                                              "pllc2", "r",
 373                                              "usb24s",
 374                                              "i", "zg", "b", "m1", "hp",
 375                                              "hpp", "usbp", "s", "zb", "m3",
 376                                              "cp";
 377                 };
 378
 379                 /* Variable factor clocks (DIV6) */
 380                 sub_clk: sub_clk@e6150080 {
 381                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 382                         reg = <0xe6150080 4>;
 383                         clocks = <&pllc1_div2_clk>;
 384                         #clock-cells = <0>;
 385                         clock-output-names = "sub";
 386                 };
 387
 388                 /* Fixed factor clocks */
 389                 pllc1_div2_clk: pllc1_div2_clk {
 390                         compatible = "fixed-factor-clock";
 391                         clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
 392                         #clock-cells = <0>;
 393                         clock-div = <2>;
 394                         clock-mult = <1>;
 395                         clock-output-names = "pllc1_div2";
 396                 };
 397                 extal1_div2_clk: extal1_div2_clk {
 398                         compatible = "fixed-factor-clock";
 399                         clocks = <&extal1_clk>;
 400                         #clock-cells = <0>;
 401                         clock-div = <2>;
 402                         clock-mult = <1>;
 403                         clock-output-names = "extal1_div2";
 404                 };
 405
 406                 /* Gate clocks */
 407                 subck_clks: subck_clks@e6150080 {
 408                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 409                         reg = <0xe6150080 4>;
 410                         clocks = <&sub_clk>, <&sub_clk>;
 411                         #clock-cells = <1>;
 412                         renesas,clock-indices = <
 413                                 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
 414                         >;
 415                         clock-output-names =
 416                                 "subck", "subck2";
 417                 };
 418                 mstp1_clks: mstp1_clks@e6150134 {
 419                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 420                         reg = <0xe6150134 4>, <0xe6150038 4>;
 421                         clocks = <&cpg_clocks R8A7740_CLK_S>,
 422                                  <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 423                                  <&cpg_clocks R8A7740_CLK_B>,
 424                                  <&sub_clk>, <&sub_clk>,
 425                                  <&cpg_clocks R8A7740_CLK_B>;
 426                         #clock-cells = <1>;
 427                         renesas,clock-indices = <
 428                                 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
 429                                 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
 430                                 R8A7740_CLK_LCDC0
 431                         >;
 432                         clock-output-names =
 433                                 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
 434                                 "tmu1", "lcdc0";
 435                 };
 436                 mstp2_clks: mstp2_clks@e6150138 {
 437                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 438                         reg = <0xe6150138 4>, <0xe6150040 4>;
 439                         clocks = <&sub_clk>, <&sub_clk>,
 440                                  <&cpg_clocks R8A7740_CLK_HP>,
 441                                  <&cpg_clocks R8A7740_CLK_HP>,
 442                                  <&cpg_clocks R8A7740_CLK_HP>,
 443                                  <&cpg_clocks R8A7740_CLK_HP>,
 444                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 445                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 446                                  <&sub_clk>;
 447                         #clock-cells = <1>;
 448                         renesas,clock-indices = <
 449                                 R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
 450                                 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
 451                                 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
 452                                 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
 453                                 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
 454                                 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
 455                                 R8A7740_CLK_SCIFA4
 456                         >;
 457                         clock-output-names =
 458                                 "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
 459                                 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
 460                                 "scifa2", "scifa3", "scifa4";
 461                 };
 462                 mstp3_clks: mstp3_clks@e615013c {
 463                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 464                         reg = <0xe615013c 4>, <0xe6150048 4>;
 465                         clocks = <&cpg_clocks R8A7740_CLK_R>,
 466                                  <&cpg_clocks R8A7740_CLK_HP>,
 467                                  <&sub_clk>,
 468                                  <&cpg_clocks R8A7740_CLK_HP>,
 469                                  <&cpg_clocks R8A7740_CLK_HP>,
 470                                  <&cpg_clocks R8A7740_CLK_HP>,
 471                                  <&cpg_clocks R8A7740_CLK_HP>,
 472                                  <&cpg_clocks R8A7740_CLK_HP>,
 473                                  <&cpg_clocks R8A7740_CLK_HP>;
 474                         #clock-cells = <1>;
 475                         renesas,clock-indices = <
 476                                 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
 477                                 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
 478                                 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
 479                         >;
 480                         clock-output-names =
 481                                 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
 482                                 "mmc", "gether", "tpu0";
 483                 };
 484                 mstp4_clks: mstp4_clks@e6150140 {
 485                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 486                         reg = <0xe6150140 4>, <0xe615004c 4>;
 487                         clocks = <&cpg_clocks R8A7740_CLK_HP>,
 488                                  <&cpg_clocks R8A7740_CLK_HP>,
 489                                  <&cpg_clocks R8A7740_CLK_HP>,
 490                                  <&cpg_clocks R8A7740_CLK_HP>;
 491                         #clock-cells = <1>;
 492                         renesas,clock-indices = <
 493                                 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
 494                                 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
 495                         >;
 496                         clock-output-names =
 497                                 "usbhost", "sdhi2", "usbfunc", "usphy";
 498                 };
 499         };
 500 };