arch/arm/boot/dts/r8a7791-porter.dts

   1 /*
   2  * Device Tree Source for the Porter board
   3  *
   4  * Copyright (C) 2015 Cogent Embedded, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12 #include "r8a7791.dtsi"
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         model = "Porter";
  17         compatible = "renesas,porter", "renesas,r8a7791";
  18
  19         aliases {
  20                 serial0 = &scif0;
  21         };
  22
  23         chosen {
  24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  25                 stdout-path = &scif0;
  26         };
  27
  28         memory@40000000 {
  29                 device_type = "memory";
  30                 reg = <0 0x40000000 0 0x40000000>;
  31         };
  32
  33         memory@200000000 {
  34                 device_type = "memory";
  35                 reg = <2 0x00000000 0 0x40000000>;
  36         };
  37
  38         vcc_sdhi0: regulator@0 {
  39                 compatible = "regulator-fixed";
  40
  41                 regulator-name = "SDHI0 Vcc";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44                 regulator-always-on;
  45         };
  46
  47         vccq_sdhi0: regulator@1 {
  48                 compatible = "regulator-gpio";
  49
  50                 regulator-name = "SDHI0 VccQ";
  51                 regulator-min-microvolt = <1800000>;
  52                 regulator-max-microvolt = <3300000>;
  53
  54                 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  55                 gpios-states = <1>;
  56                 states = <3300000 1
  57                           1800000 0>;
  58         };
  59
  60         vcc_sdhi2: regulator@2 {
  61                 compatible = "regulator-fixed";
  62
  63                 regulator-name = "SDHI2 Vcc";
  64                 regulator-min-microvolt = <3300000>;
  65                 regulator-max-microvolt = <3300000>;
  66                 regulator-always-on;
  67         };
  68
  69         vccq_sdhi2: regulator@3 {
  70                 compatible = "regulator-gpio";
  71
  72                 regulator-name = "SDHI2 VccQ";
  73                 regulator-min-microvolt = <1800000>;
  74                 regulator-max-microvolt = <3300000>;
  75
  76                 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  77                 gpios-states = <1>;
  78                 states = <3300000 1
  79                           1800000 0>;
  80         };
  81 };
  82
  83 &extal_clk {
  84         clock-frequency = <20000000>;
  85 };
  86
  87 &pfc {
  88         scif0_pins: serial0 {
  89                 renesas,groups = "scif0_data_d";
  90                 renesas,function = "scif0";
  91         };
  92
  93         ether_pins: ether {
  94                 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
  95                 renesas,function = "eth";
  96         };
  97
  98         phy1_pins: phy1 {
  99                 renesas,groups = "intc_irq0";
 100                 renesas,function = "intc";
 101         };
 102
 103         sdhi0_pins: sd0 {
 104                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
 105                 renesas,function = "sdhi0";
 106         };
 107
 108         sdhi2_pins: sd2 {
 109                 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
 110                 renesas,function = "sdhi2";
 111         };
 112
 113         qspi_pins: spi0 {
 114                 renesas,groups = "qspi_ctrl", "qspi_data4";
 115                 renesas,function = "qspi";
 116         };
 117
 118         i2c2_pins: i2c2 {
 119                 renesas,groups = "i2c2";
 120                 renesas,function = "i2c2";
 121         };
 122
 123         usb0_pins: usb0 {
 124                 renesas,groups = "usb0";
 125                 renesas,function = "usb0";
 126         };
 127
 128         usb1_pins: usb1 {
 129                 renesas,groups = "usb1";
 130                 renesas,function = "usb1";
 131         };
 132
 133         vin0_pins: vin0 {
 134                 renesas,groups = "vin0_data8", "vin0_clk";
 135                 renesas,function = "vin0";
 136         };
 137
 138         can0_pins: can0 {
 139                 renesas,groups = "can0_data";
 140                 renesas,function = "can0";
 141         };
 142 };
 143
 144 &scif0 {
 145         pinctrl-0 = <&scif0_pins>;
 146         pinctrl-names = "default";
 147
 148         status = "okay";
 149 };
 150
 151 &ether {
 152         pinctrl-0 = <&ether_pins &phy1_pins>;
 153         pinctrl-names = "default";
 154
 155         phy-handle = <&phy1>;
 156         renesas,ether-link-active-low;
 157         status = "ok";
 158
 159         phy1: ethernet-phy@1 {
 160                 reg = <1>;
 161                 interrupt-parent = <&irqc0>;
 162                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 163                 micrel,led-mode = <1>;
 164         };
 165 };
 166
 167 &sdhi0 {
 168         pinctrl-0 = <&sdhi0_pins>;
 169         pinctrl-names = "default";
 170
 171         vmmc-supply = <&vcc_sdhi0>;
 172         vqmmc-supply = <&vccq_sdhi0>;
 173         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
 174         wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
 175         status = "okay";
 176 };
 177
 178 &sdhi2 {
 179         pinctrl-0 = <&sdhi2_pins>;
 180         pinctrl-names = "default";
 181
 182         vmmc-supply = <&vcc_sdhi2>;
 183         vqmmc-supply = <&vccq_sdhi2>;
 184         cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
 185         status = "okay";
 186 };
 187
 188 &qspi {
 189         pinctrl-0 = <&qspi_pins>;
 190         pinctrl-names = "default";
 191
 192         status = "okay";
 193
 194         flash@0 {
 195                 compatible = "spansion,s25fl512s", "jedec,spi-nor";
 196                 reg = <0>;
 197                 spi-max-frequency = <30000000>;
 198                 spi-tx-bus-width = <4>;
 199                 spi-rx-bus-width = <4>;
 200                 m25p,fast-read;
 201
 202                 partitions {
 203                         #address-cells = <1>;
 204                         #size-cells = <1>;
 205
 206                         partition@0 {
 207                                 label = "loader_prg";
 208                                 reg = <0x00000000 0x00040000>;
 209                                 read-only;
 210                         };
 211                         partition@40000 {
 212                                 label = "user_prg";
 213                                 reg = <0x00040000 0x00400000>;
 214                                 read-only;
 215                         };
 216                         partition@440000 {
 217                                 label = "flash_fs";
 218                                 reg = <0x00440000 0x03bc0000>;
 219                         };
 220                 };
 221         };
 222 };
 223
 224 &i2c2 {
 225         pinctrl-0 = <&i2c2_pins>;
 226         pinctrl-names = "default";
 227
 228         status = "okay";
 229         clock-frequency = <400000>;
 230
 231         composite-in@20 {
 232                 compatible = "adi,adv7180";
 233                 reg = <0x20>;
 234                 remote = <&vin0>;
 235
 236                 port {
 237                         adv7180: endpoint {
 238                                 bus-width = <8>;
 239                                 remote-endpoint = <&vin0ep>;
 240                         };
 241                 };
 242         };
 243 };
 244
 245 &sata0 {
 246         status = "okay";
 247 };
 248
 249 /* composite video input */
 250 &vin0 {
 251         status = "ok";
 252         pinctrl-0 = <&vin0_pins>;
 253         pinctrl-names = "default";
 254
 255         port {
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258
 259                 vin0ep: endpoint {
 260                         remote-endpoint = <&adv7180>;
 261                         bus-width = <8>;
 262                 };
 263         };
 264 };
 265
 266 &pci0 {
 267         pinctrl-0 = <&usb0_pins>;
 268         pinctrl-names = "default";
 269
 270         status = "okay";
 271 };
 272
 273 &pci1 {
 274         pinctrl-0 = <&usb1_pins>;
 275         pinctrl-names = "default";
 276
 277         status = "okay";
 278 };
 279
 280 &hsusb {
 281         pinctrl-0 = <&usb0_pins>;
 282         pinctrl-names = "default";
 283
 284         status = "okay";
 285         renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
 286 };
 287
 288 &usbphy {
 289         status = "okay";
 290 };
 291
 292 &pcie_bus_clk {
 293         status = "okay";
 294 };
 295
 296 &pciec {
 297         status = "okay";
 298 };
 299
 300 &can0 {
 301         pinctrl-0 = <&can0_pins>;
 302         pinctrl-names = "default";
 303
 304         status = "okay";
 305 };