arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/power/r8a7791-sysc.h>
  17
  18 / {
  19         compatible = "renesas,r8a7791";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &i2c4;
  30                 i2c5 = &i2c5;
  31                 i2c6 = &i2c6;
  32                 i2c7 = &i2c7;
  33                 i2c8 = &i2c8;
  34                 spi0 = &qspi;
  35                 spi1 = &msiof0;
  36                 spi2 = &msiof1;
  37                 spi3 = &msiof2;
  38                 vin0 = &vin0;
  39                 vin1 = &vin1;
  40                 vin2 = &vin2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0>;
  51                         clock-frequency = <1500000000>;
  52                         voltage-tolerance = <1>; /* 1% */
  53                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  54                         clock-latency = <300000>; /* 300 us */
  55                         power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
  56                         next-level-cache = <&L2_CA15>;
  57
  58                         /* kHz - uV - OPPs unknown yet */
  59                         operating-points = <1500000 1000000>,
  60                                            <1312500 1000000>,
  61                                            <1125000 1000000>,
  62                                            < 937500 1000000>,
  63                                            < 750000 1000000>,
  64                                            < 375000 1000000>;
  65                 };
  66
  67                 cpu1: cpu@1 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <1>;
  71                         clock-frequency = <1500000000>;
  72                         power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
  73                         next-level-cache = <&L2_CA15>;
  74                 };
  75         };
  76
  77         thermal-zones {
  78                 cpu_thermal: cpu-thermal {
  79                         polling-delay-passive   = <0>;
  80                         polling-delay           = <0>;
  81
  82                         thermal-sensors = <&thermal>;
  83
  84                         trips {
  85                                 cpu-crit {
  86                                         temperature     = <115000>;
  87                                         hysteresis      = <0>;
  88                                         type            = "critical";
  89                                 };
  90                         };
  91                         cooling-maps {
  92                         };
  93                 };
  94         };
  95
  96         L2_CA15: cache-controller@0 {
  97                 compatible = "cache";
  98                 power-domains = <&sysc R8A7791_PD_CA15_SCU>;
  99                 cache-unified;
 100                 cache-level = <2>;
 101         };
 102
 103         gic: interrupt-controller@f1001000 {
 104                 compatible = "arm,gic-400";
 105                 #interrupt-cells = <3>;
 106                 #address-cells = <0>;
 107                 interrupt-controller;
 108                 reg = <0 0xf1001000 0 0x1000>,
 109                         <0 0xf1002000 0 0x1000>,
 110                         <0 0xf1004000 0 0x2000>,
 111                         <0 0xf1006000 0 0x2000>;
 112                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 113         };
 114
 115         gpio0: gpio@e6050000 {
 116                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 117                 reg = <0 0xe6050000 0 0x50>;
 118                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 119                 #gpio-cells = <2>;
 120                 gpio-controller;
 121                 gpio-ranges = <&pfc 0 0 32>;
 122                 #interrupt-cells = <2>;
 123                 interrupt-controller;
 124                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
 125                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 126         };
 127
 128         gpio1: gpio@e6051000 {
 129                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 130                 reg = <0 0xe6051000 0 0x50>;
 131                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 132                 #gpio-cells = <2>;
 133                 gpio-controller;
 134                 gpio-ranges = <&pfc 0 32 26>;
 135                 #interrupt-cells = <2>;
 136                 interrupt-controller;
 137                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 138                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 139         };
 140
 141         gpio2: gpio@e6052000 {
 142                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 143                 reg = <0 0xe6052000 0 0x50>;
 144                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 145                 #gpio-cells = <2>;
 146                 gpio-controller;
 147                 gpio-ranges = <&pfc 0 64 32>;
 148                 #interrupt-cells = <2>;
 149                 interrupt-controller;
 150                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 151                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 152         };
 153
 154         gpio3: gpio@e6053000 {
 155                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 156                 reg = <0 0xe6053000 0 0x50>;
 157                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 158                 #gpio-cells = <2>;
 159                 gpio-controller;
 160                 gpio-ranges = <&pfc 0 96 32>;
 161                 #interrupt-cells = <2>;
 162                 interrupt-controller;
 163                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 164                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 165         };
 166
 167         gpio4: gpio@e6054000 {
 168                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 169                 reg = <0 0xe6054000 0 0x50>;
 170                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 171                 #gpio-cells = <2>;
 172                 gpio-controller;
 173                 gpio-ranges = <&pfc 0 128 32>;
 174                 #interrupt-cells = <2>;
 175                 interrupt-controller;
 176                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 177                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 178         };
 179
 180         gpio5: gpio@e6055000 {
 181                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 182                 reg = <0 0xe6055000 0 0x50>;
 183                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 184                 #gpio-cells = <2>;
 185                 gpio-controller;
 186                 gpio-ranges = <&pfc 0 160 32>;
 187                 #interrupt-cells = <2>;
 188                 interrupt-controller;
 189                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 190                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 191         };
 192
 193         gpio6: gpio@e6055400 {
 194                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 195                 reg = <0 0xe6055400 0 0x50>;
 196                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 197                 #gpio-cells = <2>;
 198                 gpio-controller;
 199                 gpio-ranges = <&pfc 0 192 32>;
 200                 #interrupt-cells = <2>;
 201                 interrupt-controller;
 202                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 203                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 204         };
 205
 206         gpio7: gpio@e6055800 {
 207                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 208                 reg = <0 0xe6055800 0 0x50>;
 209                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 210                 #gpio-cells = <2>;
 211                 gpio-controller;
 212                 gpio-ranges = <&pfc 0 224 26>;
 213                 #interrupt-cells = <2>;
 214                 interrupt-controller;
 215                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 216                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 217         };
 218
 219         thermal: thermal@e61f0000 {
 220                 compatible =    "renesas,thermal-r8a7791",
 221                                 "renesas,rcar-gen2-thermal",
 222                                 "renesas,rcar-thermal";
 223                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 224                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 226                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 227                 #thermal-sensor-cells = <0>;
 228         };
 229
 230         timer {
 231                 compatible = "arm,armv7-timer";
 232                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 233                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 234                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 235                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 236         };
 237
 238         cmt0: timer@ffca0000 {
 239                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 240                 reg = <0 0xffca0000 0 0x1004>;
 241                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 244                 clock-names = "fck";
 245                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 246
 247                 renesas,channels-mask = <0x60>;
 248
 249                 status = "disabled";
 250         };
 251
 252         cmt1: timer@e6130000 {
 253                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 254                 reg = <0 0xe6130000 0 0x1004>;
 255                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 263                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 264                 clock-names = "fck";
 265                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 266
 267                 renesas,channels-mask = <0xff>;
 268
 269                 status = "disabled";
 270         };
 271
 272         irqc0: interrupt-controller@e61c0000 {
 273                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 274                 #interrupt-cells = <2>;
 275                 interrupt-controller;
 276                 reg = <0 0xe61c0000 0 0x200>;
 277                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 287                 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
 288                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 289         };
 290
 291         dmac0: dma-controller@e6700000 {
 292                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 293                 reg = <0 0xe6700000 0 0x20000>;
 294                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 295                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 296                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 297                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 298                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 299                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 300                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 301                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 302                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 303                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 304                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 305                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 306                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 307                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 308                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 310                 interrupt-names = "error",
 311                                 "ch0", "ch1", "ch2", "ch3",
 312                                 "ch4", "ch5", "ch6", "ch7",
 313                                 "ch8", "ch9", "ch10", "ch11",
 314                                 "ch12", "ch13", "ch14";
 315                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 316                 clock-names = "fck";
 317                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 318                 #dma-cells = <1>;
 319                 dma-channels = <15>;
 320         };
 321
 322         dmac1: dma-controller@e6720000 {
 323                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 324                 reg = <0 0xe6720000 0 0x20000>;
 325                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 326                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 327                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 328                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 329                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 330                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 331                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 332                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 333                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 334                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 335                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 341                 interrupt-names = "error",
 342                                 "ch0", "ch1", "ch2", "ch3",
 343                                 "ch4", "ch5", "ch6", "ch7",
 344                                 "ch8", "ch9", "ch10", "ch11",
 345                                 "ch12", "ch13", "ch14";
 346                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 347                 clock-names = "fck";
 348                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 349                 #dma-cells = <1>;
 350                 dma-channels = <15>;
 351         };
 352
 353         audma0: dma-controller@ec700000 {
 354                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 355                 reg = <0 0xec700000 0 0x10000>;
 356                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 357                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 358                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 359                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 360                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 361                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 362                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 363                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 364                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 365                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 366                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 367                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 368                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 369                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 370                 interrupt-names = "error",
 371                                 "ch0", "ch1", "ch2", "ch3",
 372                                 "ch4", "ch5", "ch6", "ch7",
 373                                 "ch8", "ch9", "ch10", "ch11",
 374                                 "ch12";
 375                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 376                 clock-names = "fck";
 377                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 378                 #dma-cells = <1>;
 379                 dma-channels = <13>;
 380         };
 381
 382         audma1: dma-controller@ec720000 {
 383                 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 384                 reg = <0 0xec720000 0 0x10000>;
 385                 interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 386                                  GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 387                                  GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 388                                  GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 389                                  GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 390                                  GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 391                                  GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 392                                  GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 393                                  GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 394                                  GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 395                                  GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 396                                  GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 397                                  GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 398                                  GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 399                 interrupt-names = "error",
 400                                 "ch0", "ch1", "ch2", "ch3",
 401                                 "ch4", "ch5", "ch6", "ch7",
 402                                 "ch8", "ch9", "ch10", "ch11",
 403                                 "ch12";
 404                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 405                 clock-names = "fck";
 406                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 407                 #dma-cells = <1>;
 408                 dma-channels = <13>;
 409         };
 410
 411         usb_dmac0: dma-controller@e65a0000 {
 412                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 413                 reg = <0 0xe65a0000 0 0x100>;
 414                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
 415                               GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 416                 interrupt-names = "ch0", "ch1";
 417                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
 418                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 419                 #dma-cells = <1>;
 420                 dma-channels = <2>;
 421         };
 422
 423         usb_dmac1: dma-controller@e65b0000 {
 424                 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 425                 reg = <0 0xe65b0000 0 0x100>;
 426                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
 427                               GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 428                 interrupt-names = "ch0", "ch1";
 429                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
 430                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 431                 #dma-cells = <1>;
 432                 dma-channels = <2>;
 433         };
 434
 435         /* The memory map in the User's Manual maps the cores to bus numbers */
 436         i2c0: i2c@e6508000 {
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 compatible = "renesas,i2c-r8a7791";
 440                 reg = <0 0xe6508000 0 0x40>;
 441                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 443                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 444                 i2c-scl-internal-delay-ns = <6>;
 445                 status = "disabled";
 446         };
 447
 448         i2c1: i2c@e6518000 {
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 compatible = "renesas,i2c-r8a7791";
 452                 reg = <0 0xe6518000 0 0x40>;
 453                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 455                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 456                 i2c-scl-internal-delay-ns = <6>;
 457                 status = "disabled";
 458         };
 459
 460         i2c2: i2c@e6530000 {
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 compatible = "renesas,i2c-r8a7791";
 464                 reg = <0 0xe6530000 0 0x40>;
 465                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 467                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 468                 i2c-scl-internal-delay-ns = <6>;
 469                 status = "disabled";
 470         };
 471
 472         i2c3: i2c@e6540000 {
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 compatible = "renesas,i2c-r8a7791";
 476                 reg = <0 0xe6540000 0 0x40>;
 477                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 478                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 479                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 480                 i2c-scl-internal-delay-ns = <6>;
 481                 status = "disabled";
 482         };
 483
 484         i2c4: i2c@e6520000 {
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 compatible = "renesas,i2c-r8a7791";
 488                 reg = <0 0xe6520000 0 0x40>;
 489                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 491                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 492                 i2c-scl-internal-delay-ns = <6>;
 493                 status = "disabled";
 494         };
 495
 496         i2c5: i2c@e6528000 {
 497                 /* doesn't need pinmux */
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 compatible = "renesas,i2c-r8a7791";
 501                 reg = <0 0xe6528000 0 0x40>;
 502                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 504                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 505                 i2c-scl-internal-delay-ns = <110>;
 506                 status = "disabled";
 507         };
 508
 509         i2c6: i2c@e60b0000 {
 510                 /* doesn't need pinmux */
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 514                 reg = <0 0xe60b0000 0 0x425>;
 515                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 517                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 518                 dma-names = "tx", "rx";
 519                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 520                 status = "disabled";
 521         };
 522
 523         i2c7: i2c@e6500000 {
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 527                 reg = <0 0xe6500000 0 0x425>;
 528                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 529                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 530                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 531                 dma-names = "tx", "rx";
 532                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 533                 status = "disabled";
 534         };
 535
 536         i2c8: i2c@e6510000 {
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 540                 reg = <0 0xe6510000 0 0x425>;
 541                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 542                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 543                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 544                 dma-names = "tx", "rx";
 545                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 546                 status = "disabled";
 547         };
 548
 549         pfc: pfc@e6060000 {
 550                 compatible = "renesas,pfc-r8a7791";
 551                 reg = <0 0xe6060000 0 0x250>;
 552         };
 553
 554         mmcif0: mmc@ee200000 {
 555                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 556                 reg = <0 0xee200000 0 0x80>;
 557                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 559                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 560                 dma-names = "tx", "rx";
 561                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 562                 reg-io-width = <4>;
 563                 status = "disabled";
 564                 max-frequency = <97500000>;
 565         };
 566
 567         sdhi0: sd@ee100000 {
 568                 compatible = "renesas,sdhi-r8a7791";
 569                 reg = <0 0xee100000 0 0x328>;
 570                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 572                 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 573                 dma-names = "tx", "rx";
 574                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 575                 status = "disabled";
 576         };
 577
 578         sdhi1: sd@ee140000 {
 579                 compatible = "renesas,sdhi-r8a7791";
 580                 reg = <0 0xee140000 0 0x100>;
 581                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 582                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 583                 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 584                 dma-names = "tx", "rx";
 585                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 586                 status = "disabled";
 587         };
 588
 589         sdhi2: sd@ee160000 {
 590                 compatible = "renesas,sdhi-r8a7791";
 591                 reg = <0 0xee160000 0 0x100>;
 592                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 594                 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 595                 dma-names = "tx", "rx";
 596                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 597                 status = "disabled";
 598         };
 599
 600         scifa0: serial@e6c40000 {
 601                 compatible = "renesas,scifa-r8a7791",
 602                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 603                 reg = <0 0xe6c40000 0 64>;
 604                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 606                 clock-names = "fck";
 607                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 608                 dma-names = "tx", "rx";
 609                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 610                 status = "disabled";
 611         };
 612
 613         scifa1: serial@e6c50000 {
 614                 compatible = "renesas,scifa-r8a7791",
 615                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 616                 reg = <0 0xe6c50000 0 64>;
 617                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 618                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 619                 clock-names = "fck";
 620                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 621                 dma-names = "tx", "rx";
 622                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 623                 status = "disabled";
 624         };
 625
 626         scifa2: serial@e6c60000 {
 627                 compatible = "renesas,scifa-r8a7791",
 628                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 629                 reg = <0 0xe6c60000 0 64>;
 630                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 631                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 632                 clock-names = "fck";
 633                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 634                 dma-names = "tx", "rx";
 635                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 636                 status = "disabled";
 637         };
 638
 639         scifa3: serial@e6c70000 {
 640                 compatible = "renesas,scifa-r8a7791",
 641                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 642                 reg = <0 0xe6c70000 0 64>;
 643                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 645                 clock-names = "fck";
 646                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 647                 dma-names = "tx", "rx";
 648                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 649                 status = "disabled";
 650         };
 651
 652         scifa4: serial@e6c78000 {
 653                 compatible = "renesas,scifa-r8a7791",
 654                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 655                 reg = <0 0xe6c78000 0 64>;
 656                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 657                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 658                 clock-names = "fck";
 659                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 660                 dma-names = "tx", "rx";
 661                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 662                 status = "disabled";
 663         };
 664
 665         scifa5: serial@e6c80000 {
 666                 compatible = "renesas,scifa-r8a7791",
 667                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 668                 reg = <0 0xe6c80000 0 64>;
 669                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 670                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 671                 clock-names = "fck";
 672                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 673                 dma-names = "tx", "rx";
 674                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 675                 status = "disabled";
 676         };
 677
 678         scifb0: serial@e6c20000 {
 679                 compatible = "renesas,scifb-r8a7791",
 680                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 681                 reg = <0 0xe6c20000 0 64>;
 682                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 683                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 684                 clock-names = "fck";
 685                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 686                 dma-names = "tx", "rx";
 687                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 688                 status = "disabled";
 689         };
 690
 691         scifb1: serial@e6c30000 {
 692                 compatible = "renesas,scifb-r8a7791",
 693                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 694                 reg = <0 0xe6c30000 0 64>;
 695                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 697                 clock-names = "fck";
 698                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 699                 dma-names = "tx", "rx";
 700                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 701                 status = "disabled";
 702         };
 703
 704         scifb2: serial@e6ce0000 {
 705                 compatible = "renesas,scifb-r8a7791",
 706                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 707                 reg = <0 0xe6ce0000 0 64>;
 708                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 710                 clock-names = "fck";
 711                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 712                 dma-names = "tx", "rx";
 713                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 714                 status = "disabled";
 715         };
 716
 717         scif0: serial@e6e60000 {
 718                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 719                              "renesas,scif";
 720                 reg = <0 0xe6e60000 0 64>;
 721                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 722                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
 723                          <&scif_clk>;
 724                 clock-names = "fck", "brg_int", "scif_clk";
 725                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 726                 dma-names = "tx", "rx";
 727                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 728                 status = "disabled";
 729         };
 730
 731         scif1: serial@e6e68000 {
 732                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 733                              "renesas,scif";
 734                 reg = <0 0xe6e68000 0 64>;
 735                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 736                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
 737                          <&scif_clk>;
 738                 clock-names = "fck", "brg_int", "scif_clk";
 739                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 740                 dma-names = "tx", "rx";
 741                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 742                 status = "disabled";
 743         };
 744
 745         scif2: serial@e6e58000 {
 746                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 747                              "renesas,scif";
 748                 reg = <0 0xe6e58000 0 64>;
 749                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 750                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
 751                          <&scif_clk>;
 752                 clock-names = "fck", "brg_int", "scif_clk";
 753                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 754                 dma-names = "tx", "rx";
 755                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 756                 status = "disabled";
 757         };
 758
 759         scif3: serial@e6ea8000 {
 760                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 761                              "renesas,scif";
 762                 reg = <0 0xe6ea8000 0 64>;
 763                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 764                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
 765                          <&scif_clk>;
 766                 clock-names = "fck", "brg_int", "scif_clk";
 767                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 768                 dma-names = "tx", "rx";
 769                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 770                 status = "disabled";
 771         };
 772
 773         scif4: serial@e6ee0000 {
 774                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 775                              "renesas,scif";
 776                 reg = <0 0xe6ee0000 0 64>;
 777                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
 779                          <&scif_clk>;
 780                 clock-names = "fck", "brg_int", "scif_clk";
 781                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 782                 dma-names = "tx", "rx";
 783                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 784                 status = "disabled";
 785         };
 786
 787         scif5: serial@e6ee8000 {
 788                 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 789                              "renesas,scif";
 790                 reg = <0 0xe6ee8000 0 64>;
 791                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 792                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
 793                          <&scif_clk>;
 794                 clock-names = "fck", "brg_int", "scif_clk";
 795                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 796                 dma-names = "tx", "rx";
 797                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 798                 status = "disabled";
 799         };
 800
 801         hscif0: serial@e62c0000 {
 802                 compatible = "renesas,hscif-r8a7791",
 803                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 804                 reg = <0 0xe62c0000 0 96>;
 805                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 806                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
 807                          <&scif_clk>;
 808                 clock-names = "fck", "brg_int", "scif_clk";
 809                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 810                 dma-names = "tx", "rx";
 811                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 812                 status = "disabled";
 813         };
 814
 815         hscif1: serial@e62c8000 {
 816                 compatible = "renesas,hscif-r8a7791",
 817                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 818                 reg = <0 0xe62c8000 0 96>;
 819                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 820                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
 821                          <&scif_clk>;
 822                 clock-names = "fck", "brg_int", "scif_clk";
 823                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 824                 dma-names = "tx", "rx";
 825                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 826                 status = "disabled";
 827         };
 828
 829         hscif2: serial@e62d0000 {
 830                 compatible = "renesas,hscif-r8a7791",
 831                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 832                 reg = <0 0xe62d0000 0 96>;
 833                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 834                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
 835                          <&scif_clk>;
 836                 clock-names = "fck", "brg_int", "scif_clk";
 837                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 838                 dma-names = "tx", "rx";
 839                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 840                 status = "disabled";
 841         };
 842
 843         ether: ethernet@ee700000 {
 844                 compatible = "renesas,ether-r8a7791";
 845                 reg = <0 0xee700000 0 0x400>;
 846                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 847                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 848                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 849                 phy-mode = "rmii";
 850                 #address-cells = <1>;
 851                 #size-cells = <0>;
 852                 status = "disabled";
 853         };
 854
 855         avb: ethernet@e6800000 {
 856                 compatible = "renesas,etheravb-r8a7791",
 857                              "renesas,etheravb-rcar-gen2";
 858                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 859                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
 861                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 862                 #address-cells = <1>;
 863                 #size-cells = <0>;
 864                 status = "disabled";
 865         };
 866
 867         sata0: sata@ee300000 {
 868                 compatible = "renesas,sata-r8a7791";
 869                 reg = <0 0xee300000 0 0x2000>;
 870                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 871                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 872                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 873                 status = "disabled";
 874         };
 875
 876         sata1: sata@ee500000 {
 877                 compatible = "renesas,sata-r8a7791";
 878                 reg = <0 0xee500000 0 0x2000>;
 879                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 880                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 881                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 882                 status = "disabled";
 883         };
 884
 885         hsusb: usb@e6590000 {
 886                 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
 887                 reg = <0 0xe6590000 0 0x100>;
 888                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 889                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 890                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 891                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 892                 dma-names = "ch0", "ch1", "ch2", "ch3";
 893                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 894                 renesas,buswait = <4>;
 895                 phys = <&usb0 1>;
 896                 phy-names = "usb";
 897                 status = "disabled";
 898         };
 899
 900         usbphy: usb-phy@e6590100 {
 901                 compatible = "renesas,usb-phy-r8a7791";
 902                 reg = <0 0xe6590100 0 0x100>;
 903                 #address-cells = <1>;
 904                 #size-cells = <0>;
 905                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 906                 clock-names = "usbhs";
 907                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 908                 status = "disabled";
 909
 910                 usb0: usb-channel@0 {
 911                         reg = <0>;
 912                         #phy-cells = <1>;
 913                 };
 914                 usb2: usb-channel@2 {
 915                         reg = <2>;
 916                         #phy-cells = <1>;
 917                 };
 918         };
 919
 920         vin0: video@e6ef0000 {
 921                 compatible = "renesas,vin-r8a7791";
 922                 reg = <0 0xe6ef0000 0 0x1000>;
 923                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 924                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 925                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 926                 status = "disabled";
 927         };
 928
 929         vin1: video@e6ef1000 {
 930                 compatible = "renesas,vin-r8a7791";
 931                 reg = <0 0xe6ef1000 0 0x1000>;
 932                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 933                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 934                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 935                 status = "disabled";
 936         };
 937
 938         vin2: video@e6ef2000 {
 939                 compatible = "renesas,vin-r8a7791";
 940                 reg = <0 0xe6ef2000 0 0x1000>;
 941                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 942                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 943                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 944                 status = "disabled";
 945         };
 946
 947         vsp1@fe928000 {
 948                 compatible = "renesas,vsp1";
 949                 reg = <0 0xfe928000 0 0x8000>;
 950                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 951                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
 952                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 953
 954                 renesas,has-lut;
 955                 renesas,has-sru;
 956                 renesas,#rpf = <5>;
 957                 renesas,#uds = <3>;
 958                 renesas,#wpf = <4>;
 959         };
 960
 961         vsp1@fe930000 {
 962                 compatible = "renesas,vsp1";
 963                 reg = <0 0xfe930000 0 0x8000>;
 964                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 965                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
 966                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 967
 968                 renesas,has-lif;
 969                 renesas,has-lut;
 970                 renesas,#rpf = <4>;
 971                 renesas,#uds = <1>;
 972                 renesas,#wpf = <4>;
 973         };
 974
 975         vsp1@fe938000 {
 976                 compatible = "renesas,vsp1";
 977                 reg = <0 0xfe938000 0 0x8000>;
 978                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 979                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
 980                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 981
 982                 renesas,has-lif;
 983                 renesas,has-lut;
 984                 renesas,#rpf = <4>;
 985                 renesas,#uds = <1>;
 986                 renesas,#wpf = <4>;
 987         };
 988
 989         du: display@feb00000 {
 990                 compatible = "renesas,du-r8a7791";
 991                 reg = <0 0xfeb00000 0 0x40000>,
 992                       <0 0xfeb90000 0 0x1c>;
 993                 reg-names = "du", "lvds.0";
 994                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 995                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 996                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
 997                          <&mstp7_clks R8A7791_CLK_DU1>,
 998                          <&mstp7_clks R8A7791_CLK_LVDS0>;
 999                 clock-names = "du.0", "du.1", "lvds.0";
1000                 status = "disabled";
1001
1002                 ports {
1003                         #address-cells = <1>;
1004                         #size-cells = <0>;
1005
1006                         port@0 {
1007                                 reg = <0>;
1008                                 du_out_rgb: endpoint {
1009                                 };
1010                         };
1011                         port@1 {
1012                                 reg = <1>;
1013                                 du_out_lvds0: endpoint {
1014                                 };
1015                         };
1016                 };
1017         };
1018
1019         can0: can@e6e80000 {
1020                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1021                 reg = <0 0xe6e80000 0 0x1000>;
1022                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1023                 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1024                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1025                 clock-names = "clkp1", "clkp2", "can_clk";
1026                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1027                 status = "disabled";
1028         };
1029
1030         can1: can@e6e88000 {
1031                 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1032                 reg = <0 0xe6e88000 0 0x1000>;
1033                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1034                 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1035                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1036                 clock-names = "clkp1", "clkp2", "can_clk";
1037                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1038                 status = "disabled";
1039         };
1040
1041         jpu: jpeg-codec@fe980000 {
1042                 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
1043                 reg = <0 0xfe980000 0 0x10300>;
1044                 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1045                 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
1046                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1047         };
1048
1049         clocks {
1050                 #address-cells = <2>;
1051                 #size-cells = <2>;
1052                 ranges;
1053
1054                 /* External root clock */
1055                 extal_clk: extal {
1056                         compatible = "fixed-clock";
1057                         #clock-cells = <0>;
1058                         /* This value must be overriden by the board. */
1059                         clock-frequency = <0>;
1060                 };
1061
1062                 /*
1063                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1064                  * default. Boards that provide audio clocks should override them.
1065                  */
1066                 audio_clk_a: audio_clk_a {
1067                         compatible = "fixed-clock";
1068                         #clock-cells = <0>;
1069                         clock-frequency = <0>;
1070                 };
1071                 audio_clk_b: audio_clk_b {
1072                         compatible = "fixed-clock";
1073                         #clock-cells = <0>;
1074                         clock-frequency = <0>;
1075                 };
1076                 audio_clk_c: audio_clk_c {
1077                         compatible = "fixed-clock";
1078                         #clock-cells = <0>;
1079                         clock-frequency = <0>;
1080                 };
1081
1082                 /* External PCIe clock - can be overridden by the board */
1083                 pcie_bus_clk: pcie_bus {
1084                         compatible = "fixed-clock";
1085                         #clock-cells = <0>;
1086                         clock-frequency = <0>;
1087                 };
1088
1089                 /* External SCIF clock */
1090                 scif_clk: scif {
1091                         compatible = "fixed-clock";
1092                         #clock-cells = <0>;
1093                         /* This value must be overridden by the board. */
1094                         clock-frequency = <0>;
1095                 };
1096
1097                 /* External USB clock - can be overridden by the board */
1098                 usb_extal_clk: usb_extal {
1099                         compatible = "fixed-clock";
1100                         #clock-cells = <0>;
1101                         clock-frequency = <48000000>;
1102                 };
1103
1104                 /* External CAN clock */
1105                 can_clk: can_clk {
1106                         compatible = "fixed-clock";
1107                         #clock-cells = <0>;
1108                         /* This value must be overridden by the board. */
1109                         clock-frequency = <0>;
1110                 };
1111
1112                 /* Special CPG clocks */
1113                 cpg_clocks: cpg_clocks@e6150000 {
1114                         compatible = "renesas,r8a7791-cpg-clocks",
1115                                      "renesas,rcar-gen2-cpg-clocks";
1116                         reg = <0 0xe6150000 0 0x1000>;
1117                         clocks = <&extal_clk &usb_extal_clk>;
1118                         #clock-cells = <1>;
1119                         clock-output-names = "main", "pll0", "pll1", "pll3",
1120                                              "lb", "qspi", "sdh", "sd0", "z",
1121                                              "rcan", "adsp";
1122                         #power-domain-cells = <0>;
1123                 };
1124
1125                 /* Variable factor clocks */
1126                 sd2_clk: sd2@e6150078 {
1127                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1128                         reg = <0 0xe6150078 0 4>;
1129                         clocks = <&pll1_div2_clk>;
1130                         #clock-cells = <0>;
1131                 };
1132                 sd3_clk: sd3@e615026c {
1133                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1134                         reg = <0 0xe615026c 0 4>;
1135                         clocks = <&pll1_div2_clk>;
1136                         #clock-cells = <0>;
1137                 };
1138                 mmc0_clk: mmc0@e6150240 {
1139                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1140                         reg = <0 0xe6150240 0 4>;
1141                         clocks = <&pll1_div2_clk>;
1142                         #clock-cells = <0>;
1143                 };
1144                 ssp_clk: ssp@e6150248 {
1145                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1146                         reg = <0 0xe6150248 0 4>;
1147                         clocks = <&pll1_div2_clk>;
1148                         #clock-cells = <0>;
1149                 };
1150                 ssprs_clk: ssprs@e615024c {
1151                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1152                         reg = <0 0xe615024c 0 4>;
1153                         clocks = <&pll1_div2_clk>;
1154                         #clock-cells = <0>;
1155                 };
1156
1157                 /* Fixed factor clocks */
1158                 pll1_div2_clk: pll1_div2 {
1159                         compatible = "fixed-factor-clock";
1160                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1161                         #clock-cells = <0>;
1162                         clock-div = <2>;
1163                         clock-mult = <1>;
1164                 };
1165                 zg_clk: zg {
1166                         compatible = "fixed-factor-clock";
1167                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1168                         #clock-cells = <0>;
1169                         clock-div = <3>;
1170                         clock-mult = <1>;
1171                 };
1172                 zx_clk: zx {
1173                         compatible = "fixed-factor-clock";
1174                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1175                         #clock-cells = <0>;
1176                         clock-div = <3>;
1177                         clock-mult = <1>;
1178                 };
1179                 zs_clk: zs {
1180                         compatible = "fixed-factor-clock";
1181                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1182                         #clock-cells = <0>;
1183                         clock-div = <6>;
1184                         clock-mult = <1>;
1185                 };
1186                 hp_clk: hp {
1187                         compatible = "fixed-factor-clock";
1188                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1189                         #clock-cells = <0>;
1190                         clock-div = <12>;
1191                         clock-mult = <1>;
1192                 };
1193                 i_clk: i {
1194                         compatible = "fixed-factor-clock";
1195                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1196                         #clock-cells = <0>;
1197                         clock-div = <2>;
1198                         clock-mult = <1>;
1199                 };
1200                 b_clk: b {
1201                         compatible = "fixed-factor-clock";
1202                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1203                         #clock-cells = <0>;
1204                         clock-div = <12>;
1205                         clock-mult = <1>;
1206                 };
1207                 p_clk: p {
1208                         compatible = "fixed-factor-clock";
1209                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1210                         #clock-cells = <0>;
1211                         clock-div = <24>;
1212                         clock-mult = <1>;
1213                 };
1214                 cl_clk: cl {
1215                         compatible = "fixed-factor-clock";
1216                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1217                         #clock-cells = <0>;
1218                         clock-div = <48>;
1219                         clock-mult = <1>;
1220                 };
1221                 m2_clk: m2 {
1222                         compatible = "fixed-factor-clock";
1223                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1224                         #clock-cells = <0>;
1225                         clock-div = <8>;
1226                         clock-mult = <1>;
1227                 };
1228                 rclk_clk: rclk {
1229                         compatible = "fixed-factor-clock";
1230                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1231                         #clock-cells = <0>;
1232                         clock-div = <(48 * 1024)>;
1233                         clock-mult = <1>;
1234                 };
1235                 oscclk_clk: oscclk {
1236                         compatible = "fixed-factor-clock";
1237                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1238                         #clock-cells = <0>;
1239                         clock-div = <(12 * 1024)>;
1240                         clock-mult = <1>;
1241                 };
1242                 zb3_clk: zb3 {
1243                         compatible = "fixed-factor-clock";
1244                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1245                         #clock-cells = <0>;
1246                         clock-div = <4>;
1247                         clock-mult = <1>;
1248                 };
1249                 zb3d2_clk: zb3d2 {
1250                         compatible = "fixed-factor-clock";
1251                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1252                         #clock-cells = <0>;
1253                         clock-div = <8>;
1254                         clock-mult = <1>;
1255                 };
1256                 ddr_clk: ddr {
1257                         compatible = "fixed-factor-clock";
1258                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1259                         #clock-cells = <0>;
1260                         clock-div = <8>;
1261                         clock-mult = <1>;
1262                 };
1263                 mp_clk: mp {
1264                         compatible = "fixed-factor-clock";
1265                         clocks = <&pll1_div2_clk>;
1266                         #clock-cells = <0>;
1267                         clock-div = <15>;
1268                         clock-mult = <1>;
1269                 };
1270                 cp_clk: cp {
1271                         compatible = "fixed-factor-clock";
1272                         clocks = <&extal_clk>;
1273                         #clock-cells = <0>;
1274                         clock-div = <2>;
1275                         clock-mult = <1>;
1276                 };
1277
1278                 /* Gate clocks */
1279                 mstp0_clks: mstp0_clks@e6150130 {
1280                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1281                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1282                         clocks = <&mp_clk>;
1283                         #clock-cells = <1>;
1284                         clock-indices = <R8A7791_CLK_MSIOF0>;
1285                         clock-output-names = "msiof0";
1286                 };
1287                 mstp1_clks: mstp1_clks@e6150134 {
1288                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1289                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1290                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1291                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1292                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1293                                  <&zs_clk>;
1294                         #clock-cells = <1>;
1295                         clock-indices = <
1296                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1297                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1298                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1299                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1300                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1301                                 R8A7791_CLK_VSP1_S
1302                         >;
1303                         clock-output-names =
1304                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1305                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1306                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1307                 };
1308                 mstp2_clks: mstp2_clks@e6150138 {
1309                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1310                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1311                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1312                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1313                                  <&zs_clk>, <&zs_clk>;
1314                         #clock-cells = <1>;
1315                         clock-indices = <
1316                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1317                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1318                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1319                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1320                         >;
1321                         clock-output-names =
1322                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1323                                 "scifb1", "msiof1", "scifb2",
1324                                 "sys-dmac1", "sys-dmac0";
1325                 };
1326                 mstp3_clks: mstp3_clks@e615013c {
1327                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1328                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1329                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1330                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1331                                  <&hp_clk>, <&hp_clk>;
1332                         #clock-cells = <1>;
1333                         clock-indices = <
1334                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1335                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1336                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1337                                 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1338                         >;
1339                         clock-output-names =
1340                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1341                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1342                                 "usbdmac0", "usbdmac1";
1343                 };
1344                 mstp4_clks: mstp4_clks@e6150140 {
1345                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1346                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1347                         clocks = <&cp_clk>;
1348                         #clock-cells = <1>;
1349                         clock-indices = <R8A7791_CLK_IRQC>;
1350                         clock-output-names = "irqc";
1351                 };
1352                 mstp5_clks: mstp5_clks@e6150144 {
1353                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1354                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1355                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1356                                  <&extal_clk>, <&p_clk>;
1357                         #clock-cells = <1>;
1358                         clock-indices = <
1359                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1360                                 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1361                                 R8A7791_CLK_PWM
1362                         >;
1363                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1364                                              "thermal", "pwm";
1365                 };
1366                 mstp7_clks: mstp7_clks@e615014c {
1367                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1368                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1369                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1370                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1371                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1372                         #clock-cells = <1>;
1373                         clock-indices = <
1374                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1375                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1376                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1377                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1378                                 R8A7791_CLK_LVDS0
1379                         >;
1380                         clock-output-names =
1381                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1382                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1383                 };
1384                 mstp8_clks: mstp8_clks@e6150990 {
1385                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1386                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1387                         clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1388                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1389                                  <&zs_clk>;
1390                         #clock-cells = <1>;
1391                         clock-indices = <
1392                                 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1393                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1394                                 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1395                                 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1396                         >;
1397                         clock-output-names =
1398                                 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1399                                 "etheravb", "ether", "sata1", "sata0";
1400                 };
1401                 mstp9_clks: mstp9_clks@e6150994 {
1402                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1403                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1404                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1405                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1406                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1407                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1408                                  <&hp_clk>, <&hp_clk>;
1409                         #clock-cells = <1>;
1410                         clock-indices = <
1411                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1412                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1413                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1414                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1415                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1416                         >;
1417                         clock-output-names =
1418                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1419                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1420                                 "i2c1", "i2c0";
1421                 };
1422                 mstp10_clks: mstp10_clks@e6150998 {
1423                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1424                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1425                         clocks = <&p_clk>,
1426                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1427                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1428                                 <&p_clk>,
1429                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1430                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1431                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1432                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1433                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1434                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1435                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1436
1437                         #clock-cells = <1>;
1438                         clock-indices = <
1439                                 R8A7791_CLK_SSI_ALL
1440                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1441                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1442                                 R8A7791_CLK_SCU_ALL
1443                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1444                                 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1445                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1446                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1447                         >;
1448                         clock-output-names =
1449                                 "ssi-all",
1450                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1451                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1452                                 "scu-all",
1453                                 "scu-dvc1", "scu-dvc0",
1454                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1455                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1456                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1457                 };
1458                 mstp11_clks: mstp11_clks@e615099c {
1459                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1460                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1461                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1462                         #clock-cells = <1>;
1463                         clock-indices = <
1464                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1465                         >;
1466                         clock-output-names = "scifa3", "scifa4", "scifa5";
1467                 };
1468         };
1469
1470         sysc: system-controller@e6180000 {
1471                 compatible = "renesas,r8a7791-sysc";
1472                 reg = <0 0xe6180000 0 0x0200>;
1473                 #power-domain-cells = <1>;
1474         };
1475
1476         qspi: spi@e6b10000 {
1477                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1478                 reg = <0 0xe6b10000 0 0x2c>;
1479                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1480                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1481                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1482                 dma-names = "tx", "rx";
1483                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1484                 num-cs = <1>;
1485                 #address-cells = <1>;
1486                 #size-cells = <0>;
1487                 status = "disabled";
1488         };
1489
1490         msiof0: spi@e6e20000 {
1491                 compatible = "renesas,msiof-r8a7791";
1492                 reg = <0 0xe6e20000 0 0x0064>;
1493                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1494                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1495                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1496                 dma-names = "tx", "rx";
1497                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1498                 #address-cells = <1>;
1499                 #size-cells = <0>;
1500                 status = "disabled";
1501         };
1502
1503         msiof1: spi@e6e10000 {
1504                 compatible = "renesas,msiof-r8a7791";
1505                 reg = <0 0xe6e10000 0 0x0064>;
1506                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1507                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1508                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1509                 dma-names = "tx", "rx";
1510                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1511                 #address-cells = <1>;
1512                 #size-cells = <0>;
1513                 status = "disabled";
1514         };
1515
1516         msiof2: spi@e6e00000 {
1517                 compatible = "renesas,msiof-r8a7791";
1518                 reg = <0 0xe6e00000 0 0x0064>;
1519                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1520                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1521                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1522                 dma-names = "tx", "rx";
1523                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1524                 #address-cells = <1>;
1525                 #size-cells = <0>;
1526                 status = "disabled";
1527         };
1528
1529         xhci: usb@ee000000 {
1530                 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
1531                 reg = <0 0xee000000 0 0xc00>;
1532                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1533                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1534                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1535                 phys = <&usb2 1>;
1536                 phy-names = "usb";
1537                 status = "disabled";
1538         };
1539
1540         pci0: pci@ee090000 {
1541                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1542                 device_type = "pci";
1543                 reg = <0 0xee090000 0 0xc00>,
1544                       <0 0xee080000 0 0x1100>;
1545                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1546                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1547                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1548                 status = "disabled";
1549
1550                 bus-range = <0 0>;
1551                 #address-cells = <3>;
1552                 #size-cells = <2>;
1553                 #interrupt-cells = <1>;
1554                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1555                 interrupt-map-mask = <0xff00 0 0 0x7>;
1556                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1557                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1558                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1559
1560                 usb@0,1 {
1561                         reg = <0x800 0 0 0 0>;
1562                         device_type = "pci";
1563                         phys = <&usb0 0>;
1564                         phy-names = "usb";
1565                 };
1566
1567                 usb@0,2 {
1568                         reg = <0x1000 0 0 0 0>;
1569                         device_type = "pci";
1570                         phys = <&usb0 0>;
1571                         phy-names = "usb";
1572                 };
1573         };
1574
1575         pci1: pci@ee0d0000 {
1576                 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1577                 device_type = "pci";
1578                 reg = <0 0xee0d0000 0 0xc00>,
1579                       <0 0xee0c0000 0 0x1100>;
1580                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1581                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1582                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1583                 status = "disabled";
1584
1585                 bus-range = <1 1>;
1586                 #address-cells = <3>;
1587                 #size-cells = <2>;
1588                 #interrupt-cells = <1>;
1589                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1590                 interrupt-map-mask = <0xff00 0 0 0x7>;
1591                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1592                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1593                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1594
1595                 usb@0,1 {
1596                         reg = <0x800 0 0 0 0>;
1597                         device_type = "pci";
1598                         phys = <&usb2 0>;
1599                         phy-names = "usb";
1600                 };
1601
1602                 usb@0,2 {
1603                         reg = <0x1000 0 0 0 0>;
1604                         device_type = "pci";
1605                         phys = <&usb2 0>;
1606                         phy-names = "usb";
1607                 };
1608         };
1609
1610         pciec: pcie@fe000000 {
1611                 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
1612                 reg = <0 0xfe000000 0 0x80000>;
1613                 #address-cells = <3>;
1614                 #size-cells = <2>;
1615                 bus-range = <0x00 0xff>;
1616                 device_type = "pci";
1617                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1618                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1619                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1620                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1621                 /* Map all possible DDR as inbound ranges */
1622                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1623                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1624                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1625                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1626                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1627                 #interrupt-cells = <1>;
1628                 interrupt-map-mask = <0 0 0 0>;
1629                 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1630                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1631                 clock-names = "pcie", "pcie_bus";
1632                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1633                 status = "disabled";
1634         };
1635
1636         ipmmu_sy0: mmu@e6280000 {
1637                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1638                 reg = <0 0xe6280000 0 0x1000>;
1639                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1640                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1641                 #iommu-cells = <1>;
1642                 status = "disabled";
1643         };
1644
1645         ipmmu_sy1: mmu@e6290000 {
1646                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1647                 reg = <0 0xe6290000 0 0x1000>;
1648                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1649                 #iommu-cells = <1>;
1650                 status = "disabled";
1651         };
1652
1653         ipmmu_ds: mmu@e6740000 {
1654                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1655                 reg = <0 0xe6740000 0 0x1000>;
1656                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1657                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1658                 #iommu-cells = <1>;
1659                 status = "disabled";
1660         };
1661
1662         ipmmu_mp: mmu@ec680000 {
1663                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1664                 reg = <0 0xec680000 0 0x1000>;
1665                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1666                 #iommu-cells = <1>;
1667                 status = "disabled";
1668         };
1669
1670         ipmmu_mx: mmu@fe951000 {
1671                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1672                 reg = <0 0xfe951000 0 0x1000>;
1673                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1674                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1675                 #iommu-cells = <1>;
1676                 status = "disabled";
1677         };
1678
1679         ipmmu_rt: mmu@ffc80000 {
1680                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1681                 reg = <0 0xffc80000 0 0x1000>;
1682                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1683                 #iommu-cells = <1>;
1684                 status = "disabled";
1685         };
1686
1687         ipmmu_gp: mmu@e62a0000 {
1688                 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1689                 reg = <0 0xe62a0000 0 0x1000>;
1690                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1691                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1692                 #iommu-cells = <1>;
1693                 status = "disabled";
1694         };
1695
1696         rcar_sound: sound@ec500000 {
1697                 /*
1698                  * #sound-dai-cells is required
1699                  *
1700                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1701                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1702                  */
1703                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1704                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1705                         <0 0xec5a0000 0 0x100>,  /* ADG */
1706                         <0 0xec540000 0 0x1000>, /* SSIU */
1707                         <0 0xec541000 0 0x280>,  /* SSI */
1708                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1709                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1710
1711                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1712                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1713                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1714                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1715                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1716                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1717                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1718                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1719                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1720                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1721                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1722                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1723                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1724                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1725                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1726                 clock-names = "ssi-all",
1727                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1728                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1729                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1730                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1731                                 "ctu.0", "ctu.1",
1732                                 "mix.0", "mix.1",
1733                                 "dvc.0", "dvc.1",
1734                                 "clk_a", "clk_b", "clk_c", "clk_i";
1735                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1736
1737                 status = "disabled";
1738
1739                 rcar_sound,dvc {
1740                         dvc0: dvc@0 {
1741                                 dmas = <&audma0 0xbc>;
1742                                 dma-names = "tx";
1743                         };
1744                         dvc1: dvc@1 {
1745                                 dmas = <&audma0 0xbe>;
1746                                 dma-names = "tx";
1747                         };
1748                 };
1749
1750                 rcar_sound,mix {
1751                         mix0: mix@0 { };
1752                         mix1: mix@1 { };
1753                 };
1754
1755                 rcar_sound,ctu {
1756                         ctu00: ctu@0 { };
1757                         ctu01: ctu@1 { };
1758                         ctu02: ctu@2 { };
1759                         ctu03: ctu@3 { };
1760                         ctu10: ctu@4 { };
1761                         ctu11: ctu@5 { };
1762                         ctu12: ctu@6 { };
1763                         ctu13: ctu@7 { };
1764                 };
1765
1766                 rcar_sound,src {
1767                         src0: src@0 {
1768                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1769                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1770                                 dma-names = "rx", "tx";
1771                         };
1772                         src1: src@1 {
1773                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1774                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1775                                 dma-names = "rx", "tx";
1776                         };
1777                         src2: src@2 {
1778                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1779                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1780                                 dma-names = "rx", "tx";
1781                         };
1782                         src3: src@3 {
1783                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1784                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1785                                 dma-names = "rx", "tx";
1786                         };
1787                         src4: src@4 {
1788                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1789                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1790                                 dma-names = "rx", "tx";
1791                         };
1792                         src5: src@5 {
1793                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1794                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1795                                 dma-names = "rx", "tx";
1796                         };
1797                         src6: src@6 {
1798                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1799                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1800                                 dma-names = "rx", "tx";
1801                         };
1802                         src7: src@7 {
1803                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1804                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1805                                 dma-names = "rx", "tx";
1806                         };
1807                         src8: src@8 {
1808                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1809                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1810                                 dma-names = "rx", "tx";
1811                         };
1812                         src9: src@9 {
1813                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1814                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1815                                 dma-names = "rx", "tx";
1816                         };
1817                 };
1818
1819                 rcar_sound,ssi {
1820                         ssi0: ssi@0 {
1821                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1822                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1823                                 dma-names = "rx", "tx", "rxu", "txu";
1824                         };
1825                         ssi1: ssi@1 {
1826                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1827                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1828                                 dma-names = "rx", "tx", "rxu", "txu";
1829                         };
1830                         ssi2: ssi@2 {
1831                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1832                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1833                                 dma-names = "rx", "tx", "rxu", "txu";
1834                         };
1835                         ssi3: ssi@3 {
1836                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1837                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1838                                 dma-names = "rx", "tx", "rxu", "txu";
1839                         };
1840                         ssi4: ssi@4 {
1841                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1842                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1843                                 dma-names = "rx", "tx", "rxu", "txu";
1844                         };
1845                         ssi5: ssi@5 {
1846                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1847                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1848                                 dma-names = "rx", "tx", "rxu", "txu";
1849                         };
1850                         ssi6: ssi@6 {
1851                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1852                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1853                                 dma-names = "rx", "tx", "rxu", "txu";
1854                         };
1855                         ssi7: ssi@7 {
1856                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1857                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1858                                 dma-names = "rx", "tx", "rxu", "txu";
1859                         };
1860                         ssi8: ssi@8 {
1861                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1862                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1863                                 dma-names = "rx", "tx", "rxu", "txu";
1864                         };
1865                         ssi9: ssi@9 {
1866                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1867                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1868                                 dma-names = "rx", "tx", "rxu", "txu";
1869                         };
1870                 };
1871         };
1872 };