2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
66 device_type = "memory";
67 reg = <0x60000000 0x40000000>;
73 enable-method = "rockchip,rk3036-smp";
77 compatible = "arm,cortex-a7";
79 resets = <&cru SRST_CORE0>;
84 clock-latency = <40000>;
85 clocks = <&cru ARMCLK>;
90 compatible = "arm,cortex-a7";
92 resets = <&cru SRST_CORE1>;
97 compatible = "arm,amba-bus";
102 pdma: pdma@20078000 {
103 compatible = "arm,pl330", "arm,primecell";
104 reg = <0x20078000 0x4000>;
105 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&cru ACLK_DMAC2>;
109 clock-names = "apb_pclk";
114 compatible = "arm,cortex-a7-pmu";
115 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
121 compatible = "arm,armv7-timer";
122 arm,cpu-registers-not-fw-configured;
123 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
124 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
125 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
126 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
127 clock-frequency = <24000000>;
131 compatible = "fixed-clock";
132 clock-frequency = <24000000>;
133 clock-output-names = "xin24m";
137 bus_intmem@10080000 {
138 compatible = "mmio-sram";
139 reg = <0x10080000 0x2000>;
140 #address-cells = <1>;
142 ranges = <0 0x10080000 0x2000>;
145 compatible = "rockchip,rk3066-smp-sram";
150 gic: interrupt-controller@10139000 {
151 compatible = "arm,gic-400";
152 interrupt-controller;
153 #interrupt-cells = <3>;
154 #address-cells = <0>;
156 reg = <0x10139000 0x1000>,
160 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
163 usb_otg: usb@10180000 {
164 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
166 reg = <0x10180000 0x40000>;
167 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&cru HCLK_OTG0>;
171 g-np-tx-fifo-size = <16>;
172 g-rx-fifo-size = <275>;
173 g-tx-fifo-size = <256 128 128 64 64 32>;
178 usb_host: usb@101c0000 {
179 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
181 reg = <0x101c0000 0x40000>;
182 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru HCLK_OTG1>;
189 emac: ethernet@10200000 {
190 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
191 reg = <0x10200000 0x4000>;
192 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
195 rockchip,grf = <&grf>;
196 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
197 clock-names = "hclk", "macref", "macclk";
199 * Fix the emac parent clock is DPLL instead of APLL.
200 * since that will cause some unstable things if the cpufreq
201 * is working. (e.g: the accurate 50MHz what mac_ref need)
203 assigned-clocks = <&cru SCLK_MACPLL>;
204 assigned-clock-parents = <&cru PLL_DPLL>;
210 sdmmc: dwmmc@10214000 {
211 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
212 reg = <0x10214000 0x4000>;
213 clock-frequency = <37500000>;
214 clock-freq-min-max = <400000 37500000>;
215 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
216 clock-names = "biu", "ciu";
217 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
222 sdio: dwmmc@10218000 {
223 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
224 reg = <0x10218000 0x4000>;
225 clock-freq-min-max = <400000 37500000>;
226 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
227 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
228 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
229 fifo-depth = <0x100>;
230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
234 emmc: dwmmc@1021c000 {
235 compatible = "rockchip,rk3288-dw-mshc";
236 reg = <0x1021c000 0x4000>;
237 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
241 clock-frequency = <37500000>;
242 clock-freq-min-max = <400000 37500000>;
243 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
244 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
245 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
246 default-sample-phase = <158>;
250 fifo-depth = <0x100>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
260 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
261 reg = <0x10220000 0x4000>;
262 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
263 #address-cells = <1>;
265 clock-names = "i2s_hclk", "i2s_clk";
266 clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
267 dmas = <&pdma 0>, <&pdma 1>;
268 dma-names = "tx", "rx";
269 pinctrl-names = "default";
270 pinctrl-0 = <&i2s_bus>;
274 cru: clock-controller@20000000 {
275 compatible = "rockchip,rk3036-cru";
276 reg = <0x20000000 0x1000>;
277 rockchip,grf = <&grf>;
280 assigned-clocks = <&cru PLL_GPLL>;
281 assigned-clock-rates = <594000000>;
284 grf: syscon@20008000 {
285 compatible = "rockchip,rk3036-grf", "syscon";
286 reg = <0x20008000 0x1000>;
289 acodec: acodec-ana@20030000 {
290 compatible = "rk3036-codec";
291 reg = <0x20030000 0x4000>;
292 rockchip,grf = <&grf>;
293 clock-names = "acodec_pclk";
294 clocks = <&cru PCLK_ACODEC>;
298 timer: timer@20044000 {
299 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
300 reg = <0x20044000 0x20>;
301 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&xin24m>, <&cru PCLK_TIMER>;
303 clock-names = "timer", "pclk";
307 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
308 reg = <0x20050000 0x10>;
310 clocks = <&cru PCLK_PWM>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pwm0_pin>;
318 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
319 reg = <0x20050010 0x10>;
321 clocks = <&cru PCLK_PWM>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pwm1_pin>;
329 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
330 reg = <0x20050020 0x10>;
332 clocks = <&cru PCLK_PWM>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pwm2_pin>;
340 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
341 reg = <0x20050030 0x10>;
343 clocks = <&cru PCLK_PWM>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pwm3_pin>;
351 compatible = "rockchip,rk3288-i2c";
352 reg = <0x20056000 0x1000>;
353 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
357 clocks = <&cru PCLK_I2C1>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c1_xfer>;
364 compatible = "rockchip,rk3288-i2c";
365 reg = <0x2005a000 0x1000>;
366 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
370 clocks = <&cru PCLK_I2C2>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c2_xfer>;
376 uart0: serial@20060000 {
377 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
378 reg = <0x20060000 0x100>;
379 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
382 clock-frequency = <24000000>;
383 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
384 clock-names = "baudclk", "apb_pclk";
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
390 uart1: serial@20064000 {
391 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
392 reg = <0x20064000 0x100>;
393 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
396 clock-frequency = <24000000>;
397 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
398 clock-names = "baudclk", "apb_pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&uart1_xfer>;
404 uart2: serial@20068000 {
405 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
406 reg = <0x20068000 0x100>;
407 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
410 clock-frequency = <24000000>;
411 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
412 clock-names = "baudclk", "apb_pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&uart2_xfer>;
419 compatible = "rockchip,rk3288-i2c";
420 reg = <0x20072000 0x1000>;
421 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
425 clocks = <&cru PCLK_I2C0>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c0_xfer>;
432 compatible = "rockchip,rk3036-pinctrl";
433 rockchip,grf = <&grf>;
434 #address-cells = <1>;
438 gpio0: gpio0@2007c000 {
439 compatible = "rockchip,gpio-bank";
440 reg = <0x2007c000 0x100>;
441 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru PCLK_GPIO0>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
451 gpio1: gpio1@20080000 {
452 compatible = "rockchip,gpio-bank";
453 reg = <0x20080000 0x100>;
454 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru PCLK_GPIO1>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
464 gpio2: gpio2@20084000 {
465 compatible = "rockchip,gpio-bank";
466 reg = <0x20084000 0x100>;
467 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru PCLK_GPIO2>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
477 pcfg_pull_default: pcfg_pull_default {
478 bias-pull-pin-default;
481 pcfg_pull_none: pcfg-pull-none {
487 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
493 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
499 rockchip,pins = <0 1 2 &pcfg_pull_none>;
505 rockchip,pins = <0 27 1 &pcfg_pull_none>;
510 sdmmc_clk: sdmmc-clk {
511 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
514 sdmmc_cmd: sdmmc-cmd {
515 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
519 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
522 sdmmc_bus1: sdmmc-bus1 {
523 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
526 sdmmc_bus4: sdmmc-bus4 {
527 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
528 <1 19 RK_FUNC_1 &pcfg_pull_default>,
529 <1 20 RK_FUNC_1 &pcfg_pull_default>,
530 <1 21 RK_FUNC_1 &pcfg_pull_default>;
535 sdio_bus1: sdio-bus1 {
536 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
539 sdio_bus4: sdio-bus4 {
540 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
541 <0 12 RK_FUNC_1 &pcfg_pull_default>,
542 <0 13 RK_FUNC_1 &pcfg_pull_default>,
543 <0 14 RK_FUNC_1 &pcfg_pull_default>;
547 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
551 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
557 * We run eMMC at max speed; bump up drive strength.
558 * We also have external pulls, so disable the internal ones.
561 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
565 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
568 emmc_bus8: emmc-bus8 {
569 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
570 <1 25 RK_FUNC_2 &pcfg_pull_default>,
571 <1 26 RK_FUNC_2 &pcfg_pull_default>,
572 <1 27 RK_FUNC_2 &pcfg_pull_default>,
573 <1 28 RK_FUNC_2 &pcfg_pull_default>,
574 <1 29 RK_FUNC_2 &pcfg_pull_default>,
575 <1 30 RK_FUNC_2 &pcfg_pull_default>,
576 <1 31 RK_FUNC_2 &pcfg_pull_default>;
581 emac_xfer: emac-xfer {
582 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
583 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
584 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
585 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
586 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
587 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
588 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
589 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
592 emac_mdio: emac-mdio {
593 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
594 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
599 i2c0_xfer: i2c0-xfer {
600 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
601 <0 1 RK_FUNC_1 &pcfg_pull_none>;
606 i2c1_xfer: i2c1-xfer {
607 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
608 <0 3 RK_FUNC_1 &pcfg_pull_none>;
613 i2c2_xfer: i2c2-xfer {
614 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
615 <2 21 RK_FUNC_1 &pcfg_pull_none>;
621 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
622 <1 1 RK_FUNC_1 &pcfg_pull_none>,
623 <1 2 RK_FUNC_1 &pcfg_pull_none>,
624 <1 3 RK_FUNC_1 &pcfg_pull_none>,
625 <1 4 RK_FUNC_1 &pcfg_pull_none>,
626 <1 5 RK_FUNC_1 &pcfg_pull_none>;
631 uart0_xfer: uart0-xfer {
632 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
633 <0 17 RK_FUNC_1 &pcfg_pull_none>;
636 uart0_cts: uart0-cts {
637 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
640 uart0_rts: uart0-rts {
641 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
646 uart1_xfer: uart1-xfer {
647 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
648 <2 23 RK_FUNC_1 &pcfg_pull_none>;
650 /* no rts / cts for uart1 */
654 uart2_xfer: uart2-xfer {
655 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
656 <1 19 RK_FUNC_2 &pcfg_pull_none>;
658 /* no rts / cts for uart2 */