arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3066a-cru.h>
  19 #include "rk3xxx.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3066a";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "rockchip,rk3066-smp";
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x1>;
  40                 };
  41         };
  42
  43         sram: sram@10080000 {
  44                 compatible = "mmio-sram";
  45                 reg = <0x10080000 0x10000>;
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0 0x10080000 0x10000>;
  49
  50                 smp-sram@0 {
  51                         compatible = "rockchip,rk3066-smp-sram";
  52                         reg = <0x0 0x50>;
  53                 };
  54         };
  55
  56         cru: clock-controller@20000000 {
  57                 compatible = "rockchip,rk3066a-cru";
  58                 reg = <0x20000000 0x1000>;
  59                 rockchip,grf = <&grf>;
  60
  61                 #clock-cells = <1>;
  62                 #reset-cells = <1>;
  63         };
  64
  65         timer@2000e000 {
  66                 compatible = "snps,dw-apb-timer-osc";
  67                 reg = <0x2000e000 0x100>;
  68                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  69                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
  70                 clock-names = "timer", "pclk";
  71         };
  72
  73         timer@20038000 {
  74                 compatible = "snps,dw-apb-timer-osc";
  75                 reg = <0x20038000 0x100>;
  76                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
  78                 clock-names = "timer", "pclk";
  79         };
  80
  81         timer@2003a000 {
  82                 compatible = "snps,dw-apb-timer-osc";
  83                 reg = <0x2003a000 0x100>;
  84                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  85                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
  86                 clock-names = "timer", "pclk";
  87         };
  88
  89         pinctrl: pinctrl {
  90                 compatible = "rockchip,rk3066a-pinctrl";
  91                 rockchip,grf = <&grf>;
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 gpio0: gpio0@20034000 {
  97                         compatible = "rockchip,gpio-bank";
  98                         reg = <0x20034000 0x100>;
  99                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 100                         clocks = <&cru PCLK_GPIO0>;
 101
 102                         gpio-controller;
 103                         #gpio-cells = <2>;
 104
 105                         interrupt-controller;
 106                         #interrupt-cells = <2>;
 107                 };
 108
 109                 gpio1: gpio1@2003c000 {
 110                         compatible = "rockchip,gpio-bank";
 111                         reg = <0x2003c000 0x100>;
 112                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 113                         clocks = <&cru PCLK_GPIO1>;
 114
 115                         gpio-controller;
 116                         #gpio-cells = <2>;
 117
 118                         interrupt-controller;
 119                         #interrupt-cells = <2>;
 120                 };
 121
 122                 gpio2: gpio2@2003e000 {
 123                         compatible = "rockchip,gpio-bank";
 124                         reg = <0x2003e000 0x100>;
 125                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&cru PCLK_GPIO2>;
 127
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130
 131                         interrupt-controller;
 132                         #interrupt-cells = <2>;
 133                 };
 134
 135                 gpio3: gpio3@20080000 {
 136                         compatible = "rockchip,gpio-bank";
 137                         reg = <0x20080000 0x100>;
 138                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&cru PCLK_GPIO3>;
 140
 141                         gpio-controller;
 142                         #gpio-cells = <2>;
 143
 144                         interrupt-controller;
 145                         #interrupt-cells = <2>;
 146                 };
 147
 148                 gpio4: gpio4@20084000 {
 149                         compatible = "rockchip,gpio-bank";
 150                         reg = <0x20084000 0x100>;
 151                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 152                         clocks = <&cru PCLK_GPIO4>;
 153
 154                         gpio-controller;
 155                         #gpio-cells = <2>;
 156
 157                         interrupt-controller;
 158                         #interrupt-cells = <2>;
 159                 };
 160
 161                 gpio6: gpio6@2000a000 {
 162                         compatible = "rockchip,gpio-bank";
 163                         reg = <0x2000a000 0x100>;
 164                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 165                         clocks = <&cru PCLK_GPIO6>;
 166
 167                         gpio-controller;
 168                         #gpio-cells = <2>;
 169
 170                         interrupt-controller;
 171                         #interrupt-cells = <2>;
 172                 };
 173
 174                 pcfg_pull_default: pcfg_pull_default {
 175                         bias-pull-pin-default;
 176                 };
 177
 178                 pcfg_pull_none: pcfg_pull_none {
 179                         bias-disable;
 180                 };
 181
 182                 emmc {
 183                         emmc_clk: emmc-clk {
 184                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 185                         };
 186
 187                         emmc_cmd: emmc-cmd {
 188                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 189                         };
 190
 191                         emmc_rst: emmc-rst {
 192                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 193                         };
 194
 195                         /*
 196                          * The data pins are shared between nandc and emmc and
 197                          * not accessible through pinctrl. Also they should've
 198                          * been already set correctly by firmware, as
 199                          * flash/emmc is the boot-device.
 200                          */
 201                 };
 202
 203                 i2c0 {
 204                         i2c0_xfer: i2c0-xfer {
 205                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 206                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 207                         };
 208                 };
 209
 210                 i2c1 {
 211                         i2c1_xfer: i2c1-xfer {
 212                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 213                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 214                         };
 215                 };
 216
 217                 i2c2 {
 218                         i2c2_xfer: i2c2-xfer {
 219                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 220                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 221                         };
 222                 };
 223
 224                 i2c3 {
 225                         i2c3_xfer: i2c3-xfer {
 226                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 227                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 228                         };
 229                 };
 230
 231                 i2c4 {
 232                         i2c4_xfer: i2c4-xfer {
 233                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 234                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 235                         };
 236                 };
 237
 238                 pwm0 {
 239                         pwm0_out: pwm0-out {
 240                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 241                         };
 242                 };
 243
 244                 pwm1 {
 245                         pwm1_out: pwm1-out {
 246                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 247                         };
 248                 };
 249
 250                 pwm2 {
 251                         pwm2_out: pwm2-out {
 252                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 253                         };
 254                 };
 255
 256                 pwm3 {
 257                         pwm3_out: pwm3-out {
 258                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 259                         };
 260                 };
 261
 262                 spi0 {
 263                         spi0_clk: spi0-clk {
 264                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 265                         };
 266                         spi0_cs0: spi0-cs0 {
 267                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 268                         };
 269                         spi0_tx: spi0-tx {
 270                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 271                         };
 272                         spi0_rx: spi0-rx {
 273                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 274                         };
 275                         spi0_cs1: spi0-cs1 {
 276                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 277                         };
 278                 };
 279
 280                 spi1 {
 281                         spi1_clk: spi1-clk {
 282                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 283                         };
 284                         spi1_cs0: spi1-cs0 {
 285                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 286                         };
 287                         spi1_rx: spi1-rx {
 288                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 289                         };
 290                         spi1_tx: spi1-tx {
 291                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 292                         };
 293                         spi1_cs1: spi1-cs1 {
 294                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 295                         };
 296                 };
 297
 298                 uart0 {
 299                         uart0_xfer: uart0-xfer {
 300                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 301                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 302                         };
 303
 304                         uart0_cts: uart0-cts {
 305                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 306                         };
 307
 308                         uart0_rts: uart0-rts {
 309                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 310                         };
 311                 };
 312
 313                 uart1 {
 314                         uart1_xfer: uart1-xfer {
 315                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 316                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 317                         };
 318
 319                         uart1_cts: uart1-cts {
 320                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 321                         };
 322
 323                         uart1_rts: uart1-rts {
 324                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 325                         };
 326                 };
 327
 328                 uart2 {
 329                         uart2_xfer: uart2-xfer {
 330                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 331                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 332                         };
 333                         /* no rts / cts for uart2 */
 334                 };
 335
 336                 uart3 {
 337                         uart3_xfer: uart3-xfer {
 338                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 339                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 340                         };
 341
 342                         uart3_cts: uart3-cts {
 343                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 344                         };
 345
 346                         uart3_rts: uart3-rts {
 347                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 348                         };
 349                 };
 350
 351                 sd0 {
 352                         sd0_clk: sd0-clk {
 353                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 354                         };
 355
 356                         sd0_cmd: sd0-cmd {
 357                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 358                         };
 359
 360                         sd0_cd: sd0-cd {
 361                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 362                         };
 363
 364                         sd0_wp: sd0-wp {
 365                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 366                         };
 367
 368                         sd0_bus1: sd0-bus-width1 {
 369                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 370                         };
 371
 372                         sd0_bus4: sd0-bus-width4 {
 373                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 374                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 375                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 376                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 377                         };
 378                 };
 379
 380                 sd1 {
 381                         sd1_clk: sd1-clk {
 382                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 383                         };
 384
 385                         sd1_cmd: sd1-cmd {
 386                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 387                         };
 388
 389                         sd1_cd: sd1-cd {
 390                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 391                         };
 392
 393                         sd1_wp: sd1-wp {
 394                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 395                         };
 396
 397                         sd1_bus1: sd1-bus-width1 {
 398                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 399                         };
 400
 401                         sd1_bus4: sd1-bus-width4 {
 402                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 403                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 404                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 405                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 406                         };
 407                 };
 408         };
 409 };
 410
 411 &i2c0 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&i2c0_xfer>;
 414 };
 415
 416 &i2c1 {
 417         pinctrl-names = "default";
 418         pinctrl-0 = <&i2c1_xfer>;
 419 };
 420
 421 &i2c2 {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&i2c2_xfer>;
 424 };
 425
 426 &i2c3 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&i2c3_xfer>;
 429 };
 430
 431 &i2c4 {
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&i2c4_xfer>;
 434 };
 435
 436 &mmc0 {
 437         pinctrl-names = "default";
 438         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 439 };
 440
 441 &mmc1 {
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 444 };
 445
 446 &pwm0 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pwm0_out>;
 449 };
 450
 451 &pwm1 {
 452         pinctrl-names = "default";
 453         pinctrl-0 = <&pwm1_out>;
 454 };
 455
 456 &pwm2 {
 457         pinctrl-names = "default";
 458         pinctrl-0 = <&pwm2_out>;
 459 };
 460
 461 &pwm3 {
 462         pinctrl-names = "default";
 463         pinctrl-0 = <&pwm3_out>;
 464 };
 465
 466 &spi0 {
 467         pinctrl-names = "default";
 468         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 469 };
 470
 471 &spi1 {
 472         pinctrl-names = "default";
 473         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 474 };
 475
 476 &uart0 {
 477         pinctrl-names = "default";
 478         pinctrl-0 = <&uart0_xfer>;
 479 };
 480
 481 &uart1 {
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&uart1_xfer>;
 484 };
 485
 486 &uart2 {
 487         pinctrl-names = "default";
 488         pinctrl-0 = <&uart2_xfer>;
 489 };
 490
 491 &uart3 {
 492         pinctrl-names = "default";
 493         pinctrl-0 = <&uart3_xfer>;
 494 };
 495
 496 &wdt {
 497         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 498 };