2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/pinctrl/rockchip.h>
20 #include "skeleton.dtsi"
21 #include "rk3066a-clocks.dtsi"
24 compatible = "rockchip,rk3066a";
25 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
39 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
48 compatible = "simple-bus";
51 gic: interrupt-controller@1013d000 {
52 compatible = "arm,cortex-a9-gic";
54 #interrupt-cells = <3>;
55 reg = <0x1013d000 0x1000>,
59 L2: l2-cache-controller@10138000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10138000 0x1000>;
66 local-timer@1013c600 {
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0x1013c600 0x20>;
69 interrupts = <GIC_PPI 13 0x304>;
70 clocks = <&dummy150m>;
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk_gates1 0>, <&clk_gates7 7>;
78 clock-names = "timer", "pclk";
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&clk_gates1 1>, <&clk_gates7 8>;
86 clock-names = "timer", "pclk";
90 compatible = "snps,dw-apb-timer-osc";
91 reg = <0x2000e000 0x100>;
92 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&clk_gates1 2>, <&clk_gates7 9>;
94 clock-names = "timer", "pclk";
98 compatible = "rockchip,rk3066a-pinctrl";
99 reg = <0x20008000 0x150>;
100 #address-cells = <1>;
104 gpio0: gpio0@20034000 {
105 compatible = "rockchip,gpio-bank";
106 reg = <0x20034000 0x100>;
107 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&clk_gates8 9>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
117 gpio1: gpio1@2003c000 {
118 compatible = "rockchip,gpio-bank";
119 reg = <0x2003c000 0x100>;
120 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clk_gates8 10>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
130 gpio2: gpio2@2003e000 {
131 compatible = "rockchip,gpio-bank";
132 reg = <0x2003e000 0x100>;
133 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clk_gates8 11>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
143 gpio3: gpio3@20080000 {
144 compatible = "rockchip,gpio-bank";
145 reg = <0x20080000 0x100>;
146 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clk_gates8 12>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
156 gpio4: gpio4@20084000 {
157 compatible = "rockchip,gpio-bank";
158 reg = <0x20084000 0x100>;
159 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clk_gates8 13>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
169 gpio6: gpio6@2000a000 {
170 compatible = "rockchip,gpio-bank";
171 reg = <0x2000a000 0x100>;
172 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&clk_gates8 15>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
182 pcfg_pull_default: pcfg_pull_default {
183 bias-pull-pin-default;
186 pcfg_pull_none: pcfg_pull_none {
191 uart0_xfer: uart0-xfer {
192 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
193 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
196 uart0_cts: uart0-cts {
197 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
200 uart0_rts: uart0-rts {
201 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
206 uart1_xfer: uart1-xfer {
207 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
208 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
211 uart1_cts: uart1-cts {
212 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
215 uart1_rts: uart1-rts {
216 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
221 uart2_xfer: uart2-xfer {
222 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
223 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
225 /* no rts / cts for uart2 */
229 uart3_xfer: uart3-xfer {
230 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
231 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
234 uart3_cts: uart3-cts {
235 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
238 uart3_rts: uart3-rts {
239 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
245 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
249 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
253 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
257 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
260 sd0_bus1: sd0-bus-width1 {
261 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
264 sd0_bus4: sd0-bus-width4 {
265 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
266 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
267 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
268 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
274 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
278 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
282 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
286 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
289 sd1_bus1: sd1-bus-width1 {
290 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
293 sd1_bus4: sd1-bus-width4 {
294 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
295 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
296 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
297 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
302 uart0: serial@10124000 {
303 compatible = "snps,dw-apb-uart";
304 reg = <0x10124000 0x400>;
305 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clk_gates1 8>;
312 uart1: serial@10126000 {
313 compatible = "snps,dw-apb-uart";
314 reg = <0x10126000 0x400>;
315 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&clk_gates1 10>;
322 uart2: serial@20064000 {
323 compatible = "snps,dw-apb-uart";
324 reg = <0x20064000 0x400>;
325 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clk_gates1 12>;
332 uart3: serial@20068000 {
333 compatible = "snps,dw-apb-uart";
334 reg = <0x20068000 0x400>;
335 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clk_gates1 14>;
343 compatible = "rockchip,rk2928-dw-mshc";
344 reg = <0x10214000 0x1000>;
345 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
349 clocks = <&clk_gates5 10>, <&clk_gates2 11>;
350 clock-names = "biu", "ciu";
356 compatible = "rockchip,rk2928-dw-mshc";
357 reg = <0x10218000 0x1000>;
358 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
362 clocks = <&clk_gates5 11>, <&clk_gates2 13>;
363 clock-names = "biu", "ciu";