2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dt-bindings/thermal/thermal.h>
19 #include "skeleton.dtsi"
22 compatible = "rockchip,rk3288";
24 interrupt-parent = <&gic>;
50 enable-method = "rockchip,rk3066-smp";
51 rockchip,pmu = <&pmu>;
55 compatible = "arm,cortex-a12";
57 resets = <&cru SRST_CORE0>;
73 #cooling-cells = <2>; /* min followed by max */
74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
79 compatible = "arm,cortex-a12";
81 resets = <&cru SRST_CORE1>;
85 compatible = "arm,cortex-a12";
87 resets = <&cru SRST_CORE2>;
91 compatible = "arm,cortex-a12";
93 resets = <&cru SRST_CORE3>;
98 compatible = "arm,amba-bus";
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
143 compatible = "arm,armv7-timer";
144 arm,cpu-registers-not-fw-configured;
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
152 sdmmc: dwmmc@ff0c0000 {
153 compatible = "rockchip,rk3288-dw-mshc";
154 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
155 clock-names = "biu", "ciu";
156 fifo-depth = <0x100>;
157 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
158 reg = <0xff0c0000 0x4000>;
162 sdio0: dwmmc@ff0d0000 {
163 compatible = "rockchip,rk3288-dw-mshc";
164 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
165 clock-names = "biu", "ciu";
166 fifo-depth = <0x100>;
167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
168 reg = <0xff0d0000 0x4000>;
172 sdio1: dwmmc@ff0e0000 {
173 compatible = "rockchip,rk3288-dw-mshc";
174 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
175 clock-names = "biu", "ciu";
176 fifo-depth = <0x100>;
177 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
178 reg = <0xff0e0000 0x4000>;
182 emmc: dwmmc@ff0f0000 {
183 compatible = "rockchip,rk3288-dw-mshc";
184 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
185 clock-names = "biu", "ciu";
186 fifo-depth = <0x100>;
187 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
188 reg = <0xff0f0000 0x4000>;
192 saradc: saradc@ff100000 {
193 compatible = "rockchip,saradc";
194 reg = <0xff100000 0x100>;
195 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
196 #io-channel-cells = <1>;
197 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
198 clock-names = "saradc", "apb_pclk";
203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
204 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
205 clock-names = "spiclk", "apb_pclk";
206 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
207 dma-names = "tx", "rx";
208 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
211 reg = <0xff110000 0x1000>;
212 #address-cells = <1>;
218 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
219 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
220 clock-names = "spiclk", "apb_pclk";
221 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
222 dma-names = "tx", "rx";
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
226 reg = <0xff120000 0x1000>;
227 #address-cells = <1>;
233 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
234 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
235 clock-names = "spiclk", "apb_pclk";
236 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
237 dma-names = "tx", "rx";
238 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
241 reg = <0xff130000 0x1000>;
242 #address-cells = <1>;
248 compatible = "rockchip,rk3288-i2c";
249 reg = <0xff140000 0x1000>;
250 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
251 #address-cells = <1>;
254 clocks = <&cru PCLK_I2C1>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&i2c1_xfer>;
261 compatible = "rockchip,rk3288-i2c";
262 reg = <0xff150000 0x1000>;
263 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
264 #address-cells = <1>;
267 clocks = <&cru PCLK_I2C3>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&i2c3_xfer>;
274 compatible = "rockchip,rk3288-i2c";
275 reg = <0xff160000 0x1000>;
276 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
277 #address-cells = <1>;
280 clocks = <&cru PCLK_I2C4>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&i2c4_xfer>;
287 compatible = "rockchip,rk3288-i2c";
288 reg = <0xff170000 0x1000>;
289 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
290 #address-cells = <1>;
293 clocks = <&cru PCLK_I2C5>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&i2c5_xfer>;
299 uart0: serial@ff180000 {
300 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
301 reg = <0xff180000 0x100>;
302 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
306 clock-names = "baudclk", "apb_pclk";
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart0_xfer>;
312 uart1: serial@ff190000 {
313 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
314 reg = <0xff190000 0x100>;
315 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
319 clock-names = "baudclk", "apb_pclk";
320 pinctrl-names = "default";
321 pinctrl-0 = <&uart1_xfer>;
325 uart2: serial@ff690000 {
326 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
327 reg = <0xff690000 0x100>;
328 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
332 clock-names = "baudclk", "apb_pclk";
333 pinctrl-names = "default";
334 pinctrl-0 = <&uart2_xfer>;
338 uart3: serial@ff1b0000 {
339 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
340 reg = <0xff1b0000 0x100>;
341 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
345 clock-names = "baudclk", "apb_pclk";
346 pinctrl-names = "default";
347 pinctrl-0 = <&uart3_xfer>;
351 uart4: serial@ff1c0000 {
352 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
353 reg = <0xff1c0000 0x100>;
354 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
358 clock-names = "baudclk", "apb_pclk";
359 pinctrl-names = "default";
360 pinctrl-0 = <&uart4_xfer>;
365 #include "rk3288-thermal.dtsi"
368 tsadc: tsadc@ff280000 {
369 compatible = "rockchip,rk3288-tsadc";
370 reg = <0xff280000 0x100>;
371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
373 clock-names = "tsadc", "apb_pclk";
374 resets = <&cru SRST_TSADC>;
375 reset-names = "tsadc-apb";
376 pinctrl-names = "default";
377 pinctrl-0 = <&otp_out>;
378 #thermal-sensor-cells = <1>;
379 rockchip,hw-tshut-temp = <95000>;
383 gmac: ethernet@ff290000 {
384 compatible = "rockchip,rk3288-gmac";
385 reg = <0xff290000 0x10000>;
386 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "macirq";
388 rockchip,grf = <&grf>;
389 clocks = <&cru SCLK_MAC>,
390 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
391 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
392 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
393 clock-names = "stmmaceth",
394 "mac_clk_rx", "mac_clk_tx",
395 "clk_mac_ref", "clk_mac_refout",
396 "aclk_mac", "pclk_mac";
399 usb_host0_ehci: usb@ff500000 {
400 compatible = "generic-ehci";
401 reg = <0xff500000 0x100>;
402 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru HCLK_USBHOST0>;
404 clock-names = "usbhost";
408 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
410 usb_host1: usb@ff540000 {
411 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
413 reg = <0xff540000 0x40000>;
414 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&cru HCLK_USBHOST1>;
420 usb_otg: usb@ff580000 {
421 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
423 reg = <0xff580000 0x40000>;
424 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru HCLK_OTG0>;
430 usb_hsic: usb@ff5c0000 {
431 compatible = "generic-ehci";
432 reg = <0xff5c0000 0x100>;
433 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&cru HCLK_HSIC>;
435 clock-names = "usbhost";
440 compatible = "rockchip,rk3288-i2c";
441 reg = <0xff650000 0x1000>;
442 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
446 clocks = <&cru PCLK_I2C0>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c0_xfer>;
453 compatible = "rockchip,rk3288-i2c";
454 reg = <0xff660000 0x1000>;
455 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
459 clocks = <&cru PCLK_I2C2>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c2_xfer>;
466 compatible = "rockchip,rk3288-pwm";
467 reg = <0xff680000 0x10>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pwm0_pin>;
471 clocks = <&cru PCLK_PWM>;
477 compatible = "rockchip,rk3288-pwm";
478 reg = <0xff680010 0x10>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pwm1_pin>;
482 clocks = <&cru PCLK_PWM>;
488 compatible = "rockchip,rk3288-pwm";
489 reg = <0xff680020 0x10>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pwm2_pin>;
493 clocks = <&cru PCLK_PWM>;
499 compatible = "rockchip,rk3288-pwm";
500 reg = <0xff680030 0x10>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pwm3_pin>;
504 clocks = <&cru PCLK_PWM>;
509 bus_intmem@ff700000 {
510 compatible = "mmio-sram";
511 reg = <0xff700000 0x18000>;
512 #address-cells = <1>;
514 ranges = <0 0xff700000 0x18000>;
516 compatible = "rockchip,rk3066-smp-sram";
521 pmu: power-management@ff730000 {
522 compatible = "rockchip,rk3288-pmu", "syscon";
523 reg = <0xff730000 0x100>;
526 sgrf: syscon@ff740000 {
527 compatible = "rockchip,rk3288-sgrf", "syscon";
528 reg = <0xff740000 0x1000>;
531 cru: clock-controller@ff760000 {
532 compatible = "rockchip,rk3288-cru";
533 reg = <0xff760000 0x1000>;
534 rockchip,grf = <&grf>;
537 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
538 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
539 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
540 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
542 assigned-clock-rates = <594000000>, <400000000>,
543 <500000000>, <300000000>,
544 <150000000>, <75000000>,
545 <300000000>, <150000000>,
549 grf: syscon@ff770000 {
550 compatible = "rockchip,rk3288-grf", "syscon";
551 reg = <0xff770000 0x1000>;
554 wdt: watchdog@ff800000 {
555 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
556 reg = <0xff800000 0x100>;
557 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
562 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
563 reg = <0xff890000 0x10000>;
564 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
565 #address-cells = <1>;
567 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
568 dma-names = "tx", "rx";
569 clock-names = "i2s_hclk", "i2s_clk";
570 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2s0_bus>;
576 vopb_mmu: iommu@ff930300 {
577 compatible = "rockchip,iommu";
578 reg = <0xff930300 0x100>;
579 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
580 interrupt-names = "vopb_mmu";
585 vopl_mmu: iommu@ff940300 {
586 compatible = "rockchip,iommu";
587 reg = <0xff940300 0x100>;
588 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-names = "vopl_mmu";
594 gic: interrupt-controller@ffc01000 {
595 compatible = "arm,gic-400";
596 interrupt-controller;
597 #interrupt-cells = <3>;
598 #address-cells = <0>;
600 reg = <0xffc01000 0x1000>,
604 interrupts = <GIC_PPI 9 0xf04>;
608 compatible = "rockchip,rk3288-pinctrl";
609 rockchip,grf = <&grf>;
610 rockchip,pmu = <&pmu>;
611 #address-cells = <1>;
615 gpio0: gpio0@ff750000 {
616 compatible = "rockchip,gpio-bank";
617 reg = <0xff750000 0x100>;
618 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru PCLK_GPIO0>;
624 interrupt-controller;
625 #interrupt-cells = <2>;
628 gpio1: gpio1@ff780000 {
629 compatible = "rockchip,gpio-bank";
630 reg = <0xff780000 0x100>;
631 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru PCLK_GPIO1>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
641 gpio2: gpio2@ff790000 {
642 compatible = "rockchip,gpio-bank";
643 reg = <0xff790000 0x100>;
644 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru PCLK_GPIO2>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
654 gpio3: gpio3@ff7a0000 {
655 compatible = "rockchip,gpio-bank";
656 reg = <0xff7a0000 0x100>;
657 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cru PCLK_GPIO3>;
663 interrupt-controller;
664 #interrupt-cells = <2>;
667 gpio4: gpio4@ff7b0000 {
668 compatible = "rockchip,gpio-bank";
669 reg = <0xff7b0000 0x100>;
670 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cru PCLK_GPIO4>;
676 interrupt-controller;
677 #interrupt-cells = <2>;
680 gpio5: gpio5@ff7c0000 {
681 compatible = "rockchip,gpio-bank";
682 reg = <0xff7c0000 0x100>;
683 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru PCLK_GPIO5>;
689 interrupt-controller;
690 #interrupt-cells = <2>;
693 gpio6: gpio6@ff7d0000 {
694 compatible = "rockchip,gpio-bank";
695 reg = <0xff7d0000 0x100>;
696 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cru PCLK_GPIO6>;
702 interrupt-controller;
703 #interrupt-cells = <2>;
706 gpio7: gpio7@ff7e0000 {
707 compatible = "rockchip,gpio-bank";
708 reg = <0xff7e0000 0x100>;
709 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cru PCLK_GPIO7>;
715 interrupt-controller;
716 #interrupt-cells = <2>;
719 gpio8: gpio8@ff7f0000 {
720 compatible = "rockchip,gpio-bank";
721 reg = <0xff7f0000 0x100>;
722 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cru PCLK_GPIO8>;
728 interrupt-controller;
729 #interrupt-cells = <2>;
732 pcfg_pull_up: pcfg-pull-up {
736 pcfg_pull_down: pcfg-pull-down {
740 pcfg_pull_none: pcfg-pull-none {
744 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
746 drive-strength = <12>;
750 i2c0_xfer: i2c0-xfer {
751 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
752 <0 16 RK_FUNC_1 &pcfg_pull_none>;
757 i2c1_xfer: i2c1-xfer {
758 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
759 <8 5 RK_FUNC_1 &pcfg_pull_none>;
764 i2c2_xfer: i2c2-xfer {
765 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
766 <6 10 RK_FUNC_1 &pcfg_pull_none>;
771 i2c3_xfer: i2c3-xfer {
772 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
773 <2 17 RK_FUNC_1 &pcfg_pull_none>;
778 i2c4_xfer: i2c4-xfer {
779 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
780 <7 18 RK_FUNC_1 &pcfg_pull_none>;
785 i2c5_xfer: i2c5-xfer {
786 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
787 <7 20 RK_FUNC_1 &pcfg_pull_none>;
793 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
794 <6 1 RK_FUNC_1 &pcfg_pull_none>,
795 <6 2 RK_FUNC_1 &pcfg_pull_none>,
796 <6 3 RK_FUNC_1 &pcfg_pull_none>,
797 <6 4 RK_FUNC_1 &pcfg_pull_none>,
798 <6 8 RK_FUNC_1 &pcfg_pull_none>;
803 sdmmc_clk: sdmmc-clk {
804 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
807 sdmmc_cmd: sdmmc-cmd {
808 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
812 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
815 sdmmc_bus1: sdmmc-bus1 {
816 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
819 sdmmc_bus4: sdmmc-bus4 {
820 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
821 <6 17 RK_FUNC_1 &pcfg_pull_up>,
822 <6 18 RK_FUNC_1 &pcfg_pull_up>,
823 <6 19 RK_FUNC_1 &pcfg_pull_up>;
828 sdio0_bus1: sdio0-bus1 {
829 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
832 sdio0_bus4: sdio0-bus4 {
833 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
834 <4 21 RK_FUNC_1 &pcfg_pull_up>,
835 <4 22 RK_FUNC_1 &pcfg_pull_up>,
836 <4 23 RK_FUNC_1 &pcfg_pull_up>;
839 sdio0_cmd: sdio0-cmd {
840 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
843 sdio0_clk: sdio0-clk {
844 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
848 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
852 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
855 sdio0_pwr: sdio0-pwr {
856 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
859 sdio0_bkpwr: sdio0-bkpwr {
860 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
863 sdio0_int: sdio0-int {
864 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
869 sdio1_bus1: sdio1-bus1 {
870 rockchip,pins = <3 24 4 &pcfg_pull_up>;
873 sdio1_bus4: sdio1-bus4 {
874 rockchip,pins = <3 24 4 &pcfg_pull_up>,
875 <3 25 4 &pcfg_pull_up>,
876 <3 26 4 &pcfg_pull_up>,
877 <3 27 4 &pcfg_pull_up>;
881 rockchip,pins = <3 28 4 &pcfg_pull_up>;
885 rockchip,pins = <3 29 4 &pcfg_pull_up>;
888 sdio1_bkpwr: sdio1-bkpwr {
889 rockchip,pins = <3 30 4 &pcfg_pull_up>;
892 sdio1_int: sdio1-int {
893 rockchip,pins = <3 31 4 &pcfg_pull_up>;
896 sdio1_cmd: sdio1-cmd {
897 rockchip,pins = <4 6 4 &pcfg_pull_up>;
900 sdio1_clk: sdio1-clk {
901 rockchip,pins = <4 7 4 &pcfg_pull_none>;
904 sdio1_pwr: sdio1-pwr {
905 rockchip,pins = <4 9 4 &pcfg_pull_up>;
911 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
915 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
919 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
922 emmc_bus1: emmc-bus1 {
923 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
926 emmc_bus4: emmc-bus4 {
927 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
928 <3 1 RK_FUNC_2 &pcfg_pull_up>,
929 <3 2 RK_FUNC_2 &pcfg_pull_up>,
930 <3 3 RK_FUNC_2 &pcfg_pull_up>;
933 emmc_bus8: emmc-bus8 {
934 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
935 <3 1 RK_FUNC_2 &pcfg_pull_up>,
936 <3 2 RK_FUNC_2 &pcfg_pull_up>,
937 <3 3 RK_FUNC_2 &pcfg_pull_up>,
938 <3 4 RK_FUNC_2 &pcfg_pull_up>,
939 <3 5 RK_FUNC_2 &pcfg_pull_up>,
940 <3 6 RK_FUNC_2 &pcfg_pull_up>,
941 <3 7 RK_FUNC_2 &pcfg_pull_up>;
947 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
950 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
953 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
956 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
959 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
964 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
967 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
970 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
973 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
979 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
982 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
985 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
988 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
991 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
996 uart0_xfer: uart0-xfer {
997 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
998 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1001 uart0_cts: uart0-cts {
1002 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1005 uart0_rts: uart0-rts {
1006 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1011 uart1_xfer: uart1-xfer {
1012 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1013 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1016 uart1_cts: uart1-cts {
1017 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1020 uart1_rts: uart1-rts {
1021 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1026 uart2_xfer: uart2-xfer {
1027 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1028 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1030 /* no rts / cts for uart2 */
1034 uart3_xfer: uart3-xfer {
1035 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1036 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1039 uart3_cts: uart3-cts {
1040 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1043 uart3_rts: uart3-rts {
1044 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1049 uart4_xfer: uart4-xfer {
1050 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1051 <5 13 3 &pcfg_pull_none>;
1054 uart4_cts: uart4-cts {
1055 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1058 uart4_rts: uart4-rts {
1059 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1065 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1070 pwm0_pin: pwm0-pin {
1071 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1076 pwm1_pin: pwm1-pin {
1077 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1082 pwm2_pin: pwm2-pin {
1083 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1088 pwm3_pin: pwm3-pin {
1089 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1094 rgmii_pins: rgmii-pins {
1095 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1096 <3 31 3 &pcfg_pull_none>,
1097 <3 26 3 &pcfg_pull_none>,
1098 <3 27 3 &pcfg_pull_none>,
1099 <3 28 3 &pcfg_pull_none_12ma>,
1100 <3 29 3 &pcfg_pull_none_12ma>,
1101 <3 24 3 &pcfg_pull_none_12ma>,
1102 <3 25 3 &pcfg_pull_none_12ma>,
1103 <4 0 3 &pcfg_pull_none>,
1104 <4 5 3 &pcfg_pull_none>,
1105 <4 6 3 &pcfg_pull_none>,
1106 <4 9 3 &pcfg_pull_none_12ma>,
1107 <4 4 3 &pcfg_pull_none_12ma>,
1108 <4 1 3 &pcfg_pull_none>,
1109 <4 3 3 &pcfg_pull_none>;
1112 rmii_pins: rmii-pins {
1113 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1114 <3 31 3 &pcfg_pull_none>,
1115 <3 28 3 &pcfg_pull_none>,
1116 <3 29 3 &pcfg_pull_none>,
1117 <4 0 3 &pcfg_pull_none>,
1118 <4 5 3 &pcfg_pull_none>,
1119 <4 4 3 &pcfg_pull_none>,
1120 <4 1 3 &pcfg_pull_none>,
1121 <4 2 3 &pcfg_pull_none>,
1122 <4 3 3 &pcfg_pull_none>;