arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include "skeleton.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3288";
  23
  24         interrupt-parent = <&gic>;
  25
  26         aliases {
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mshc0 = &emmc;
  34                 mshc1 = &sdmmc;
  35                 mshc2 = &sdio0;
  36                 mshc3 = &sdio1;
  37                 serial0 = &uart0;
  38                 serial1 = &uart1;
  39                 serial2 = &uart2;
  40                 serial3 = &uart3;
  41                 serial4 = &uart4;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 rockchip,pmu = <&pmu>;
  51
  52                 cpu0: cpu@500 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a12";
  55                         reg = <0x500>;
  56                         resets = <&cru SRST_CORE0>;
  57                         operating-points = <
  58                                 /* KHz    uV */
  59                                 1608000 1350000
  60                                 1512000 1300000
  61                                 1416000 1200000
  62                                 1200000 1100000
  63                                 1008000 1050000
  64                                  816000 1000000
  65                                  696000  950000
  66                                  600000  900000
  67                                  408000  900000
  68                                  312000  900000
  69                                  216000  900000
  70                                  126000  900000
  71                         >;
  72                         #cooling-cells = <2>; /* min followed by max */
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76                 cpu@501 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a12";
  79                         reg = <0x501>;
  80                         resets = <&cru SRST_CORE1>;
  81                 };
  82                 cpu@502 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a12";
  85                         reg = <0x502>;
  86                         resets = <&cru SRST_CORE2>;
  87                 };
  88                 cpu@503 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a12";
  91                         reg = <0x503>;
  92                         resets = <&cru SRST_CORE3>;
  93                 };
  94         };
  95
  96         amba {
  97                 compatible = "arm,amba-bus";
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 ranges;
 101
 102                 dmac_peri: dma-controller@ff250000 {
 103                         compatible = "arm,pl330", "arm,primecell";
 104                         reg = <0xff250000 0x4000>;
 105                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 107                         #dma-cells = <1>;
 108                         clocks = <&cru ACLK_DMAC2>;
 109                         clock-names = "apb_pclk";
 110                 };
 111
 112                 dmac_bus_ns: dma-controller@ff600000 {
 113                         compatible = "arm,pl330", "arm,primecell";
 114                         reg = <0xff600000 0x4000>;
 115                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 116                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 117                         #dma-cells = <1>;
 118                         clocks = <&cru ACLK_DMAC1>;
 119                         clock-names = "apb_pclk";
 120                         status = "disabled";
 121                 };
 122
 123                 dmac_bus_s: dma-controller@ffb20000 {
 124                         compatible = "arm,pl330", "arm,primecell";
 125                         reg = <0xffb20000 0x4000>;
 126                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 127                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 128                         #dma-cells = <1>;
 129                         clocks = <&cru ACLK_DMAC1>;
 130                         clock-names = "apb_pclk";
 131                 };
 132         };
 133
 134         xin24m: oscillator {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <24000000>;
 137                 clock-output-names = "xin24m";
 138                 #clock-cells = <0>;
 139         };
 140
 141         timer {
 142                 compatible = "arm,armv7-timer";
 143                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 144                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 145                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 147                 clock-frequency = <24000000>;
 148         };
 149
 150         sdmmc: dwmmc@ff0c0000 {
 151                 compatible = "rockchip,rk3288-dw-mshc";
 152                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 153                 clock-names = "biu", "ciu";
 154                 fifo-depth = <0x100>;
 155                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 156                 reg = <0xff0c0000 0x4000>;
 157                 status = "disabled";
 158         };
 159
 160         sdio0: dwmmc@ff0d0000 {
 161                 compatible = "rockchip,rk3288-dw-mshc";
 162                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 163                 clock-names = "biu", "ciu";
 164                 fifo-depth = <0x100>;
 165                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 166                 reg = <0xff0d0000 0x4000>;
 167                 status = "disabled";
 168         };
 169
 170         sdio1: dwmmc@ff0e0000 {
 171                 compatible = "rockchip,rk3288-dw-mshc";
 172                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 173                 clock-names = "biu", "ciu";
 174                 fifo-depth = <0x100>;
 175                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 176                 reg = <0xff0e0000 0x4000>;
 177                 status = "disabled";
 178         };
 179
 180         emmc: dwmmc@ff0f0000 {
 181                 compatible = "rockchip,rk3288-dw-mshc";
 182                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 183                 clock-names = "biu", "ciu";
 184                 fifo-depth = <0x100>;
 185                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 186                 reg = <0xff0f0000 0x4000>;
 187                 status = "disabled";
 188         };
 189
 190         saradc: saradc@ff100000 {
 191                 compatible = "rockchip,saradc";
 192                 reg = <0xff100000 0x100>;
 193                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 194                 #io-channel-cells = <1>;
 195                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 196                 clock-names = "saradc", "apb_pclk";
 197                 status = "disabled";
 198         };
 199
 200         spi0: spi@ff110000 {
 201                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 202                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 203                 clock-names = "spiclk", "apb_pclk";
 204                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 205                 dma-names = "tx", "rx";
 206                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 207                 pinctrl-names = "default";
 208                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 209                 reg = <0xff110000 0x1000>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         spi1: spi@ff120000 {
 216                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 217                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 218                 clock-names = "spiclk", "apb_pclk";
 219                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 220                 dma-names = "tx", "rx";
 221                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 224                 reg = <0xff120000 0x1000>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 status = "disabled";
 228         };
 229
 230         spi2: spi@ff130000 {
 231                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 232                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 233                 clock-names = "spiclk", "apb_pclk";
 234                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 235                 dma-names = "tx", "rx";
 236                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 237                 pinctrl-names = "default";
 238                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 239                 reg = <0xff130000 0x1000>;
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242                 status = "disabled";
 243         };
 244
 245         i2c1: i2c@ff140000 {
 246                 compatible = "rockchip,rk3288-i2c";
 247                 reg = <0xff140000 0x1000>;
 248                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 clock-names = "i2c";
 252                 clocks = <&cru PCLK_I2C1>;
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&i2c1_xfer>;
 255                 status = "disabled";
 256         };
 257
 258         i2c3: i2c@ff150000 {
 259                 compatible = "rockchip,rk3288-i2c";
 260                 reg = <0xff150000 0x1000>;
 261                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 clock-names = "i2c";
 265                 clocks = <&cru PCLK_I2C3>;
 266                 pinctrl-names = "default";
 267                 pinctrl-0 = <&i2c3_xfer>;
 268                 status = "disabled";
 269         };
 270
 271         i2c4: i2c@ff160000 {
 272                 compatible = "rockchip,rk3288-i2c";
 273                 reg = <0xff160000 0x1000>;
 274                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clock-names = "i2c";
 278                 clocks = <&cru PCLK_I2C4>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c4_xfer>;
 281                 status = "disabled";
 282         };
 283
 284         i2c5: i2c@ff170000 {
 285                 compatible = "rockchip,rk3288-i2c";
 286                 reg = <0xff170000 0x1000>;
 287                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 clock-names = "i2c";
 291                 clocks = <&cru PCLK_I2C5>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&i2c5_xfer>;
 294                 status = "disabled";
 295         };
 296
 297         uart0: serial@ff180000 {
 298                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 299                 reg = <0xff180000 0x100>;
 300                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 301                 reg-shift = <2>;
 302                 reg-io-width = <4>;
 303                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 304                 clock-names = "baudclk", "apb_pclk";
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&uart0_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         uart1: serial@ff190000 {
 311                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 312                 reg = <0xff190000 0x100>;
 313                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 314                 reg-shift = <2>;
 315                 reg-io-width = <4>;
 316                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 317                 clock-names = "baudclk", "apb_pclk";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart1_xfer>;
 320                 status = "disabled";
 321         };
 322
 323         uart2: serial@ff690000 {
 324                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 325                 reg = <0xff690000 0x100>;
 326                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 327                 reg-shift = <2>;
 328                 reg-io-width = <4>;
 329                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 330                 clock-names = "baudclk", "apb_pclk";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&uart2_xfer>;
 333                 status = "disabled";
 334         };
 335
 336         uart3: serial@ff1b0000 {
 337                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 338                 reg = <0xff1b0000 0x100>;
 339                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 340                 reg-shift = <2>;
 341                 reg-io-width = <4>;
 342                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 343                 clock-names = "baudclk", "apb_pclk";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&uart3_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         uart4: serial@ff1c0000 {
 350                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 351                 reg = <0xff1c0000 0x100>;
 352                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 353                 reg-shift = <2>;
 354                 reg-io-width = <4>;
 355                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 356                 clock-names = "baudclk", "apb_pclk";
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&uart4_xfer>;
 359                 status = "disabled";
 360         };
 361
 362         thermal-zones {
 363                 #include "rk3288-thermal.dtsi"
 364         };
 365
 366         tsadc: tsadc@ff280000 {
 367                 compatible = "rockchip,rk3288-tsadc";
 368                 reg = <0xff280000 0x100>;
 369                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 370                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 371                 clock-names = "tsadc", "apb_pclk";
 372                 resets = <&cru SRST_TSADC>;
 373                 reset-names = "tsadc-apb";
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&otp_out>;
 376                 #thermal-sensor-cells = <1>;
 377                 rockchip,hw-tshut-temp = <95000>;
 378                 status = "disabled";
 379         };
 380
 381         usb_host0_ehci: usb@ff500000 {
 382                 compatible = "generic-ehci";
 383                 reg = <0xff500000 0x100>;
 384                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 385                 clocks = <&cru HCLK_USBHOST0>;
 386                 clock-names = "usbhost";
 387                 status = "disabled";
 388         };
 389
 390         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 391
 392         usb_host1: usb@ff540000 {
 393                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 394                                 "snps,dwc2";
 395                 reg = <0xff540000 0x40000>;
 396                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&cru HCLK_USBHOST1>;
 398                 clock-names = "otg";
 399                 status = "disabled";
 400         };
 401
 402         usb_otg: usb@ff580000 {
 403                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 404                                 "snps,dwc2";
 405                 reg = <0xff580000 0x40000>;
 406                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&cru HCLK_OTG0>;
 408                 clock-names = "otg";
 409                 status = "disabled";
 410         };
 411
 412         usb_hsic: usb@ff5c0000 {
 413                 compatible = "generic-ehci";
 414                 reg = <0xff5c0000 0x100>;
 415                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&cru HCLK_HSIC>;
 417                 clock-names = "usbhost";
 418                 status = "disabled";
 419         };
 420
 421         i2c0: i2c@ff650000 {
 422                 compatible = "rockchip,rk3288-i2c";
 423                 reg = <0xff650000 0x1000>;
 424                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 clock-names = "i2c";
 428                 clocks = <&cru PCLK_I2C0>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&i2c0_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         i2c2: i2c@ff660000 {
 435                 compatible = "rockchip,rk3288-i2c";
 436                 reg = <0xff660000 0x1000>;
 437                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 clock-names = "i2c";
 441                 clocks = <&cru PCLK_I2C2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&i2c2_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         pwm0: pwm@ff680000 {
 448                 compatible = "rockchip,rk3288-pwm";
 449                 reg = <0xff680000 0x10>;
 450                 #pwm-cells = <3>;
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&pwm0_pin>;
 453                 clocks = <&cru PCLK_PWM>;
 454                 clock-names = "pwm";
 455                 status = "disabled";
 456         };
 457
 458         pwm1: pwm@ff680010 {
 459                 compatible = "rockchip,rk3288-pwm";
 460                 reg = <0xff680010 0x10>;
 461                 #pwm-cells = <3>;
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&pwm1_pin>;
 464                 clocks = <&cru PCLK_PWM>;
 465                 clock-names = "pwm";
 466                 status = "disabled";
 467         };
 468
 469         pwm2: pwm@ff680020 {
 470                 compatible = "rockchip,rk3288-pwm";
 471                 reg = <0xff680020 0x10>;
 472                 #pwm-cells = <3>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&pwm2_pin>;
 475                 clocks = <&cru PCLK_PWM>;
 476                 clock-names = "pwm";
 477                 status = "disabled";
 478         };
 479
 480         pwm3: pwm@ff680030 {
 481                 compatible = "rockchip,rk3288-pwm";
 482                 reg = <0xff680030 0x10>;
 483                 #pwm-cells = <2>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&pwm3_pin>;
 486                 clocks = <&cru PCLK_PWM>;
 487                 clock-names = "pwm";
 488                 status = "disabled";
 489         };
 490
 491         bus_intmem@ff700000 {
 492                 compatible = "mmio-sram";
 493                 reg = <0xff700000 0x18000>;
 494                 #address-cells = <1>;
 495                 #size-cells = <1>;
 496                 ranges = <0 0xff700000 0x18000>;
 497                 smp-sram@0 {
 498                         compatible = "rockchip,rk3066-smp-sram";
 499                         reg = <0x00 0x10>;
 500                 };
 501         };
 502
 503         pmu: power-management@ff730000 {
 504                 compatible = "rockchip,rk3288-pmu", "syscon";
 505                 reg = <0xff730000 0x100>;
 506         };
 507
 508         sgrf: syscon@ff740000 {
 509                 compatible = "rockchip,rk3288-sgrf", "syscon";
 510                 reg = <0xff740000 0x1000>;
 511         };
 512
 513         cru: clock-controller@ff760000 {
 514                 compatible = "rockchip,rk3288-cru";
 515                 reg = <0xff760000 0x1000>;
 516                 rockchip,grf = <&grf>;
 517                 #clock-cells = <1>;
 518                 #reset-cells = <1>;
 519                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 520                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 521                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 522                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 523                                   <&cru PCLK_PERI>;
 524                 assigned-clock-rates = <594000000>, <400000000>,
 525                                        <500000000>, <300000000>,
 526                                        <150000000>, <75000000>,
 527                                        <300000000>, <150000000>,
 528                                        <75000000>;
 529         };
 530
 531         grf: syscon@ff770000 {
 532                 compatible = "rockchip,rk3288-grf", "syscon";
 533                 reg = <0xff770000 0x1000>;
 534         };
 535
 536         wdt: watchdog@ff800000 {
 537                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 538                 reg = <0xff800000 0x100>;
 539                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 540                 status = "disabled";
 541         };
 542
 543         i2s: i2s@ff890000 {
 544                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 545                 reg = <0xff890000 0x10000>;
 546                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 550                 dma-names = "tx", "rx";
 551                 clock-names = "i2s_hclk", "i2s_clk";
 552                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&i2s0_bus>;
 555                 status = "disabled";
 556         };
 557
 558         vopb_mmu: iommu@ff930300 {
 559                 compatible = "rockchip,iommu";
 560                 reg = <0xff930300 0x100>;
 561                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 562                 interrupt-names = "vopb_mmu";
 563                 #iommu-cells = <0>;
 564                 status = "disabled";
 565         };
 566
 567         vopl_mmu: iommu@ff940300 {
 568                 compatible = "rockchip,iommu";
 569                 reg = <0xff940300 0x100>;
 570                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 571                 interrupt-names = "vopl_mmu";
 572                 #iommu-cells = <0>;
 573                 status = "disabled";
 574         };
 575
 576         gic: interrupt-controller@ffc01000 {
 577                 compatible = "arm,gic-400";
 578                 interrupt-controller;
 579                 #interrupt-cells = <3>;
 580                 #address-cells = <0>;
 581
 582                 reg = <0xffc01000 0x1000>,
 583                       <0xffc02000 0x1000>,
 584                       <0xffc04000 0x2000>,
 585                       <0xffc06000 0x2000>;
 586                 interrupts = <GIC_PPI 9 0xf04>;
 587         };
 588
 589         pinctrl: pinctrl {
 590                 compatible = "rockchip,rk3288-pinctrl";
 591                 rockchip,grf = <&grf>;
 592                 rockchip,pmu = <&pmu>;
 593                 #address-cells = <1>;
 594                 #size-cells = <1>;
 595                 ranges;
 596
 597                 gpio0: gpio0@ff750000 {
 598                         compatible = "rockchip,gpio-bank";
 599                         reg =   <0xff750000 0x100>;
 600                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&cru PCLK_GPIO0>;
 602
 603                         gpio-controller;
 604                         #gpio-cells = <2>;
 605
 606                         interrupt-controller;
 607                         #interrupt-cells = <2>;
 608                 };
 609
 610                 gpio1: gpio1@ff780000 {
 611                         compatible = "rockchip,gpio-bank";
 612                         reg = <0xff780000 0x100>;
 613                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 614                         clocks = <&cru PCLK_GPIO1>;
 615
 616                         gpio-controller;
 617                         #gpio-cells = <2>;
 618
 619                         interrupt-controller;
 620                         #interrupt-cells = <2>;
 621                 };
 622
 623                 gpio2: gpio2@ff790000 {
 624                         compatible = "rockchip,gpio-bank";
 625                         reg = <0xff790000 0x100>;
 626                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&cru PCLK_GPIO2>;
 628
 629                         gpio-controller;
 630                         #gpio-cells = <2>;
 631
 632                         interrupt-controller;
 633                         #interrupt-cells = <2>;
 634                 };
 635
 636                 gpio3: gpio3@ff7a0000 {
 637                         compatible = "rockchip,gpio-bank";
 638                         reg = <0xff7a0000 0x100>;
 639                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 640                         clocks = <&cru PCLK_GPIO3>;
 641
 642                         gpio-controller;
 643                         #gpio-cells = <2>;
 644
 645                         interrupt-controller;
 646                         #interrupt-cells = <2>;
 647                 };
 648
 649                 gpio4: gpio4@ff7b0000 {
 650                         compatible = "rockchip,gpio-bank";
 651                         reg = <0xff7b0000 0x100>;
 652                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&cru PCLK_GPIO4>;
 654
 655                         gpio-controller;
 656                         #gpio-cells = <2>;
 657
 658                         interrupt-controller;
 659                         #interrupt-cells = <2>;
 660                 };
 661
 662                 gpio5: gpio5@ff7c0000 {
 663                         compatible = "rockchip,gpio-bank";
 664                         reg = <0xff7c0000 0x100>;
 665                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 666                         clocks = <&cru PCLK_GPIO5>;
 667
 668                         gpio-controller;
 669                         #gpio-cells = <2>;
 670
 671                         interrupt-controller;
 672                         #interrupt-cells = <2>;
 673                 };
 674
 675                 gpio6: gpio6@ff7d0000 {
 676                         compatible = "rockchip,gpio-bank";
 677                         reg = <0xff7d0000 0x100>;
 678                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 679                         clocks = <&cru PCLK_GPIO6>;
 680
 681                         gpio-controller;
 682                         #gpio-cells = <2>;
 683
 684                         interrupt-controller;
 685                         #interrupt-cells = <2>;
 686                 };
 687
 688                 gpio7: gpio7@ff7e0000 {
 689                         compatible = "rockchip,gpio-bank";
 690                         reg = <0xff7e0000 0x100>;
 691                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&cru PCLK_GPIO7>;
 693
 694                         gpio-controller;
 695                         #gpio-cells = <2>;
 696
 697                         interrupt-controller;
 698                         #interrupt-cells = <2>;
 699                 };
 700
 701                 gpio8: gpio8@ff7f0000 {
 702                         compatible = "rockchip,gpio-bank";
 703                         reg = <0xff7f0000 0x100>;
 704                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 705                         clocks = <&cru PCLK_GPIO8>;
 706
 707                         gpio-controller;
 708                         #gpio-cells = <2>;
 709
 710                         interrupt-controller;
 711                         #interrupt-cells = <2>;
 712                 };
 713
 714                 pcfg_pull_up: pcfg-pull-up {
 715                         bias-pull-up;
 716                 };
 717
 718                 pcfg_pull_down: pcfg-pull-down {
 719                         bias-pull-down;
 720                 };
 721
 722                 pcfg_pull_none: pcfg-pull-none {
 723                         bias-disable;
 724                 };
 725
 726                 i2c0 {
 727                         i2c0_xfer: i2c0-xfer {
 728                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 729                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 730                         };
 731                 };
 732
 733                 i2c1 {
 734                         i2c1_xfer: i2c1-xfer {
 735                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 736                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 737                         };
 738                 };
 739
 740                 i2c2 {
 741                         i2c2_xfer: i2c2-xfer {
 742                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 743                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 744                         };
 745                 };
 746
 747                 i2c3 {
 748                         i2c3_xfer: i2c3-xfer {
 749                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 750                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 751                         };
 752                 };
 753
 754                 i2c4 {
 755                         i2c4_xfer: i2c4-xfer {
 756                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 757                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 758                         };
 759                 };
 760
 761                 i2c5 {
 762                         i2c5_xfer: i2c5-xfer {
 763                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 764                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 765                         };
 766                 };
 767
 768                 i2s0 {
 769                         i2s0_bus: i2s0-bus {
 770                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 771                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 772                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 773                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 774                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 775                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 776                         };
 777                 };
 778
 779                 sdmmc {
 780                         sdmmc_clk: sdmmc-clk {
 781                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 782                         };
 783
 784                         sdmmc_cmd: sdmmc-cmd {
 785                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 786                         };
 787
 788                         sdmmc_cd: sdmcc-cd {
 789                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 790                         };
 791
 792                         sdmmc_bus1: sdmmc-bus1 {
 793                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 794                         };
 795
 796                         sdmmc_bus4: sdmmc-bus4 {
 797                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 798                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 799                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 800                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 801                         };
 802                 };
 803
 804                 sdio0 {
 805                         sdio0_bus1: sdio0-bus1 {
 806                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 807                         };
 808
 809                         sdio0_bus4: sdio0-bus4 {
 810                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 811                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 812                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 813                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 814                         };
 815
 816                         sdio0_cmd: sdio0-cmd {
 817                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 818                         };
 819
 820                         sdio0_clk: sdio0-clk {
 821                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 822                         };
 823
 824                         sdio0_cd: sdio0-cd {
 825                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 826                         };
 827
 828                         sdio0_wp: sdio0-wp {
 829                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
 830                         };
 831
 832                         sdio0_pwr: sdio0-pwr {
 833                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
 834                         };
 835
 836                         sdio0_bkpwr: sdio0-bkpwr {
 837                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
 838                         };
 839
 840                         sdio0_int: sdio0-int {
 841                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
 842                         };
 843                 };
 844
 845                 sdio1 {
 846                         sdio1_bus1: sdio1-bus1 {
 847                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
 848                         };
 849
 850                         sdio1_bus4: sdio1-bus4 {
 851                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
 852                                                 <3 25 4 &pcfg_pull_up>,
 853                                                 <3 26 4 &pcfg_pull_up>,
 854                                                 <3 27 4 &pcfg_pull_up>;
 855                         };
 856
 857                         sdio1_cd: sdio1-cd {
 858                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
 859                         };
 860
 861                         sdio1_wp: sdio1-wp {
 862                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
 863                         };
 864
 865                         sdio1_bkpwr: sdio1-bkpwr {
 866                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
 867                         };
 868
 869                         sdio1_int: sdio1-int {
 870                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
 871                         };
 872
 873                         sdio1_cmd: sdio1-cmd {
 874                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
 875                         };
 876
 877                         sdio1_clk: sdio1-clk {
 878                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
 879                         };
 880
 881                         sdio1_pwr: sdio1-pwr {
 882                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
 883                         };
 884                 };
 885
 886                 emmc {
 887                         emmc_clk: emmc-clk {
 888                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
 889                         };
 890
 891                         emmc_cmd: emmc-cmd {
 892                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
 893                         };
 894
 895                         emmc_pwr: emmc-pwr {
 896                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
 897                         };
 898
 899                         emmc_bus1: emmc-bus1 {
 900                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
 901                         };
 902
 903                         emmc_bus4: emmc-bus4 {
 904                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 905                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 906                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 907                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
 908                         };
 909
 910                         emmc_bus8: emmc-bus8 {
 911                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
 912                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
 913                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
 914                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
 915                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
 916                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
 917                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
 918                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
 919                         };
 920                 };
 921
 922                 spi0 {
 923                         spi0_clk: spi0-clk {
 924                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
 925                         };
 926                         spi0_cs0: spi0-cs0 {
 927                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
 928                         };
 929                         spi0_tx: spi0-tx {
 930                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
 931                         };
 932                         spi0_rx: spi0-rx {
 933                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
 934                         };
 935                         spi0_cs1: spi0-cs1 {
 936                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
 937                         };
 938                 };
 939                 spi1 {
 940                         spi1_clk: spi1-clk {
 941                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
 942                         };
 943                         spi1_cs0: spi1-cs0 {
 944                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
 945                         };
 946                         spi1_rx: spi1-rx {
 947                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
 948                         };
 949                         spi1_tx: spi1-tx {
 950                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
 951                         };
 952                 };
 953
 954                 spi2 {
 955                         spi2_cs1: spi2-cs1 {
 956                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
 957                         };
 958                         spi2_clk: spi2-clk {
 959                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
 960                         };
 961                         spi2_cs0: spi2-cs0 {
 962                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
 963                         };
 964                         spi2_rx: spi2-rx {
 965                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
 966                         };
 967                         spi2_tx: spi2-tx {
 968                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
 969                         };
 970                 };
 971
 972                 uart0 {
 973                         uart0_xfer: uart0-xfer {
 974                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
 975                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
 976                         };
 977
 978                         uart0_cts: uart0-cts {
 979                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
 980                         };
 981
 982                         uart0_rts: uart0-rts {
 983                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
 984                         };
 985                 };
 986
 987                 uart1 {
 988                         uart1_xfer: uart1-xfer {
 989                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
 990                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992
 993                         uart1_cts: uart1-cts {
 994                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
 995                         };
 996
 997                         uart1_rts: uart1-rts {
 998                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
 999                         };
1000                 };
1001
1002                 uart2 {
1003                         uart2_xfer: uart2-xfer {
1004                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1005                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1006                         };
1007                         /* no rts / cts for uart2 */
1008                 };
1009
1010                 uart3 {
1011                         uart3_xfer: uart3-xfer {
1012                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1013                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1014                         };
1015
1016                         uart3_cts: uart3-cts {
1017                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1018                         };
1019
1020                         uart3_rts: uart3-rts {
1021                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1022                         };
1023                 };
1024
1025                 uart4 {
1026                         uart4_xfer: uart4-xfer {
1027                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1028                                                 <5 13 3 &pcfg_pull_none>;
1029                         };
1030
1031                         uart4_cts: uart4-cts {
1032                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1033                         };
1034
1035                         uart4_rts: uart4-rts {
1036                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1037                         };
1038                 };
1039
1040                 tsadc {
1041                         otp_out: otp-out {
1042                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1043                         };
1044                 };
1045
1046                 pwm0 {
1047                         pwm0_pin: pwm0-pin {
1048                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1049                         };
1050                 };
1051
1052                 pwm1 {
1053                         pwm1_pin: pwm1-pin {
1054                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1055                         };
1056                 };
1057
1058                 pwm2 {
1059                         pwm2_pin: pwm2-pin {
1060                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1061                         };
1062                 };
1063
1064                 pwm3 {
1065                         pwm3_pin: pwm3-pin {
1066                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1067                         };
1068                 };
1069         };
1070 };