arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29         };
  30
  31         xin24m: oscillator {
  32                 compatible = "fixed-clock";
  33                 clock-frequency = <24000000>;
  34                 #clock-cells = <0>;
  35                 clock-output-names = "xin24m";
  36         };
  37
  38         L2: l2-cache-controller@10138000 {
  39                 compatible = "arm,pl310-cache";
  40                 reg = <0x10138000 0x1000>;
  41                 cache-unified;
  42                 cache-level = <2>;
  43         };
  44
  45         scu@1013c000 {
  46                 compatible = "arm,cortex-a9-scu";
  47                 reg = <0x1013c000 0x100>;
  48         };
  49
  50         global_timer: global-timer@1013c200 {
  51                 compatible = "arm,cortex-a9-global-timer";
  52                 reg = <0x1013c200 0x20>;
  53                 interrupts = <GIC_PPI 11 0x304>;
  54                 clocks = <&cru CORE_PERI>;
  55         };
  56
  57         local_timer: local-timer@1013c600 {
  58                 compatible = "arm,cortex-a9-twd-timer";
  59                 reg = <0x1013c600 0x20>;
  60                 interrupts = <GIC_PPI 13 0x304>;
  61                 clocks = <&cru CORE_PERI>;
  62         };
  63
  64         gic: interrupt-controller@1013d000 {
  65                 compatible = "arm,cortex-a9-gic";
  66                 interrupt-controller;
  67                 #interrupt-cells = <3>;
  68                 reg = <0x1013d000 0x1000>,
  69                       <0x1013c100 0x0100>;
  70         };
  71
  72         uart0: serial@10124000 {
  73                 compatible = "snps,dw-apb-uart";
  74                 reg = <0x10124000 0x400>;
  75                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <1>;
  78                 clock-names = "baudclk", "apb_pclk";
  79                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  80                 status = "disabled";
  81         };
  82
  83         uart1: serial@10126000 {
  84                 compatible = "snps,dw-apb-uart";
  85                 reg = <0x10126000 0x400>;
  86                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  87                 reg-shift = <2>;
  88                 reg-io-width = <1>;
  89                 clock-names = "baudclk", "apb_pclk";
  90                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  91                 status = "disabled";
  92         };
  93
  94         mmc0: dwmmc@10214000 {
  95                 compatible = "rockchip,rk2928-dw-mshc";
  96                 reg = <0x10214000 0x1000>;
  97                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100
 101                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 102                 clock-names = "biu", "ciu";
 103
 104                 status = "disabled";
 105         };
 106
 107         mmc1: dwmmc@10218000 {
 108                 compatible = "rockchip,rk2928-dw-mshc";
 109                 reg = <0x10218000 0x1000>;
 110                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113
 114                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 115                 clock-names = "biu", "ciu";
 116
 117                 status = "disabled";
 118         };
 119
 120         pmu: pmu@20004000 {
 121                 compatible = "rockchip,rk3066-pmu", "syscon";
 122                 reg = <0x20004000 0x100>;
 123         };
 124
 125         grf: grf@20008000 {
 126                 compatible = "syscon";
 127                 reg = <0x20008000 0x200>;
 128         };
 129
 130         i2c0: i2c@2002d000 {
 131                 compatible = "rockchip,rk3066-i2c";
 132                 reg = <0x2002d000 0x1000>;
 133                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136
 137                 rockchip,grf = <&grf>;
 138                 rockchip,bus-index = <0>;
 139
 140                 clock-names = "i2c";
 141                 clocks = <&cru PCLK_I2C0>;
 142
 143                 status = "disabled";
 144         };
 145
 146         i2c1: i2c@2002f000 {
 147                 compatible = "rockchip,rk3066-i2c";
 148                 reg = <0x2002f000 0x1000>;
 149                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152
 153                 rockchip,grf = <&grf>;
 154
 155                 clocks = <&cru PCLK_I2C1>;
 156                 clock-names = "i2c";
 157
 158                 status = "disabled";
 159         };
 160
 161         pwm0: pwm@20030000 {
 162                 compatible = "rockchip,rk2928-pwm";
 163                 reg = <0x20030000 0x10>;
 164                 #pwm-cells = <2>;
 165                 clocks = <&cru PCLK_PWM01>;
 166                 status = "disabled";
 167         };
 168
 169         pwm1: pwm@20030010 {
 170                 compatible = "rockchip,rk2928-pwm";
 171                 reg = <0x20030010 0x10>;
 172                 #pwm-cells = <2>;
 173                 clocks = <&cru PCLK_PWM01>;
 174                 status = "disabled";
 175         };
 176
 177         pwm2: pwm@20050020 {
 178                 compatible = "rockchip,rk2928-pwm";
 179                 reg = <0x20050020 0x10>;
 180                 #pwm-cells = <2>;
 181                 clocks = <&cru PCLK_PWM23>;
 182                 status = "disabled";
 183         };
 184
 185         pwm3: pwm@20050030 {
 186                 compatible = "rockchip,rk2928-pwm";
 187                 reg = <0x20050030 0x10>;
 188                 #pwm-cells = <2>;
 189                 clocks = <&cru PCLK_PWM23>;
 190                 status = "disabled";
 191         };
 192
 193         i2c2: i2c@20056000 {
 194                 compatible = "rockchip,rk3066-i2c";
 195                 reg = <0x20056000 0x1000>;
 196                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199
 200                 rockchip,grf = <&grf>;
 201
 202                 clocks = <&cru PCLK_I2C2>;
 203                 clock-names = "i2c";
 204
 205                 status = "disabled";
 206         };
 207
 208         i2c3: i2c@2005a000 {
 209                 compatible = "rockchip,rk3066-i2c";
 210                 reg = <0x2005a000 0x1000>;
 211                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214
 215                 rockchip,grf = <&grf>;
 216
 217                 clocks = <&cru PCLK_I2C3>;
 218                 clock-names = "i2c";
 219
 220                 status = "disabled";
 221         };
 222
 223         i2c4: i2c@2005e000 {
 224                 compatible = "rockchip,rk3066-i2c";
 225                 reg = <0x2005e000 0x1000>;
 226                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229
 230                 rockchip,grf = <&grf>;
 231
 232                 clocks = <&cru PCLK_I2C4>;
 233                 clock-names = "i2c";
 234
 235                 status = "disabled";
 236         };
 237
 238         uart2: serial@20064000 {
 239                 compatible = "snps,dw-apb-uart";
 240                 reg = <0x20064000 0x400>;
 241                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 242                 reg-shift = <2>;
 243                 reg-io-width = <1>;
 244                 clock-names = "baudclk", "apb_pclk";
 245                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 246                 status = "disabled";
 247         };
 248
 249         uart3: serial@20068000 {
 250                 compatible = "snps,dw-apb-uart";
 251                 reg = <0x20068000 0x400>;
 252                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 253                 reg-shift = <2>;
 254                 reg-io-width = <1>;
 255                 clock-names = "baudclk", "apb_pclk";
 256                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 257                 status = "disabled";
 258         };
 259 };