arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         xin24m: oscillator {
  24                 compatible = "fixed-clock";
  25                 clock-frequency = <24000000>;
  26                 #clock-cells = <0>;
  27                 clock-output-names = "xin24m";
  28         };
  29
  30         soc {
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 compatible = "simple-bus";
  34                 ranges;
  35
  36                 scu@1013c000 {
  37                         compatible = "arm,cortex-a9-scu";
  38                         reg = <0x1013c000 0x100>;
  39                 };
  40
  41                 pmu: pmu@20004000 {
  42                         compatible = "rockchip,rk3066-pmu", "syscon";
  43                         reg = <0x20004000 0x100>;
  44                 };
  45
  46                 grf: grf@20008000 {
  47                         compatible = "syscon";
  48                         reg = <0x20008000 0x200>;
  49                 };
  50
  51                 gic: interrupt-controller@1013d000 {
  52                         compatible = "arm,cortex-a9-gic";
  53                         interrupt-controller;
  54                         #interrupt-cells = <3>;
  55                         reg = <0x1013d000 0x1000>,
  56                               <0x1013c100 0x0100>;
  57                 };
  58
  59                 L2: l2-cache-controller@10138000 {
  60                         compatible = "arm,pl310-cache";
  61                         reg = <0x10138000 0x1000>;
  62                         cache-unified;
  63                         cache-level = <2>;
  64                 };
  65
  66                 global-timer@1013c200 {
  67                         compatible = "arm,cortex-a9-global-timer";
  68                         reg = <0x1013c200 0x20>;
  69                         interrupts = <GIC_PPI 11 0x304>;
  70                         clocks = <&cru CORE_PERI>;
  71                 };
  72
  73                 local-timer@1013c600 {
  74                         compatible = "arm,cortex-a9-twd-timer";
  75                         reg = <0x1013c600 0x20>;
  76                         interrupts = <GIC_PPI 13 0x304>;
  77                         clocks = <&cru CORE_PERI>;
  78                 };
  79
  80                 uart0: serial@10124000 {
  81                         compatible = "snps,dw-apb-uart";
  82                         reg = <0x10124000 0x400>;
  83                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  84                         reg-shift = <2>;
  85                         reg-io-width = <1>;
  86                         clocks = <&cru SCLK_UART0>;
  87                         status = "disabled";
  88                 };
  89
  90                 uart1: serial@10126000 {
  91                         compatible = "snps,dw-apb-uart";
  92                         reg = <0x10126000 0x400>;
  93                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  94                         reg-shift = <2>;
  95                         reg-io-width = <1>;
  96                         clocks = <&cru SCLK_UART1>;
  97                         status = "disabled";
  98                 };
  99
 100                 uart2: serial@20064000 {
 101                         compatible = "snps,dw-apb-uart";
 102                         reg = <0x20064000 0x400>;
 103                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 104                         reg-shift = <2>;
 105                         reg-io-width = <1>;
 106                         clocks = <&cru SCLK_UART2>;
 107                         status = "disabled";
 108                 };
 109
 110                 uart3: serial@20068000 {
 111                         compatible = "snps,dw-apb-uart";
 112                         reg = <0x20068000 0x400>;
 113                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 114                         reg-shift = <2>;
 115                         reg-io-width = <1>;
 116                         clocks = <&cru SCLK_UART3>;
 117                         status = "disabled";
 118                 };
 119
 120                 dwmmc@10214000 {
 121                         compatible = "rockchip,rk2928-dw-mshc";
 122                         reg = <0x10214000 0x1000>;
 123                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126
 127                         clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 128                         clock-names = "biu", "ciu";
 129
 130                         status = "disabled";
 131                 };
 132
 133                 dwmmc@10218000 {
 134                         compatible = "rockchip,rk2928-dw-mshc";
 135                         reg = <0x10218000 0x1000>;
 136                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139
 140                         clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 141                         clock-names = "biu", "ciu";
 142
 143                         status = "disabled";
 144                 };
 145         };
 146 };