arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         soc {
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26                 compatible = "simple-bus";
  27                 ranges;
  28
  29                 scu@1013c000 {
  30                         compatible = "arm,cortex-a9-scu";
  31                         reg = <0x1013c000 0x100>;
  32                 };
  33
  34                 pmu: pmu@20004000 {
  35                         compatible = "rockchip,rk3066-pmu", "syscon";
  36                         reg = <0x20004000 0x100>;
  37                 };
  38
  39                 grf: grf@20008000 {
  40                         compatible = "syscon";
  41                         reg = <0x20008000 0x200>;
  42                 };
  43
  44                 gic: interrupt-controller@1013d000 {
  45                         compatible = "arm,cortex-a9-gic";
  46                         interrupt-controller;
  47                         #interrupt-cells = <3>;
  48                         reg = <0x1013d000 0x1000>,
  49                               <0x1013c100 0x0100>;
  50                 };
  51
  52                 L2: l2-cache-controller@10138000 {
  53                         compatible = "arm,pl310-cache";
  54                         reg = <0x10138000 0x1000>;
  55                         cache-unified;
  56                         cache-level = <2>;
  57                 };
  58
  59                 global-timer@1013c200 {
  60                         compatible = "arm,cortex-a9-global-timer";
  61                         reg = <0x1013c200 0x20>;
  62                         interrupts = <GIC_PPI 11 0x304>;
  63                         clocks = <&dummy150m>;
  64                 };
  65
  66                 local-timer@1013c600 {
  67                         compatible = "arm,cortex-a9-twd-timer";
  68                         reg = <0x1013c600 0x20>;
  69                         interrupts = <GIC_PPI 13 0x304>;
  70                         clocks = <&dummy150m>;
  71                 };
  72
  73                 uart0: serial@10124000 {
  74                         compatible = "snps,dw-apb-uart";
  75                         reg = <0x10124000 0x400>;
  76                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  77                         reg-shift = <2>;
  78                         reg-io-width = <1>;
  79                         clocks = <&clk_gates1 8>;
  80                         status = "disabled";
  81                 };
  82
  83                 uart1: serial@10126000 {
  84                         compatible = "snps,dw-apb-uart";
  85                         reg = <0x10126000 0x400>;
  86                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  87                         reg-shift = <2>;
  88                         reg-io-width = <1>;
  89                         clocks = <&clk_gates1 10>;
  90                         status = "disabled";
  91                 };
  92
  93                 uart2: serial@20064000 {
  94                         compatible = "snps,dw-apb-uart";
  95                         reg = <0x20064000 0x400>;
  96                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  97                         reg-shift = <2>;
  98                         reg-io-width = <1>;
  99                         clocks = <&clk_gates1 12>;
 100                         status = "disabled";
 101                 };
 102
 103                 uart3: serial@20068000 {
 104                         compatible = "snps,dw-apb-uart";
 105                         reg = <0x20068000 0x400>;
 106                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 107                         reg-shift = <2>;
 108                         reg-io-width = <1>;
 109                         clocks = <&clk_gates1 14>;
 110                         status = "disabled";
 111                 };
 112
 113                 dwmmc@10214000 {
 114                         compatible = "rockchip,rk2928-dw-mshc";
 115                         reg = <0x10214000 0x1000>;
 116                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119
 120                         clocks = <&clk_gates5 10>, <&clk_gates2 11>;
 121                         clock-names = "biu", "ciu";
 122
 123                         status = "disabled";
 124                 };
 125
 126                 dwmmc@10218000 {
 127                         compatible = "rockchip,rk2928-dw-mshc";
 128                         reg = <0x10218000 0x1000>;
 129                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132
 133                         clocks = <&clk_gates5 11>, <&clk_gates2 13>;
 134                         clock-names = "biu", "ciu";
 135
 136                         status = "disabled";
 137                 };
 138         };
 139 };